2 * ALSA SoC TLV320AIC3X codec driver
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 /* AIC3X register space */
16 #define AIC3X_CACHEREGNUM 103
18 /* Page select register */
19 #define AIC3X_PAGE_SELECT 0
20 /* Software reset register */
22 /* Codec Sample rate select register */
23 #define AIC3X_SAMPLE_RATE_SEL_REG 2
24 /* PLL progrramming register A */
25 #define AIC3X_PLL_PROGA_REG 3
26 /* PLL progrramming register B */
27 #define AIC3X_PLL_PROGB_REG 4
28 /* PLL progrramming register C */
29 #define AIC3X_PLL_PROGC_REG 5
30 /* PLL progrramming register D */
31 #define AIC3X_PLL_PROGD_REG 6
32 /* Codec datapath setup register */
33 #define AIC3X_CODEC_DATAPATH_REG 7
34 /* Audio serial data interface control register A */
35 #define AIC3X_ASD_INTF_CTRLA 8
36 /* Audio serial data interface control register B */
37 #define AIC3X_ASD_INTF_CTRLB 9
38 /* Audio overflow status and PLL R value programming register */
39 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
40 /* Audio codec digital filter control register */
41 #define AIC3X_CODEC_DFILT_CTRL 12
42 /* Headset/button press detection register */
43 #define AIC3X_HEADSET_DETECT_CTRL_A 13
44 #define AIC3X_HEADSET_DETECT_CTRL_B 14
45 /* ADC PGA Gain control registers */
48 /* MIC3 control registers */
49 #define MIC3LR_2_LADC_CTRL 17
50 #define MIC3LR_2_RADC_CTRL 18
51 /* Line1 Input control registers */
52 #define LINE1L_2_LADC_CTRL 19
53 #define LINE1R_2_LADC_CTRL 21
54 #define LINE1R_2_RADC_CTRL 22
55 #define LINE1L_2_RADC_CTRL 24
56 /* Line2 Input control registers */
57 #define LINE2L_2_LADC_CTRL 20
58 #define LINE2R_2_RADC_CTRL 23
59 /* MICBIAS Control Register */
60 #define MICBIAS_CTRL 25
62 /* AGC Control Registers A, B, C */
63 #define LAGC_CTRL_A 26
64 #define LAGC_CTRL_B 27
65 #define LAGC_CTRL_C 28
66 #define RAGC_CTRL_A 29
67 #define RAGC_CTRL_B 30
68 #define RAGC_CTRL_C 31
70 /* DAC Power and Left High Power Output control registers */
73 /* Right High Power Output control registers */
75 /* DAC Output Switching control registers */
76 #define DAC_LINE_MUX 41
77 /* High Power Output Driver Pop Reduction registers */
78 #define HPOUT_POP_REDUCTION 42
79 /* DAC Digital control registers */
82 /* High Power Output control registers */
83 #define LINE2L_2_HPLOUT_VOL 45
84 #define LINE2R_2_HPROUT_VOL 62
85 #define PGAL_2_HPLOUT_VOL 46
86 #define PGAL_2_HPROUT_VOL 60
87 #define PGAR_2_HPLOUT_VOL 49
88 #define PGAR_2_HPROUT_VOL 63
89 #define DACL1_2_HPLOUT_VOL 47
90 #define DACR1_2_HPROUT_VOL 64
91 #define HPLOUT_CTRL 51
92 #define HPROUT_CTRL 65
93 /* High Power COM control registers */
94 #define LINE2L_2_HPLCOM_VOL 52
95 #define LINE2R_2_HPRCOM_VOL 69
96 #define PGAL_2_HPLCOM_VOL 53
97 #define PGAR_2_HPLCOM_VOL 56
98 #define PGAL_2_HPRCOM_VOL 67
99 #define PGAR_2_HPRCOM_VOL 70
100 #define DACL1_2_HPLCOM_VOL 54
101 #define DACR1_2_HPRCOM_VOL 71
102 #define HPLCOM_CTRL 58
103 #define HPRCOM_CTRL 72
104 /* Mono Line Output Plus/Minus control registers */
105 #define LINE2L_2_MONOLOPM_VOL 73
106 #define LINE2R_2_MONOLOPM_VOL 76
107 #define PGAL_2_MONOLOPM_VOL 74
108 #define PGAR_2_MONOLOPM_VOL 77
109 #define DACL1_2_MONOLOPM_VOL 75
110 #define DACR1_2_MONOLOPM_VOL 78
111 #define MONOLOPM_CTRL 79
112 /* Line Output Plus/Minus control registers */
113 #define LINE2L_2_LLOPM_VOL 80
114 #define LINE2L_2_RLOPM_VOL 87
115 #define LINE2R_2_LLOPM_VOL 83
116 #define LINE2R_2_RLOPM_VOL 90
117 #define PGAL_2_LLOPM_VOL 81
118 #define PGAL_2_RLOPM_VOL 88
119 #define PGAR_2_LLOPM_VOL 84
120 #define PGAR_2_RLOPM_VOL 91
121 #define DACL1_2_LLOPM_VOL 82
122 #define DACL1_2_RLOPM_VOL 89
123 #define DACR1_2_RLOPM_VOL 92
124 #define DACR1_2_LLOPM_VOL 85
125 #define LLOPM_CTRL 86
126 #define RLOPM_CTRL 93
127 /* GPIO/IRQ registers */
128 #define AIC3X_STICKY_IRQ_FLAGS_REG 96
129 #define AIC3X_RT_IRQ_FLAGS_REG 97
130 #define AIC3X_GPIO1_REG 98
131 #define AIC3X_GPIO2_REG 99
132 #define AIC3X_GPIOA_REG 100
133 #define AIC3X_GPIOB_REG 101
134 /* Clock generation control register */
135 #define AIC3X_CLKGEN_CTRL_REG 102
137 /* Page select register bits */
138 #define PAGE0_SELECT 0
139 #define PAGE1_SELECT 1
141 /* Audio serial data interface control register A bits */
142 #define BIT_CLK_MASTER 0x80
143 #define WORD_CLK_MASTER 0x40
145 /* Codec Datapath setup register 7 */
146 #define FSREF_44100 (1 << 7)
147 #define FSREF_48000 (0 << 7)
148 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
149 #define LDAC2LCH (0x1 << 3)
150 #define RDAC2RCH (0x1 << 1)
152 /* PLL registers bitfields */
157 #define PLLD_MSB_SHIFT 0
158 #define PLLD_LSB_SHIFT 2
160 /* Clock generation register bits */
161 #define CODEC_CLKIN_PLLDIV 0
162 #define CODEC_CLKIN_CLKDIV 1
163 #define PLL_CLKIN_SHIFT 4
164 #define MCLK_SOURCE 0x0
165 #define PLL_CLKDIV_SHIFT 0
167 /* Software reset register bits */
168 #define SOFT_RESET 0x80
170 /* PLL progrramming register A bits */
171 #define PLL_ENABLE 0x80
174 #define ROUTE_ON 0x80
181 #define LADC_PWR_ON 0x04
182 #define RADC_PWR_ON 0x04
183 #define LDAC_PWR_ON 0x80
184 #define RDAC_PWR_ON 0x40
185 #define HPLOUT_PWR_ON 0x01
186 #define HPROUT_PWR_ON 0x01
187 #define HPLCOM_PWR_ON 0x01
188 #define HPRCOM_PWR_ON 0x01
189 #define MONOLOPM_PWR_ON 0x01
190 #define LLOPM_PWR_ON 0x01
191 #define RLOPM_PWR_ON 0x01
193 #define INVERT_VOL(val) (0x7f - val)
195 /* Default output volume (inverted) */
196 #define DEFAULT_VOL INVERT_VOL(0x50)
197 /* Default input volume */
198 #define DEFAULT_GAIN 0x20
202 AIC3X_GPIO1_FUNC_DISABLED = 0,
203 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,
204 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,
205 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,
206 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,
207 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,
208 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,
209 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,
210 AIC3X_GPIO1_FUNC_INPUT = 8,
211 AIC3X_GPIO1_FUNC_OUTPUT = 9,
212 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,
213 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,
214 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,
215 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,
216 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,
217 AIC3X_GPIO1_FUNC_ALL_IRQ = 16
221 AIC3X_GPIO2_FUNC_DISABLED = 0,
222 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,
223 AIC3X_GPIO2_FUNC_INPUT = 3,
224 AIC3X_GPIO2_FUNC_OUTPUT = 4,
225 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,
226 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,
227 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
228 AIC3X_GPIO2_FUNC_ALL_IRQ = 10,
229 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
230 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
231 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,
232 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,
233 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15
236 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
237 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
239 /* headset detection / button API */
241 /* The AIC3x supports detection of stereo headsets (GND + left + right signal)
242 * and cellular headsets (GND + speaker output + microphone input).
243 * It is recommended to enable MIC bias for this function to work properly.
244 * For more information, please refer to the datasheet. */
246 AIC3X_HEADSET_DETECT_OFF = 0,
247 AIC3X_HEADSET_DETECT_STEREO = 1,
248 AIC3X_HEADSET_DETECT_CELLULAR = 2,
249 AIC3X_HEADSET_DETECT_BOTH = 3
253 AIC3X_HEADSET_DEBOUNCE_16MS = 0,
254 AIC3X_HEADSET_DEBOUNCE_32MS = 1,
255 AIC3X_HEADSET_DEBOUNCE_64MS = 2,
256 AIC3X_HEADSET_DEBOUNCE_128MS = 3,
257 AIC3X_HEADSET_DEBOUNCE_256MS = 4,
258 AIC3X_HEADSET_DEBOUNCE_512MS = 5
262 AIC3X_BUTTON_DEBOUNCE_0MS = 0,
263 AIC3X_BUTTON_DEBOUNCE_8MS = 1,
264 AIC3X_BUTTON_DEBOUNCE_16MS = 2,
265 AIC3X_BUTTON_DEBOUNCE_32MS = 3
268 #define AIC3X_HEADSET_DETECT_ENABLED 0x80
269 #define AIC3X_HEADSET_DETECT_SHIFT 5
270 #define AIC3X_HEADSET_DETECT_MASK 3
271 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
272 #define AIC3X_HEADSET_DEBOUNCE_MASK 7
273 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
274 #define AIC3X_BUTTON_DEBOUNCE_MASK 3
276 /* see the enums above for valid parameters to this function */
277 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
278 int headset_debounce, int button_debounce);
279 int aic3x_headset_detected(struct snd_soc_codec *codec);
280 int aic3x_button_pressed(struct snd_soc_codec *codec);
282 struct aic3x_setup_data {
284 unsigned short i2c_address;
285 unsigned int gpio_func[2];
288 extern struct snd_soc_dai aic3x_dai;
289 extern struct snd_soc_codec_device soc_codec_dev_aic3x;
291 #endif /* _AIC3X_H */