sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/soc-dapm.h>
  40 #include <sound/initval.h>
  41 #include <sound/tlv.h>
  42
  43 #include <sound/tlv320dac33-plat.h>
  44 #include "tlv320dac33.h"
  45
  46 #define DAC33_BUFFER_SIZE_BYTES         24576   /* bytes, 12288 16 bit words,
  47                                                  * 6144 stereo */
  48 #define DAC33_BUFFER_SIZE_SAMPLES       6144
  49
  50 #define NSAMPLE_MAX             5700
  51
  52 #define MODE7_LTHR              10
  53 #define MODE7_UTHR              (DAC33_BUFFER_SIZE_SAMPLES - 10)
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / us))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         unsigned int nsample_min;       /* nsample should not be lower than
 104                                          * this */
 105         unsigned int nsample_max;       /* nsample should not be higher than
 106                                          * this */
 107         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 108         unsigned int nsample;           /* burst read amount from host */
 109         int mode1_latency;              /* latency caused by the i2c writes in
 110                                          * us */
 111         int auto_fifo_config;           /* Configure the FIFO based on the
 112                                          * period size */
 113         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 114         unsigned int burst_rate;        /* Interface speed in Burst modes */
 115
 116         int keep_bclk;                  /* Keep the BCLK continuously running
 117                                          * in FIFO modes */
 118         spinlock_t lock;
 119         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 120         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 121
 122         unsigned int mode1_us_burst;    /* Time to burst read n number of
 123                                          * samples */
 124         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 125
 126         unsigned int uthr;
 127
 128         enum dac33_state state;
 129         enum snd_soc_control_type control_type;
 130         void *control_data;
 131 };
 132
 133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 148 0x00, 0x00,             /* 0x38 - 0x39 */
 149 /* Registers 0x3a - 0x3f are reserved  */
 150             0x00, 0x00, /* 0x3a - 0x3b */
 151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 152
 153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 154 0x00, 0x80,             /* 0x44 - 0x45 */
 155 /* Registers 0x46 - 0x47 are reserved  */
 156             0x80, 0x80, /* 0x46 - 0x47 */
 157
 158 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 159 /* Registers 0x4b - 0x7c are reserved  */
 160                   0x00, /* 0x4b        */
 161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 173 0x00,                   /* 0x7c        */
 174
 175       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 176 };
 177
 178 /* Register read and write */
 179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 180                                                 unsigned reg)
 181 {
 182         u8 *cache = codec->reg_cache;
 183         if (reg >= DAC33_CACHEREGNUM)
 184                 return 0;
 185
 186         return cache[reg];
 187 }
 188
 189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 190                                          u8 reg, u8 value)
 191 {
 192         u8 *cache = codec->reg_cache;
 193         if (reg >= DAC33_CACHEREGNUM)
 194                 return;
 195
 196         cache[reg] = value;
 197 }
 198
 199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 200                       u8 *value)
 201 {
 202         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 203         int val;
 204
 205         *value = reg & 0xff;
 206
 207         /* If powered off, return the cached value */
 208         if (dac33->chip_power) {
 209                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 210                 if (val < 0) {
 211                         dev_err(codec->dev, "Read failed (%d)\n", val);
 212                         value[0] = dac33_read_reg_cache(codec, reg);
 213                 } else {
 214                         value[0] = val;
 215                         dac33_write_reg_cache(codec, reg, val);
 216                 }
 217         } else {
 218                 value[0] = dac33_read_reg_cache(codec, reg);
 219         }
 220
 221         return 0;
 222 }
 223
 224 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 225                        unsigned int value)
 226 {
 227         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 228         u8 data[2];
 229         int ret = 0;
 230
 231         /*
 232          * data is
 233          *   D15..D8 dac33 register offset
 234          *   D7...D0 register data
 235          */
 236         data[0] = reg & 0xff;
 237         data[1] = value & 0xff;
 238
 239         dac33_write_reg_cache(codec, data[0], data[1]);
 240         if (dac33->chip_power) {
 241                 ret = codec->hw_write(codec->control_data, data, 2);
 242                 if (ret != 2)
 243                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 244                 else
 245                         ret = 0;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 252                        unsigned int value)
 253 {
 254         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 255         int ret;
 256
 257         mutex_lock(&dac33->mutex);
 258         ret = dac33_write(codec, reg, value);
 259         mutex_unlock(&dac33->mutex);
 260
 261         return ret;
 262 }
 263
 264 #define DAC33_I2C_ADDR_AUTOINC  0x80
 265 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 266                        unsigned int value)
 267 {
 268         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 269         u8 data[3];
 270         int ret = 0;
 271
 272         /*
 273          * data is
 274          *   D23..D16 dac33 register offset
 275          *   D15..D8  register data MSB
 276          *   D7...D0  register data LSB
 277          */
 278         data[0] = reg & 0xff;
 279         data[1] = (value >> 8) & 0xff;
 280         data[2] = value & 0xff;
 281
 282         dac33_write_reg_cache(codec, data[0], data[1]);
 283         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 284
 285         if (dac33->chip_power) {
 286                 /* We need to set autoincrement mode for 16 bit writes */
 287                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 288                 ret = codec->hw_write(codec->control_data, data, 3);
 289                 if (ret != 3)
 290                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 291                 else
 292                         ret = 0;
 293         }
 294
 295         return ret;
 296 }
 297
 298 static void dac33_init_chip(struct snd_soc_codec *codec)
 299 {
 300         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 301
 302         if (unlikely(!dac33->chip_power))
 303                 return;
 304
 305         /* 44-46: DAC Control Registers */
 306         /* A : DAC sample rate Fsref/1.5 */
 307         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 308         /* B : DAC src=normal, not muted */
 309         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 310                                              DAC33_DACSRCL_LEFT);
 311         /* C : (defaults) */
 312         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 313
 314         /* 73 : volume soft stepping control,
 315          clock source = internal osc (?) */
 316         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 317
 318         dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
 319
 320         /* Restore only selected registers (gains mostly) */
 321         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 322                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 323         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 324                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 325
 326         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 327                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 328         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 329                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 330 }
 331
 332 static inline void dac33_read_id(struct snd_soc_codec *codec)
 333 {
 334         u8 reg;
 335
 336         dac33_read(codec, DAC33_DEVICE_ID_MSB, &reg);
 337         dac33_read(codec, DAC33_DEVICE_ID_LSB, &reg);
 338         dac33_read(codec, DAC33_DEVICE_REV_ID, &reg);
 339 }
 340
 341 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 342 {
 343         u8 reg;
 344
 345         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 346         if (power)
 347                 reg |= DAC33_PDNALLB;
 348         else
 349                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 350                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 351         dac33_write(codec, DAC33_PWR_CTRL, reg);
 352 }
 353
 354 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 355 {
 356         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 357         int ret = 0;
 358
 359         mutex_lock(&dac33->mutex);
 360
 361         /* Safety check */
 362         if (unlikely(power == dac33->chip_power)) {
 363                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 364                         power ? "ON" : "OFF");
 365                 goto exit;
 366         }
 367
 368         if (power) {
 369                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 370                                           dac33->supplies);
 371                 if (ret != 0) {
 372                         dev_err(codec->dev,
 373                                 "Failed to enable supplies: %d\n", ret);
 374                                 goto exit;
 375                 }
 376
 377                 if (dac33->power_gpio >= 0)
 378                         gpio_set_value(dac33->power_gpio, 1);
 379
 380                 dac33->chip_power = 1;
 381         } else {
 382                 dac33_soft_power(codec, 0);
 383                 if (dac33->power_gpio >= 0)
 384                         gpio_set_value(dac33->power_gpio, 0);
 385
 386                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 387                                              dac33->supplies);
 388                 if (ret != 0) {
 389                         dev_err(codec->dev,
 390                                 "Failed to disable supplies: %d\n", ret);
 391                         goto exit;
 392                 }
 393
 394                 dac33->chip_power = 0;
 395         }
 396
 397 exit:
 398         mutex_unlock(&dac33->mutex);
 399         return ret;
 400 }
 401
 402 static int playback_event(struct snd_soc_dapm_widget *w,
 403                 struct snd_kcontrol *kcontrol, int event)
 404 {
 405         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 406
 407         switch (event) {
 408         case SND_SOC_DAPM_PRE_PMU:
 409                 if (likely(dac33->substream)) {
 410                         dac33_calculate_times(dac33->substream);
 411                         dac33_prepare_chip(dac33->substream);
 412                 }
 413                 break;
 414         }
 415         return 0;
 416 }
 417
 418 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
 419                          struct snd_ctl_elem_value *ucontrol)
 420 {
 421         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 422         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 423
 424         ucontrol->value.integer.value[0] = dac33->nsample;
 425
 426         return 0;
 427 }
 428
 429 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
 430                          struct snd_ctl_elem_value *ucontrol)
 431 {
 432         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 433         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 434         int ret = 0;
 435
 436         if (dac33->nsample == ucontrol->value.integer.value[0])
 437                 return 0;
 438
 439         if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
 440             ucontrol->value.integer.value[0] > dac33->nsample_max) {
 441                 ret = -EINVAL;
 442         } else {
 443                 dac33->nsample = ucontrol->value.integer.value[0];
 444                 /* Re calculate the burst time */
 445                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
 446                                                       dac33->nsample);
 447         }
 448
 449         return ret;
 450 }
 451
 452 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
 453                          struct snd_ctl_elem_value *ucontrol)
 454 {
 455         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 456         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 457
 458         ucontrol->value.integer.value[0] = dac33->uthr;
 459
 460         return 0;
 461 }
 462
 463 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
 464                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 468         int ret = 0;
 469
 470         if (dac33->substream)
 471                 return -EBUSY;
 472
 473         if (dac33->uthr == ucontrol->value.integer.value[0])
 474                 return 0;
 475
 476         if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
 477             ucontrol->value.integer.value[0] > MODE7_UTHR)
 478                 ret = -EINVAL;
 479         else
 480                 dac33->uthr = ucontrol->value.integer.value[0];
 481
 482         return ret;
 483 }
 484
 485 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 486                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 490
 491         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 492
 493         return 0;
 494 }
 495
 496 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 497                          struct snd_ctl_elem_value *ucontrol)
 498 {
 499         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 500         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 501         int ret = 0;
 502
 503         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 504                 return 0;
 505         /* Do not allow changes while stream is running*/
 506         if (codec->active)
 507                 return -EPERM;
 508
 509         if (ucontrol->value.integer.value[0] < 0 ||
 510             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 511                 ret = -EINVAL;
 512         else
 513                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 514
 515         return ret;
 516 }
 517
 518 /* Codec operation modes */
 519 static const char *dac33_fifo_mode_texts[] = {
 520         "Bypass", "Mode 1", "Mode 7"
 521 };
 522
 523 static const struct soc_enum dac33_fifo_mode_enum =
 524         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 525                             dac33_fifo_mode_texts);
 526
 527 /*
 528  * DACL/R digital volume control:
 529  * from 0 dB to -63.5 in 0.5 dB steps
 530  * Need to be inverted later on:
 531  * 0x00 == 0 dB
 532  * 0x7f == -63.5 dB
 533  */
 534 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 535
 536 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 537         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 538                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 539                 0, 0x7f, 1, dac_digivol_tlv),
 540         SOC_DOUBLE_R("DAC Digital Playback Switch",
 541                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 542         SOC_DOUBLE_R("Line to Line Out Volume",
 543                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 544 };
 545
 546 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 547         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 548                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 549 };
 550
 551 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
 552         SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
 553                 dac33_get_nsample, dac33_set_nsample),
 554         SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
 555                  dac33_get_uthr, dac33_set_uthr),
 556 };
 557
 558 /* Analog bypass */
 559 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 560         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 561
 562 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 563         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 564
 565 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 566         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 567         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 568
 569         SND_SOC_DAPM_INPUT("LINEL"),
 570         SND_SOC_DAPM_INPUT("LINER"),
 571
 572         SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
 573         SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
 574
 575         /* Analog bypass */
 576         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 577                                 &dac33_dapm_abypassl_control),
 578         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 579                                 &dac33_dapm_abypassr_control),
 580
 581         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
 582                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 583         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
 584                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 585
 586         SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
 587 };
 588
 589 static const struct snd_soc_dapm_route audio_map[] = {
 590         /* Analog bypass */
 591         {"Analog Left Bypass", "Switch", "LINEL"},
 592         {"Analog Right Bypass", "Switch", "LINER"},
 593
 594         {"Output Left Amp Power", NULL, "DACL"},
 595         {"Output Right Amp Power", NULL, "DACR"},
 596
 597         {"Output Left Amp Power", NULL, "Analog Left Bypass"},
 598         {"Output Right Amp Power", NULL, "Analog Right Bypass"},
 599
 600         /* output */
 601         {"LEFT_LO", NULL, "Output Left Amp Power"},
 602         {"RIGHT_LO", NULL, "Output Right Amp Power"},
 603 };
 604
 605 static int dac33_add_widgets(struct snd_soc_codec *codec)
 606 {
 607         snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
 608                                   ARRAY_SIZE(dac33_dapm_widgets));
 609
 610         /* set up audio path interconnects */
 611         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 612
 613         return 0;
 614 }
 615
 616 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 617                                 enum snd_soc_bias_level level)
 618 {
 619         int ret;
 620
 621         switch (level) {
 622         case SND_SOC_BIAS_ON:
 623                 dac33_soft_power(codec, 1);
 624                 break;
 625         case SND_SOC_BIAS_PREPARE:
 626                 break;
 627         case SND_SOC_BIAS_STANDBY:
 628                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 629                         /* Coming from OFF, switch on the codec */
 630                         ret = dac33_hard_power(codec, 1);
 631                         if (ret != 0)
 632                                 return ret;
 633
 634                         dac33_init_chip(codec);
 635                 }
 636                 break;
 637         case SND_SOC_BIAS_OFF:
 638                 /* Do not power off, when the codec is already off */
 639                 if (codec->bias_level == SND_SOC_BIAS_OFF)
 640                         return 0;
 641                 ret = dac33_hard_power(codec, 0);
 642                 if (ret != 0)
 643                         return ret;
 644                 break;
 645         }
 646         codec->bias_level = level;
 647
 648         return 0;
 649 }
 650
 651 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 652 {
 653         struct snd_soc_codec *codec = dac33->codec;
 654
 655         switch (dac33->fifo_mode) {
 656         case DAC33_FIFO_MODE1:
 657                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 658                         DAC33_THRREG(dac33->nsample));
 659
 660                 /* Take the timestamps */
 661                 spin_lock_irq(&dac33->lock);
 662                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 663                 dac33->t_stamp1 = dac33->t_stamp2;
 664                 spin_unlock_irq(&dac33->lock);
 665
 666                 dac33_write16(codec, DAC33_PREFILL_MSB,
 667                                 DAC33_THRREG(dac33->alarm_threshold));
 668                 /* Enable Alarm Threshold IRQ with a delay */
 669                 udelay(SAMPLES_TO_US(dac33->burst_rate,
 670                                      dac33->alarm_threshold));
 671                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 672                 break;
 673         case DAC33_FIFO_MODE7:
 674                 /* Take the timestamp */
 675                 spin_lock_irq(&dac33->lock);
 676                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 677                 /* Move back the timestamp with drain time */
 678                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 679                 spin_unlock_irq(&dac33->lock);
 680
 681                 dac33_write16(codec, DAC33_PREFILL_MSB,
 682                                 DAC33_THRREG(MODE7_LTHR));
 683
 684                 /* Enable Upper Threshold IRQ */
 685                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 686                 break;
 687         default:
 688                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 689                                                         dac33->fifo_mode);
 690                 break;
 691         }
 692 }
 693
 694 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 695 {
 696         struct snd_soc_codec *codec = dac33->codec;
 697
 698         switch (dac33->fifo_mode) {
 699         case DAC33_FIFO_MODE1:
 700                 /* Take the timestamp */
 701                 spin_lock_irq(&dac33->lock);
 702                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 703                 spin_unlock_irq(&dac33->lock);
 704
 705                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 706                                 DAC33_THRREG(dac33->nsample));
 707                 break;
 708         case DAC33_FIFO_MODE7:
 709                 /* At the moment we are not using interrupts in mode7 */
 710                 break;
 711         default:
 712                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 713                                                         dac33->fifo_mode);
 714                 break;
 715         }
 716 }
 717
 718 static void dac33_work(struct work_struct *work)
 719 {
 720         struct snd_soc_codec *codec;
 721         struct tlv320dac33_priv *dac33;
 722         u8 reg;
 723
 724         dac33 = container_of(work, struct tlv320dac33_priv, work);
 725         codec = dac33->codec;
 726
 727         mutex_lock(&dac33->mutex);
 728         switch (dac33->state) {
 729         case DAC33_PREFILL:
 730                 dac33->state = DAC33_PLAYBACK;
 731                 dac33_prefill_handler(dac33);
 732                 break;
 733         case DAC33_PLAYBACK:
 734                 dac33_playback_handler(dac33);
 735                 break;
 736         case DAC33_IDLE:
 737                 break;
 738         case DAC33_FLUSH:
 739                 dac33->state = DAC33_IDLE;
 740                 /* Mask all interrupts from dac33 */
 741                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 742
 743                 /* flush fifo */
 744                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 745                 reg |= DAC33_FIFOFLUSH;
 746                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 747                 break;
 748         }
 749         mutex_unlock(&dac33->mutex);
 750 }
 751
 752 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 753 {
 754         struct snd_soc_codec *codec = dev;
 755         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 756
 757         spin_lock(&dac33->lock);
 758         dac33->t_stamp1 = ktime_to_us(ktime_get());
 759         spin_unlock(&dac33->lock);
 760
 761         /* Do not schedule the workqueue in Mode7 */
 762         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 763                 queue_work(dac33->dac33_wq, &dac33->work);
 764
 765         return IRQ_HANDLED;
 766 }
 767
 768 static void dac33_oscwait(struct snd_soc_codec *codec)
 769 {
 770         int timeout = 20;
 771         u8 reg;
 772
 773         do {
 774                 msleep(1);
 775                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 776         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 777         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 778                 dev_err(codec->dev,
 779                         "internal oscillator calibration failed\n");
 780 }
 781
 782 static int dac33_startup(struct snd_pcm_substream *substream,
 783                            struct snd_soc_dai *dai)
 784 {
 785         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 786         struct snd_soc_codec *codec = rtd->codec;
 787         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 788
 789         /* Stream started, save the substream pointer */
 790         dac33->substream = substream;
 791
 792         return 0;
 793 }
 794
 795 static void dac33_shutdown(struct snd_pcm_substream *substream,
 796                              struct snd_soc_dai *dai)
 797 {
 798         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 799         struct snd_soc_codec *codec = rtd->codec;
 800         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 801
 802         dac33->substream = NULL;
 803
 804         /* Reset the nSample restrictions */
 805         dac33->nsample_min = 0;
 806         dac33->nsample_max = NSAMPLE_MAX;
 807 }
 808
 809 static int dac33_hw_params(struct snd_pcm_substream *substream,
 810                            struct snd_pcm_hw_params *params,
 811                            struct snd_soc_dai *dai)
 812 {
 813         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 814         struct snd_soc_codec *codec = rtd->codec;
 815
 816         /* Check parameters for validity */
 817         switch (params_rate(params)) {
 818         case 44100:
 819         case 48000:
 820                 break;
 821         default:
 822                 dev_err(codec->dev, "unsupported rate %d\n",
 823                         params_rate(params));
 824                 return -EINVAL;
 825         }
 826
 827         switch (params_format(params)) {
 828         case SNDRV_PCM_FORMAT_S16_LE:
 829                 break;
 830         default:
 831                 dev_err(codec->dev, "unsupported format %d\n",
 832                         params_format(params));
 833                 return -EINVAL;
 834         }
 835
 836         return 0;
 837 }
 838
 839 #define CALC_OSCSET(rate, refclk) ( \
 840         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 841 #define CALC_RATIOSET(rate, refclk) ( \
 842         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 843
 844 /*
 845  * tlv320dac33 is strict on the sequence of the register writes, if the register
 846  * writes happens in different order, than dac33 might end up in unknown state.
 847  * Use the known, working sequence of register writes to initialize the dac33.
 848  */
 849 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 850 {
 851         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 852         struct snd_soc_codec *codec = rtd->codec;
 853         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 854         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 855         u8 aictrl_a, aictrl_b, fifoctrl_a;
 856
 857         switch (substream->runtime->rate) {
 858         case 44100:
 859         case 48000:
 860                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 861                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 862                                          dac33->refclk);
 863                 break;
 864         default:
 865                 dev_err(codec->dev, "unsupported rate %d\n",
 866                         substream->runtime->rate);
 867                 return -EINVAL;
 868         }
 869
 870
 871         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 872         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 873         /* Read FIFO control A, and clear FIFO flush bit */
 874         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 875         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 876
 877         fifoctrl_a &= ~DAC33_WIDTH;
 878         switch (substream->runtime->format) {
 879         case SNDRV_PCM_FORMAT_S16_LE:
 880                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 881                 fifoctrl_a |= DAC33_WIDTH;
 882                 break;
 883         default:
 884                 dev_err(codec->dev, "unsupported format %d\n",
 885                         substream->runtime->format);
 886                 return -EINVAL;
 887         }
 888
 889         mutex_lock(&dac33->mutex);
 890
 891         if (!dac33->chip_power) {
 892                 /*
 893                  * Chip is not powered yet.
 894                  * Do the init in the dac33_set_bias_level later.
 895                  */
 896                 mutex_unlock(&dac33->mutex);
 897                 return 0;
 898         }
 899
 900         dac33_soft_power(codec, 0);
 901         dac33_soft_power(codec, 1);
 902
 903         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 904         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 905
 906         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 907         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 908
 909         /* calib time: 128 is a nice number ;) */
 910         dac33_write(codec, DAC33_CALIB_TIME, 128);
 911
 912         /* adjustment treshold & step */
 913         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 914                                                  DAC33_ADJSTEP(1));
 915
 916         /* div=4 / gain=1 / div */
 917         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 918
 919         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 920         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 921         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 922
 923         dac33_oscwait(codec);
 924
 925         if (dac33->fifo_mode) {
 926                 /* Generic for all FIFO modes */
 927                 /* 50-51 : ASRC Control registers */
 928                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 929                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 930
 931                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 932                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 933
 934                 /* Set interrupts to high active */
 935                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 936         } else {
 937                 /* FIFO bypass mode */
 938                 /* 50-51 : ASRC Control registers */
 939                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 940                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 941         }
 942
 943         /* Interrupt behaviour configuration */
 944         switch (dac33->fifo_mode) {
 945         case DAC33_FIFO_MODE1:
 946                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 947                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 948                 break;
 949         case DAC33_FIFO_MODE7:
 950                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 951                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 952                 break;
 953         default:
 954                 /* in FIFO bypass mode, the interrupts are not used */
 955                 break;
 956         }
 957
 958         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 959
 960         switch (dac33->fifo_mode) {
 961         case DAC33_FIFO_MODE1:
 962                 /*
 963                  * For mode1:
 964                  * Disable the FIFO bypass (Enable the use of FIFO)
 965                  * Select nSample mode
 966                  * BCLK is only running when data is needed by DAC33
 967                  */
 968                 fifoctrl_a &= ~DAC33_FBYPAS;
 969                 fifoctrl_a &= ~DAC33_FAUTO;
 970                 if (dac33->keep_bclk)
 971                         aictrl_b |= DAC33_BCLKON;
 972                 else
 973                         aictrl_b &= ~DAC33_BCLKON;
 974                 break;
 975         case DAC33_FIFO_MODE7:
 976                 /*
 977                  * For mode1:
 978                  * Disable the FIFO bypass (Enable the use of FIFO)
 979                  * Select Threshold mode
 980                  * BCLK is only running when data is needed by DAC33
 981                  */
 982                 fifoctrl_a &= ~DAC33_FBYPAS;
 983                 fifoctrl_a |= DAC33_FAUTO;
 984                 if (dac33->keep_bclk)
 985                         aictrl_b |= DAC33_BCLKON;
 986                 else
 987                         aictrl_b &= ~DAC33_BCLKON;
 988                 break;
 989         default:
 990                 /*
 991                  * For FIFO bypass mode:
 992                  * Enable the FIFO bypass (Disable the FIFO use)
 993                  * Set the BCLK as continous
 994                  */
 995                 fifoctrl_a |= DAC33_FBYPAS;
 996                 aictrl_b |= DAC33_BCLKON;
 997                 break;
 998         }
 999
1000         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1001         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1002         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1003
1004         /*
1005          * BCLK divide ratio
1006          * 0: 1.5
1007          * 1: 1
1008          * 2: 2
1009          * ...
1010          * 254: 254
1011          * 255: 255
1012          */
1013         if (dac33->fifo_mode)
1014                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1015                                                         dac33->burst_bclkdiv);
1016         else
1017                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1018
1019         switch (dac33->fifo_mode) {
1020         case DAC33_FIFO_MODE1:
1021                 dac33_write16(codec, DAC33_ATHR_MSB,
1022                               DAC33_THRREG(dac33->alarm_threshold));
1023                 break;
1024         case DAC33_FIFO_MODE7:
1025                 /*
1026                  * Configure the threshold levels, and leave 10 sample space
1027                  * at the bottom, and also at the top of the FIFO
1028                  */
1029                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1030                 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1031                 break;
1032         default:
1033                 break;
1034         }
1035
1036         mutex_unlock(&dac33->mutex);
1037
1038         return 0;
1039 }
1040
1041 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1042 {
1043         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1044         struct snd_soc_codec *codec = rtd->codec;
1045         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1046         unsigned int period_size = substream->runtime->period_size;
1047         unsigned int rate = substream->runtime->rate;
1048         unsigned int nsample_limit;
1049
1050         /* In bypass mode we don't need to calculate */
1051         if (!dac33->fifo_mode)
1052                 return;
1053
1054         switch (dac33->fifo_mode) {
1055         case DAC33_FIFO_MODE1:
1056                 /* Number of samples under i2c latency */
1057                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1058                                                 dac33->mode1_latency);
1059                 if (dac33->auto_fifo_config) {
1060                         if (period_size <= dac33->alarm_threshold)
1061                                 /*
1062                                  * Configure nSamaple to number of periods,
1063                                  * which covers the latency requironment.
1064                                  */
1065                                 dac33->nsample = period_size *
1066                                        ((dac33->alarm_threshold / period_size) +
1067                                        (dac33->alarm_threshold % period_size ?
1068                                        1 : 0));
1069                         else
1070                                 dac33->nsample = period_size;
1071                 } else {
1072                         /* nSample time shall not be shorter than i2c latency */
1073                         dac33->nsample_min = dac33->alarm_threshold;
1074                         /*
1075                          * nSample should not be bigger than alsa buffer minus
1076                          * size of one period to avoid overruns
1077                          */
1078                         dac33->nsample_max = substream->runtime->buffer_size -
1079                                                 period_size;
1080                         nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1081                                         dac33->alarm_threshold;
1082                         if (dac33->nsample_max > nsample_limit)
1083                                 dac33->nsample_max = nsample_limit;
1084
1085                         /* Correct the nSample if it is outside of the ranges */
1086                         if (dac33->nsample < dac33->nsample_min)
1087                                 dac33->nsample = dac33->nsample_min;
1088                         if (dac33->nsample > dac33->nsample_max)
1089                                 dac33->nsample = dac33->nsample_max;
1090                 }
1091
1092                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1093                                                       dac33->nsample);
1094                 dac33->t_stamp1 = 0;
1095                 dac33->t_stamp2 = 0;
1096                 break;
1097         case DAC33_FIFO_MODE7:
1098                 if (dac33->auto_fifo_config) {
1099                         dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1100                                         period_size,
1101                                         rate,
1102                                         dac33->burst_rate) + 9;
1103                         if (dac33->uthr > MODE7_UTHR)
1104                                 dac33->uthr = MODE7_UTHR;
1105                         if (dac33->uthr < (MODE7_LTHR + 10))
1106                                 dac33->uthr = (MODE7_LTHR + 10);
1107                 }
1108                 dac33->mode7_us_to_lthr =
1109                                 SAMPLES_TO_US(substream->runtime->rate,
1110                                         dac33->uthr - MODE7_LTHR + 1);
1111                 dac33->t_stamp1 = 0;
1112                 break;
1113         default:
1114                 break;
1115         }
1116
1117 }
1118
1119 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1120                              struct snd_soc_dai *dai)
1121 {
1122         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1123         struct snd_soc_codec *codec = rtd->codec;
1124         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1125         int ret = 0;
1126
1127         switch (cmd) {
1128         case SNDRV_PCM_TRIGGER_START:
1129         case SNDRV_PCM_TRIGGER_RESUME:
1130         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1131                 if (dac33->fifo_mode) {
1132                         dac33->state = DAC33_PREFILL;
1133                         queue_work(dac33->dac33_wq, &dac33->work);
1134                 }
1135                 break;
1136         case SNDRV_PCM_TRIGGER_STOP:
1137         case SNDRV_PCM_TRIGGER_SUSPEND:
1138         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1139                 if (dac33->fifo_mode) {
1140                         dac33->state = DAC33_FLUSH;
1141                         queue_work(dac33->dac33_wq, &dac33->work);
1142                 }
1143                 break;
1144         default:
1145                 ret = -EINVAL;
1146         }
1147
1148         return ret;
1149 }
1150
1151 static snd_pcm_sframes_t dac33_dai_delay(
1152                         struct snd_pcm_substream *substream,
1153                         struct snd_soc_dai *dai)
1154 {
1155         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1156         struct snd_soc_codec *codec = rtd->codec;
1157         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1158         unsigned long long t0, t1, t_now;
1159         unsigned int time_delta, uthr;
1160         int samples_out, samples_in, samples;
1161         snd_pcm_sframes_t delay = 0;
1162
1163         switch (dac33->fifo_mode) {
1164         case DAC33_FIFO_BYPASS:
1165                 break;
1166         case DAC33_FIFO_MODE1:
1167                 spin_lock(&dac33->lock);
1168                 t0 = dac33->t_stamp1;
1169                 t1 = dac33->t_stamp2;
1170                 spin_unlock(&dac33->lock);
1171                 t_now = ktime_to_us(ktime_get());
1172
1173                 /* We have not started to fill the FIFO yet, delay is 0 */
1174                 if (!t1)
1175                         goto out;
1176
1177                 if (t0 > t1) {
1178                         /*
1179                          * Phase 1:
1180                          * After Alarm threshold, and before nSample write
1181                          */
1182                         time_delta = t_now - t0;
1183                         samples_out = time_delta ? US_TO_SAMPLES(
1184                                                 substream->runtime->rate,
1185                                                 time_delta) : 0;
1186
1187                         if (likely(dac33->alarm_threshold > samples_out))
1188                                 delay = dac33->alarm_threshold - samples_out;
1189                         else
1190                                 delay = 0;
1191                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1192                         /*
1193                          * Phase 2:
1194                          * After nSample write (during burst operation)
1195                          */
1196                         time_delta = t_now - t0;
1197                         samples_out = time_delta ? US_TO_SAMPLES(
1198                                                 substream->runtime->rate,
1199                                                 time_delta) : 0;
1200
1201                         time_delta = t_now - t1;
1202                         samples_in = time_delta ? US_TO_SAMPLES(
1203                                                 dac33->burst_rate,
1204                                                 time_delta) : 0;
1205
1206                         samples = dac33->alarm_threshold;
1207                         samples += (samples_in - samples_out);
1208
1209                         if (likely(samples > 0))
1210                                 delay = samples;
1211                         else
1212                                 delay = 0;
1213                 } else {
1214                         /*
1215                          * Phase 3:
1216                          * After burst operation, before next alarm threshold
1217                          */
1218                         time_delta = t_now - t0;
1219                         samples_out = time_delta ? US_TO_SAMPLES(
1220                                                 substream->runtime->rate,
1221                                                 time_delta) : 0;
1222
1223                         samples_in = dac33->nsample;
1224                         samples = dac33->alarm_threshold;
1225                         samples += (samples_in - samples_out);
1226
1227                         if (likely(samples > 0))
1228                                 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1229                                         DAC33_BUFFER_SIZE_SAMPLES : samples;
1230                         else
1231                                 delay = 0;
1232                 }
1233                 break;
1234         case DAC33_FIFO_MODE7:
1235                 spin_lock(&dac33->lock);
1236                 t0 = dac33->t_stamp1;
1237                 uthr = dac33->uthr;
1238                 spin_unlock(&dac33->lock);
1239                 t_now = ktime_to_us(ktime_get());
1240
1241                 /* We have not started to fill the FIFO yet, delay is 0 */
1242                 if (!t0)
1243                         goto out;
1244
1245                 if (t_now <= t0) {
1246                         /*
1247                          * Either the timestamps are messed or equal. Report
1248                          * maximum delay
1249                          */
1250                         delay = uthr;
1251                         goto out;
1252                 }
1253
1254                 time_delta = t_now - t0;
1255                 if (time_delta <= dac33->mode7_us_to_lthr) {
1256                         /*
1257                         * Phase 1:
1258                         * After burst (draining phase)
1259                         */
1260                         samples_out = US_TO_SAMPLES(
1261                                         substream->runtime->rate,
1262                                         time_delta);
1263
1264                         if (likely(uthr > samples_out))
1265                                 delay = uthr - samples_out;
1266                         else
1267                                 delay = 0;
1268                 } else {
1269                         /*
1270                         * Phase 2:
1271                         * During burst operation
1272                         */
1273                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1274
1275                         samples_out = US_TO_SAMPLES(
1276                                         substream->runtime->rate,
1277                                         time_delta);
1278                         samples_in = US_TO_SAMPLES(
1279                                         dac33->burst_rate,
1280                                         time_delta);
1281                         delay = MODE7_LTHR + samples_in - samples_out;
1282
1283                         if (unlikely(delay > uthr))
1284                                 delay = uthr;
1285                 }
1286                 break;
1287         default:
1288                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1289                                                         dac33->fifo_mode);
1290                 break;
1291         }
1292 out:
1293         return delay;
1294 }
1295
1296 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1297                 int clk_id, unsigned int freq, int dir)
1298 {
1299         struct snd_soc_codec *codec = codec_dai->codec;
1300         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1301         u8 ioc_reg, asrcb_reg;
1302
1303         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1304         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1305         switch (clk_id) {
1306         case TLV320DAC33_MCLK:
1307                 ioc_reg |= DAC33_REFSEL;
1308                 asrcb_reg |= DAC33_SRCREFSEL;
1309                 break;
1310         case TLV320DAC33_SLEEPCLK:
1311                 ioc_reg &= ~DAC33_REFSEL;
1312                 asrcb_reg &= ~DAC33_SRCREFSEL;
1313                 break;
1314         default:
1315                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1316                 break;
1317         }
1318         dac33->refclk = freq;
1319
1320         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1321         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1322
1323         return 0;
1324 }
1325
1326 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1327                              unsigned int fmt)
1328 {
1329         struct snd_soc_codec *codec = codec_dai->codec;
1330         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1331         u8 aictrl_a, aictrl_b;
1332
1333         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1334         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1335         /* set master/slave audio interface */
1336         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1337         case SND_SOC_DAIFMT_CBM_CFM:
1338                 /* Codec Master */
1339                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1340                 break;
1341         case SND_SOC_DAIFMT_CBS_CFS:
1342                 /* Codec Slave */
1343                 if (dac33->fifo_mode) {
1344                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1345                         return -EINVAL;
1346                 } else
1347                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1348                 break;
1349         default:
1350                 return -EINVAL;
1351         }
1352
1353         aictrl_a &= ~DAC33_AFMT_MASK;
1354         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1355         case SND_SOC_DAIFMT_I2S:
1356                 aictrl_a |= DAC33_AFMT_I2S;
1357                 break;
1358         case SND_SOC_DAIFMT_DSP_A:
1359                 aictrl_a |= DAC33_AFMT_DSP;
1360                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1361                 aictrl_b |= DAC33_DATA_DELAY(0);
1362                 break;
1363         case SND_SOC_DAIFMT_RIGHT_J:
1364                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1365                 break;
1366         case SND_SOC_DAIFMT_LEFT_J:
1367                 aictrl_a |= DAC33_AFMT_LEFT_J;
1368                 break;
1369         default:
1370                 dev_err(codec->dev, "Unsupported format (%u)\n",
1371                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1372                 return -EINVAL;
1373         }
1374
1375         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1376         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1377
1378         return 0;
1379 }
1380
1381 static int dac33_soc_probe(struct snd_soc_codec *codec)
1382 {
1383         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1384         int ret = 0;
1385
1386         codec->control_data = dac33->control_data;
1387         codec->hw_write = (hw_write_t) i2c_master_send;
1388         codec->bias_level = SND_SOC_BIAS_OFF;
1389         codec->idle_bias_off = 1;
1390         dac33->codec = codec;
1391
1392         /* Read the tlv320dac33 ID registers */
1393         ret = dac33_hard_power(codec, 1);
1394         if (ret != 0) {
1395                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1396                 goto err_power;
1397         }
1398         dac33_read_id(codec);
1399         dac33_hard_power(codec, 0);
1400
1401         /* Check if the IRQ number is valid and request it */
1402         if (dac33->irq >= 0) {
1403                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1404                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1405                                   codec->name, codec);
1406                 if (ret < 0) {
1407                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1408                                                 dac33->irq, ret);
1409                         dac33->irq = -1;
1410                 }
1411                 if (dac33->irq != -1) {
1412                         /* Setup work queue */
1413                         dac33->dac33_wq =
1414                                 create_singlethread_workqueue("tlv320dac33");
1415                         if (dac33->dac33_wq == NULL) {
1416                                 free_irq(dac33->irq, codec);
1417                                 return -ENOMEM;
1418                         }
1419
1420                         INIT_WORK(&dac33->work, dac33_work);
1421                 }
1422         }
1423
1424         snd_soc_add_controls(codec, dac33_snd_controls,
1425                              ARRAY_SIZE(dac33_snd_controls));
1426         /* Only add the FIFO controls, if we have valid IRQ number */
1427         if (dac33->irq >= 0) {
1428                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1429                                      ARRAY_SIZE(dac33_mode_snd_controls));
1430                 /* FIFO usage controls only, if autoio config is not selected */
1431                 if (!dac33->auto_fifo_config)
1432                         snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1433                                         ARRAY_SIZE(dac33_fifo_snd_controls));
1434         }
1435         dac33_add_widgets(codec);
1436
1437 err_power:
1438         return ret;
1439 }
1440
1441 static int dac33_soc_remove(struct snd_soc_codec *codec)
1442 {
1443         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1444
1445         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1446
1447         if (dac33->irq >= 0) {
1448                 free_irq(dac33->irq, dac33->codec);
1449                 destroy_workqueue(dac33->dac33_wq);
1450         }
1451         return 0;
1452 }
1453
1454 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1455 {
1456         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1457
1458         return 0;
1459 }
1460
1461 static int dac33_soc_resume(struct snd_soc_codec *codec)
1462 {
1463         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1464
1465         return 0;
1466 }
1467
1468 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1469         .read = dac33_read_reg_cache,
1470         .write = dac33_write_locked,
1471         .set_bias_level = dac33_set_bias_level,
1472         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1473         .reg_word_size = sizeof(u8),
1474         .reg_cache_default = dac33_reg,
1475         .probe = dac33_soc_probe,
1476         .remove = dac33_soc_remove,
1477         .suspend = dac33_soc_suspend,
1478         .resume = dac33_soc_resume,
1479 };
1480
1481 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1482                          SNDRV_PCM_RATE_48000)
1483 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1484
1485 static struct snd_soc_dai_ops dac33_dai_ops = {
1486         .startup        = dac33_startup,
1487         .shutdown       = dac33_shutdown,
1488         .hw_params      = dac33_hw_params,
1489         .trigger        = dac33_pcm_trigger,
1490         .delay          = dac33_dai_delay,
1491         .set_sysclk     = dac33_set_dai_sysclk,
1492         .set_fmt        = dac33_set_dai_fmt,
1493 };
1494
1495 static struct snd_soc_dai_driver dac33_dai = {
1496         .name = "tlv320dac33-hifi",
1497         .playback = {
1498                 .stream_name = "Playback",
1499                 .channels_min = 2,
1500                 .channels_max = 2,
1501                 .rates = DAC33_RATES,
1502                 .formats = DAC33_FORMATS,},
1503         .ops = &dac33_dai_ops,
1504 };
1505
1506 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1507                                      const struct i2c_device_id *id)
1508 {
1509         struct tlv320dac33_platform_data *pdata;
1510         struct tlv320dac33_priv *dac33;
1511         int ret, i;
1512
1513         if (client->dev.platform_data == NULL) {
1514                 dev_err(&client->dev, "Platform data not set\n");
1515                 return -ENODEV;
1516         }
1517         pdata = client->dev.platform_data;
1518
1519         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1520         if (dac33 == NULL)
1521                 return -ENOMEM;
1522
1523         dac33->control_data = client;
1524         mutex_init(&dac33->mutex);
1525         spin_lock_init(&dac33->lock);
1526
1527         i2c_set_clientdata(client, dac33);
1528
1529         dac33->power_gpio = pdata->power_gpio;
1530         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1531         /* Pre calculate the burst rate */
1532         dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1533         dac33->keep_bclk = pdata->keep_bclk;
1534         dac33->auto_fifo_config = pdata->auto_fifo_config;
1535         dac33->mode1_latency = pdata->mode1_latency;
1536         if (!dac33->mode1_latency)
1537                 dac33->mode1_latency = 10000; /* 10ms */
1538         dac33->irq = client->irq;
1539         dac33->nsample = NSAMPLE_MAX;
1540         dac33->nsample_max = NSAMPLE_MAX;
1541         dac33->uthr = MODE7_UTHR;
1542         /* Disable FIFO use by default */
1543         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1544
1545         /* Check if the reset GPIO number is valid and request it */
1546         if (dac33->power_gpio >= 0) {
1547                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1548                 if (ret < 0) {
1549                         dev_err(&client->dev,
1550                                 "Failed to request reset GPIO (%d)\n",
1551                                 dac33->power_gpio);
1552                         goto err_gpio;
1553                 }
1554                 gpio_direction_output(dac33->power_gpio, 0);
1555         }
1556
1557         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1558                 dac33->supplies[i].supply = dac33_supply_names[i];
1559
1560         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1561                                  dac33->supplies);
1562
1563         if (ret != 0) {
1564                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1565                 goto err_get;
1566         }
1567
1568         ret = snd_soc_register_codec(&client->dev,
1569                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1570         if (ret < 0)
1571                 goto err_register;
1572
1573         return ret;
1574 err_register:
1575         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1576 err_get:
1577         if (dac33->power_gpio >= 0)
1578                 gpio_free(dac33->power_gpio);
1579 err_gpio:
1580         kfree(dac33);
1581         return ret;
1582 }
1583
1584 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1585 {
1586         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1587
1588         if (unlikely(dac33->chip_power))
1589                 dac33_hard_power(dac33->codec, 0);
1590
1591         if (dac33->power_gpio >= 0)
1592                 gpio_free(dac33->power_gpio);
1593
1594         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1595
1596         snd_soc_unregister_codec(&client->dev);
1597         kfree(dac33);
1598
1599         return 0;
1600 }
1601
1602 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1603         {
1604                 .name = "tlv320dac33",
1605                 .driver_data = 0,
1606         },
1607         { },
1608 };
1609
1610 static struct i2c_driver tlv320dac33_i2c_driver = {
1611         .driver = {
1612                 .name = "tlv320dac33-codec",
1613                 .owner = THIS_MODULE,
1614         },
1615         .probe          = dac33_i2c_probe,
1616         .remove         = __devexit_p(dac33_i2c_remove),
1617         .id_table       = tlv320dac33_i2c_id,
1618 };
1619
1620 static int __init dac33_module_init(void)
1621 {
1622         int r;
1623         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1624         if (r < 0) {
1625                 printk(KERN_ERR "DAC33: driver registration failed\n");
1626                 return r;
1627         }
1628         return 0;
1629 }
1630 module_init(dac33_module_init);
1631
1632 static void __exit dac33_module_exit(void)
1633 {
1634         i2c_del_driver(&tlv320dac33_i2c_driver);
1635 }
1636 module_exit(dac33_module_exit);
1637
1638
1639 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1640 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1641 MODULE_LICENSE("GPL");