2 * wm8580.c -- WM8580 ALSA Soc Audio driver
4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/regulator/consumer.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/soc-dapm.h>
34 #include <sound/tlv.h>
35 #include <sound/initval.h>
36 #include <asm/div64.h>
40 /* WM8580 register space */
41 #define WM8580_PLLA1 0x00
42 #define WM8580_PLLA2 0x01
43 #define WM8580_PLLA3 0x02
44 #define WM8580_PLLA4 0x03
45 #define WM8580_PLLB1 0x04
46 #define WM8580_PLLB2 0x05
47 #define WM8580_PLLB3 0x06
48 #define WM8580_PLLB4 0x07
49 #define WM8580_CLKSEL 0x08
50 #define WM8580_PAIF1 0x09
51 #define WM8580_PAIF2 0x0A
52 #define WM8580_SAIF1 0x0B
53 #define WM8580_PAIF3 0x0C
54 #define WM8580_PAIF4 0x0D
55 #define WM8580_SAIF2 0x0E
56 #define WM8580_DAC_CONTROL1 0x0F
57 #define WM8580_DAC_CONTROL2 0x10
58 #define WM8580_DAC_CONTROL3 0x11
59 #define WM8580_DAC_CONTROL4 0x12
60 #define WM8580_DAC_CONTROL5 0x13
61 #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
62 #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
63 #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
64 #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
65 #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
66 #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
67 #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
68 #define WM8580_ADC_CONTROL1 0x1D
69 #define WM8580_SPDTXCHAN0 0x1E
70 #define WM8580_SPDTXCHAN1 0x1F
71 #define WM8580_SPDTXCHAN2 0x20
72 #define WM8580_SPDTXCHAN3 0x21
73 #define WM8580_SPDTXCHAN4 0x22
74 #define WM8580_SPDTXCHAN5 0x23
75 #define WM8580_SPDMODE 0x24
76 #define WM8580_INTMASK 0x25
77 #define WM8580_GPO1 0x26
78 #define WM8580_GPO2 0x27
79 #define WM8580_GPO3 0x28
80 #define WM8580_GPO4 0x29
81 #define WM8580_GPO5 0x2A
82 #define WM8580_INTSTAT 0x2B
83 #define WM8580_SPDRXCHAN1 0x2C
84 #define WM8580_SPDRXCHAN2 0x2D
85 #define WM8580_SPDRXCHAN3 0x2E
86 #define WM8580_SPDRXCHAN4 0x2F
87 #define WM8580_SPDRXCHAN5 0x30
88 #define WM8580_SPDSTAT 0x31
89 #define WM8580_PWRDN1 0x32
90 #define WM8580_PWRDN2 0x33
91 #define WM8580_READBACK 0x34
92 #define WM8580_RESET 0x35
94 #define WM8580_MAX_REGISTER 0x35
96 /* PLLB4 (register 7h) */
97 #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
98 #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
99 #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
100 #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
102 #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
103 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
104 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
105 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
107 /* CLKSEL (register 8h) */
108 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
109 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
110 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
112 /* AIF control 1 (registers 9h-bh) */
113 #define WM8580_AIF_RATE_MASK 0x7
114 #define WM8580_AIF_RATE_128 0x0
115 #define WM8580_AIF_RATE_192 0x1
116 #define WM8580_AIF_RATE_256 0x2
117 #define WM8580_AIF_RATE_384 0x3
118 #define WM8580_AIF_RATE_512 0x4
119 #define WM8580_AIF_RATE_768 0x5
120 #define WM8580_AIF_RATE_1152 0x6
122 #define WM8580_AIF_BCLKSEL_MASK 0x18
123 #define WM8580_AIF_BCLKSEL_64 0x00
124 #define WM8580_AIF_BCLKSEL_128 0x08
125 #define WM8580_AIF_BCLKSEL_256 0x10
126 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
128 #define WM8580_AIF_MS 0x20
130 #define WM8580_AIF_CLKSRC_MASK 0xc0
131 #define WM8580_AIF_CLKSRC_PLLA 0x40
132 #define WM8580_AIF_CLKSRC_PLLB 0x40
133 #define WM8580_AIF_CLKSRC_MCLK 0xc0
135 /* AIF control 2 (registers ch-eh) */
136 #define WM8580_AIF_FMT_MASK 0x03
137 #define WM8580_AIF_FMT_RIGHTJ 0x00
138 #define WM8580_AIF_FMT_LEFTJ 0x01
139 #define WM8580_AIF_FMT_I2S 0x02
140 #define WM8580_AIF_FMT_DSP 0x03
142 #define WM8580_AIF_LENGTH_MASK 0x0c
143 #define WM8580_AIF_LENGTH_16 0x00
144 #define WM8580_AIF_LENGTH_20 0x04
145 #define WM8580_AIF_LENGTH_24 0x08
146 #define WM8580_AIF_LENGTH_32 0x0c
148 #define WM8580_AIF_LRP 0x10
149 #define WM8580_AIF_BCP 0x20
151 /* Powerdown Register 1 (register 32h) */
152 #define WM8580_PWRDN1_PWDN 0x001
153 #define WM8580_PWRDN1_ALLDACPD 0x040
155 /* Powerdown Register 2 (register 33h) */
156 #define WM8580_PWRDN2_OSSCPD 0x001
157 #define WM8580_PWRDN2_PLLAPD 0x002
158 #define WM8580_PWRDN2_PLLBPD 0x004
159 #define WM8580_PWRDN2_SPDIFPD 0x008
160 #define WM8580_PWRDN2_SPDIFTXD 0x010
161 #define WM8580_PWRDN2_SPDIFRXD 0x020
163 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
166 * wm8580 register cache
167 * We can't read the WM8580 register space when we
168 * are using 2 wire for device control, so we cache them instead.
170 static const u16 wm8580_reg[] = {
171 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
172 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
173 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
174 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
175 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
176 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
177 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
178 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
179 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
180 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
181 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
182 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
183 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
184 0x0000, 0x0000 /*R53*/
192 #define WM8580_NUM_SUPPLIES 3
193 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
199 /* codec private data */
201 struct snd_soc_codec codec;
202 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
203 u16 reg_cache[WM8580_MAX_REGISTER + 1];
208 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
210 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
211 struct snd_ctl_elem_value *ucontrol)
213 struct soc_mixer_control *mc =
214 (struct soc_mixer_control *)kcontrol->private_value;
215 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
216 u16 *reg_cache = codec->reg_cache;
217 unsigned int reg = mc->reg;
218 unsigned int reg2 = mc->rreg;
221 /* Clear the register cache so we write without VU set */
225 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
229 /* Now write again with the volume update bit set */
230 snd_soc_update_bits(codec, reg, 0x100, 0x100);
231 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
236 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
237 xinvert, tlv_array) \
238 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
239 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
240 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
241 .tlv.p = (tlv_array), \
242 .info = snd_soc_info_volsw_2r, \
243 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
244 .private_value = (unsigned long)&(struct soc_mixer_control) \
245 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
246 .max = xmax, .invert = xinvert} }
248 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
249 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
250 WM8580_DIGITAL_ATTENUATION_DACL1,
251 WM8580_DIGITAL_ATTENUATION_DACR1,
252 0, 0xff, 0, dac_tlv),
253 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
254 WM8580_DIGITAL_ATTENUATION_DACL2,
255 WM8580_DIGITAL_ATTENUATION_DACR2,
256 0, 0xff, 0, dac_tlv),
257 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
258 WM8580_DIGITAL_ATTENUATION_DACL3,
259 WM8580_DIGITAL_ATTENUATION_DACR3,
260 0, 0xff, 0, dac_tlv),
262 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
263 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
264 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
266 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
267 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
268 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
270 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
271 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
272 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
273 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
275 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
276 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
279 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
280 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
281 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
282 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
284 SND_SOC_DAPM_OUTPUT("VOUT1L"),
285 SND_SOC_DAPM_OUTPUT("VOUT1R"),
286 SND_SOC_DAPM_OUTPUT("VOUT2L"),
287 SND_SOC_DAPM_OUTPUT("VOUT2R"),
288 SND_SOC_DAPM_OUTPUT("VOUT3L"),
289 SND_SOC_DAPM_OUTPUT("VOUT3R"),
291 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
293 SND_SOC_DAPM_INPUT("AINL"),
294 SND_SOC_DAPM_INPUT("AINR"),
297 static const struct snd_soc_dapm_route audio_map[] = {
298 { "VOUT1L", NULL, "DAC1" },
299 { "VOUT1R", NULL, "DAC1" },
301 { "VOUT2L", NULL, "DAC2" },
302 { "VOUT2R", NULL, "DAC2" },
304 { "VOUT3L", NULL, "DAC3" },
305 { "VOUT3R", NULL, "DAC3" },
307 { "ADC", NULL, "AINL" },
308 { "ADC", NULL, "AINR" },
311 static int wm8580_add_widgets(struct snd_soc_codec *codec)
313 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
314 ARRAY_SIZE(wm8580_dapm_widgets));
316 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
330 /* The size in bits of the pll divide */
331 #define FIXED_PLL_SIZE (1 << 22)
333 /* PLL rate to output rate divisions */
336 unsigned int freqmode;
337 unsigned int postscale;
349 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
353 unsigned int K, Ndiv, Nmod;
356 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
358 /* Scale the output frequency up; the PLL should run in the
359 * region of 90-100MHz.
361 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
362 if (target * post_table[i].div >= 90000000 &&
363 target * post_table[i].div <= 100000000) {
364 pll_div->freqmode = post_table[i].freqmode;
365 pll_div->postscale = post_table[i].postscale;
366 target *= post_table[i].div;
371 if (i == ARRAY_SIZE(post_table)) {
372 printk(KERN_ERR "wm8580: Unable to scale output frequency "
377 Ndiv = target / source;
381 pll_div->prescale = 1;
382 Ndiv = target / source;
384 pll_div->prescale = 0;
386 if ((Ndiv < 5) || (Ndiv > 13)) {
388 "WM8580 N=%u outside supported range\n", Ndiv);
393 Nmod = target % source;
394 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
396 do_div(Kpart, source);
398 K = Kpart & 0xFFFFFFFF;
402 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
403 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
409 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
410 int source, unsigned int freq_in, unsigned int freq_out)
413 struct snd_soc_codec *codec = codec_dai->codec;
414 struct wm8580_priv *wm8580 = codec->private_data;
415 struct pll_state *state;
416 struct _pll_div pll_div;
418 unsigned int pwr_mask;
421 /* GCC isn't able to work out the ifs below for initialising/using
422 * pll_div so suppress warnings.
424 memset(&pll_div, 0, sizeof(pll_div));
430 pwr_mask = WM8580_PWRDN2_PLLAPD;
435 pwr_mask = WM8580_PWRDN2_PLLBPD;
441 if (freq_in && freq_out) {
442 ret = pll_factors(&pll_div, freq_out, freq_in);
448 state->out = freq_out;
450 /* Always disable the PLL - it is not safe to leave it running
451 * while reprogramming it.
453 reg = snd_soc_read(codec, WM8580_PWRDN2);
454 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
456 if (!freq_in || !freq_out)
459 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
460 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
461 snd_soc_write(codec, WM8580_PLLA3 + offset,
462 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
464 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
466 reg |= pll_div.prescale | pll_div.postscale << 1 |
467 pll_div.freqmode << 3;
469 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
471 /* All done, turn it on */
472 reg = snd_soc_read(codec, WM8580_PWRDN2);
473 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
479 * Set PCM DAI bit size and sample rate.
481 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
482 struct snd_pcm_hw_params *params,
483 struct snd_soc_dai *dai)
485 struct snd_soc_pcm_runtime *rtd = substream->private_data;
486 struct snd_soc_device *socdev = rtd->socdev;
487 struct snd_soc_codec *codec = socdev->card->codec;
488 u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->id);
490 paifb &= ~WM8580_AIF_LENGTH_MASK;
492 switch (params_format(params)) {
493 case SNDRV_PCM_FORMAT_S16_LE:
495 case SNDRV_PCM_FORMAT_S20_3LE:
496 paifb |= WM8580_AIF_LENGTH_20;
498 case SNDRV_PCM_FORMAT_S24_LE:
499 paifb |= WM8580_AIF_LENGTH_24;
501 case SNDRV_PCM_FORMAT_S32_LE:
502 paifb |= WM8580_AIF_LENGTH_24;
508 snd_soc_write(codec, WM8580_PAIF3 + dai->id, paifb);
512 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
515 struct snd_soc_codec *codec = codec_dai->codec;
518 int can_invert_lrclk;
520 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->id);
521 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->id);
523 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
525 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
526 case SND_SOC_DAIFMT_CBS_CFS:
527 aifa &= ~WM8580_AIF_MS;
529 case SND_SOC_DAIFMT_CBM_CFM:
530 aifa |= WM8580_AIF_MS;
536 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
537 case SND_SOC_DAIFMT_I2S:
538 can_invert_lrclk = 1;
539 aifb |= WM8580_AIF_FMT_I2S;
541 case SND_SOC_DAIFMT_RIGHT_J:
542 can_invert_lrclk = 1;
543 aifb |= WM8580_AIF_FMT_RIGHTJ;
545 case SND_SOC_DAIFMT_LEFT_J:
546 can_invert_lrclk = 1;
547 aifb |= WM8580_AIF_FMT_LEFTJ;
549 case SND_SOC_DAIFMT_DSP_A:
550 can_invert_lrclk = 0;
551 aifb |= WM8580_AIF_FMT_DSP;
553 case SND_SOC_DAIFMT_DSP_B:
554 can_invert_lrclk = 0;
555 aifb |= WM8580_AIF_FMT_DSP;
556 aifb |= WM8580_AIF_LRP;
562 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
563 case SND_SOC_DAIFMT_NB_NF:
566 case SND_SOC_DAIFMT_IB_IF:
567 if (!can_invert_lrclk)
569 aifb |= WM8580_AIF_BCP;
570 aifb |= WM8580_AIF_LRP;
573 case SND_SOC_DAIFMT_IB_NF:
574 aifb |= WM8580_AIF_BCP;
577 case SND_SOC_DAIFMT_NB_IF:
578 if (!can_invert_lrclk)
580 aifb |= WM8580_AIF_LRP;
587 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
588 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
593 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
596 struct snd_soc_codec *codec = codec_dai->codec;
601 reg = snd_soc_read(codec, WM8580_PLLB4);
602 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
605 case WM8580_CLKSRC_MCLK:
609 case WM8580_CLKSRC_PLLA:
610 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
612 case WM8580_CLKSRC_PLLB:
613 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
616 case WM8580_CLKSRC_OSC:
617 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
623 snd_soc_write(codec, WM8580_PLLB4, reg);
626 case WM8580_DAC_CLKSEL:
627 reg = snd_soc_read(codec, WM8580_CLKSEL);
628 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
631 case WM8580_CLKSRC_MCLK:
634 case WM8580_CLKSRC_PLLA:
635 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
638 case WM8580_CLKSRC_PLLB:
639 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
645 snd_soc_write(codec, WM8580_CLKSEL, reg);
648 case WM8580_CLKOUTSRC:
649 reg = snd_soc_read(codec, WM8580_PLLB4);
650 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
653 case WM8580_CLKSRC_NONE:
656 case WM8580_CLKSRC_PLLA:
657 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
660 case WM8580_CLKSRC_PLLB:
661 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
664 case WM8580_CLKSRC_OSC:
665 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
671 snd_soc_write(codec, WM8580_PLLB4, reg);
681 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
683 struct snd_soc_codec *codec = codec_dai->codec;
686 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
689 reg |= WM8580_DAC_CONTROL5_MUTEALL;
691 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
693 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
698 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
699 enum snd_soc_bias_level level)
703 case SND_SOC_BIAS_ON:
704 case SND_SOC_BIAS_PREPARE:
707 case SND_SOC_BIAS_STANDBY:
708 if (codec->bias_level == SND_SOC_BIAS_OFF) {
709 /* Power up and get individual control of the DACs */
710 reg = snd_soc_read(codec, WM8580_PWRDN1);
711 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
712 snd_soc_write(codec, WM8580_PWRDN1, reg);
714 /* Make VMID high impedence */
715 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
717 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
721 case SND_SOC_BIAS_OFF:
722 reg = snd_soc_read(codec, WM8580_PWRDN1);
723 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
726 codec->bias_level = level;
730 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
731 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
733 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
734 .hw_params = wm8580_paif_hw_params,
735 .set_fmt = wm8580_set_paif_dai_fmt,
736 .set_clkdiv = wm8580_set_dai_clkdiv,
737 .set_pll = wm8580_set_dai_pll,
738 .digital_mute = wm8580_digital_mute,
741 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
742 .hw_params = wm8580_paif_hw_params,
743 .set_fmt = wm8580_set_paif_dai_fmt,
744 .set_clkdiv = wm8580_set_dai_clkdiv,
745 .set_pll = wm8580_set_dai_pll,
748 struct snd_soc_dai wm8580_dai[] = {
750 .name = "WM8580 PAIFRX",
753 .stream_name = "Playback",
756 .rates = SNDRV_PCM_RATE_8000_192000,
757 .formats = WM8580_FORMATS,
759 .ops = &wm8580_dai_ops_playback,
762 .name = "WM8580 PAIFTX",
765 .stream_name = "Capture",
768 .rates = SNDRV_PCM_RATE_8000_192000,
769 .formats = WM8580_FORMATS,
771 .ops = &wm8580_dai_ops_capture,
774 EXPORT_SYMBOL_GPL(wm8580_dai);
776 static struct snd_soc_codec *wm8580_codec;
778 static int wm8580_probe(struct platform_device *pdev)
780 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
781 struct snd_soc_codec *codec;
784 if (wm8580_codec == NULL) {
785 dev_err(&pdev->dev, "Codec device not registered\n");
789 socdev->card->codec = wm8580_codec;
790 codec = wm8580_codec;
793 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
795 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
799 snd_soc_add_controls(codec, wm8580_snd_controls,
800 ARRAY_SIZE(wm8580_snd_controls));
801 wm8580_add_widgets(codec);
809 /* power down chip */
810 static int wm8580_remove(struct platform_device *pdev)
812 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
814 snd_soc_free_pcms(socdev);
815 snd_soc_dapm_free(socdev);
820 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
821 .probe = wm8580_probe,
822 .remove = wm8580_remove,
824 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
826 static int wm8580_register(struct wm8580_priv *wm8580,
827 enum snd_soc_control_type control)
830 struct snd_soc_codec *codec = &wm8580->codec;
833 dev_err(codec->dev, "Another WM8580 is registered\n");
838 mutex_init(&codec->mutex);
839 INIT_LIST_HEAD(&codec->dapm_widgets);
840 INIT_LIST_HEAD(&codec->dapm_paths);
842 codec->private_data = wm8580;
843 codec->name = "WM8580";
844 codec->owner = THIS_MODULE;
845 codec->bias_level = SND_SOC_BIAS_OFF;
846 codec->set_bias_level = wm8580_set_bias_level;
847 codec->dai = wm8580_dai;
848 codec->num_dai = ARRAY_SIZE(wm8580_dai);
849 codec->reg_cache_size = ARRAY_SIZE(wm8580->reg_cache);
850 codec->reg_cache = &wm8580->reg_cache;
852 memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
854 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
856 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
860 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
861 wm8580->supplies[i].supply = wm8580_supply_names[i];
863 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
866 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
870 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
873 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
874 goto err_regulator_get;
877 /* Get the codec into a known state */
878 ret = snd_soc_write(codec, WM8580_RESET, 0);
880 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
881 goto err_regulator_enable;
884 for (i = 0; i < ARRAY_SIZE(wm8580_dai); i++)
885 wm8580_dai[i].dev = codec->dev;
887 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
889 wm8580_codec = codec;
891 ret = snd_soc_register_codec(codec);
893 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
894 goto err_regulator_enable;
897 ret = snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
899 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
906 snd_soc_unregister_codec(codec);
907 err_regulator_enable:
908 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
910 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
916 static void wm8580_unregister(struct wm8580_priv *wm8580)
918 wm8580_set_bias_level(&wm8580->codec, SND_SOC_BIAS_OFF);
919 snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
920 snd_soc_unregister_codec(&wm8580->codec);
921 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
922 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
927 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
928 static int wm8580_i2c_probe(struct i2c_client *i2c,
929 const struct i2c_device_id *id)
931 struct wm8580_priv *wm8580;
932 struct snd_soc_codec *codec;
934 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
938 codec = &wm8580->codec;
940 i2c_set_clientdata(i2c, wm8580);
941 codec->control_data = i2c;
943 codec->dev = &i2c->dev;
945 return wm8580_register(wm8580, SND_SOC_I2C);
948 static int wm8580_i2c_remove(struct i2c_client *client)
950 struct wm8580_priv *wm8580 = i2c_get_clientdata(client);
951 wm8580_unregister(wm8580);
955 static const struct i2c_device_id wm8580_i2c_id[] = {
959 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
961 static struct i2c_driver wm8580_i2c_driver = {
964 .owner = THIS_MODULE,
966 .probe = wm8580_i2c_probe,
967 .remove = wm8580_i2c_remove,
968 .id_table = wm8580_i2c_id,
972 static int __init wm8580_modinit(void)
976 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
977 ret = i2c_add_driver(&wm8580_i2c_driver);
979 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
985 module_init(wm8580_modinit);
987 static void __exit wm8580_exit(void)
989 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
990 i2c_del_driver(&wm8580_i2c_driver);
993 module_exit(wm8580_exit);
995 MODULE_DESCRIPTION("ASoC WM8580 driver");
996 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
997 MODULE_LICENSE("GPL");