2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
38 /* WM8900 register space */
39 #define WM8900_REG_RESET 0x0
40 #define WM8900_REG_ID 0x0
41 #define WM8900_REG_POWER1 0x1
42 #define WM8900_REG_POWER2 0x2
43 #define WM8900_REG_POWER3 0x3
44 #define WM8900_REG_AUDIO1 0x4
45 #define WM8900_REG_AUDIO2 0x5
46 #define WM8900_REG_CLOCKING1 0x6
47 #define WM8900_REG_CLOCKING2 0x7
48 #define WM8900_REG_AUDIO3 0x8
49 #define WM8900_REG_AUDIO4 0x9
50 #define WM8900_REG_DACCTRL 0xa
51 #define WM8900_REG_LDAC_DV 0xb
52 #define WM8900_REG_RDAC_DV 0xc
53 #define WM8900_REG_SIDETONE 0xd
54 #define WM8900_REG_ADCCTRL 0xe
55 #define WM8900_REG_LADC_DV 0xf
56 #define WM8900_REG_RADC_DV 0x10
57 #define WM8900_REG_GPIO 0x12
58 #define WM8900_REG_INCTL 0x15
59 #define WM8900_REG_LINVOL 0x16
60 #define WM8900_REG_RINVOL 0x17
61 #define WM8900_REG_INBOOSTMIX1 0x18
62 #define WM8900_REG_INBOOSTMIX2 0x19
63 #define WM8900_REG_ADCPATH 0x1a
64 #define WM8900_REG_AUXBOOST 0x1b
65 #define WM8900_REG_ADDCTL 0x1e
66 #define WM8900_REG_FLLCTL1 0x24
67 #define WM8900_REG_FLLCTL2 0x25
68 #define WM8900_REG_FLLCTL3 0x26
69 #define WM8900_REG_FLLCTL4 0x27
70 #define WM8900_REG_FLLCTL5 0x28
71 #define WM8900_REG_FLLCTL6 0x29
72 #define WM8900_REG_LOUTMIXCTL1 0x2c
73 #define WM8900_REG_ROUTMIXCTL1 0x2d
74 #define WM8900_REG_BYPASS1 0x2e
75 #define WM8900_REG_BYPASS2 0x2f
76 #define WM8900_REG_AUXOUT_CTL 0x30
77 #define WM8900_REG_LOUT1CTL 0x33
78 #define WM8900_REG_ROUT1CTL 0x34
79 #define WM8900_REG_LOUT2CTL 0x35
80 #define WM8900_REG_ROUT2CTL 0x36
81 #define WM8900_REG_HPCTL1 0x3a
82 #define WM8900_REG_OUTBIASCTL 0x73
84 #define WM8900_MAXREG 0x80
86 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
89 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
93 #define WM8900_REG_GPIO_TEMP_ENA 0x2
95 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
97 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98 #define WM8900_REG_POWER1_FLL_ENA 0x0040
100 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
102 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
104 #define WM8900_REG_POWER3_DACL_ENA 0x0002
105 #define WM8900_REG_POWER3_DACR_ENA 0x0001
107 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
111 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
114 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
116 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
119 #define WM8900_REG_DACCTRL_MUTE 0x004
120 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
121 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
123 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
125 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
127 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
129 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
131 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
136 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
138 #define WM8900_LRC_MASK 0xfc00
140 struct snd_soc_codec_device soc_codec_dev_wm8900;
143 struct snd_soc_codec codec;
145 u16 reg_cache[WM8900_MAXREG];
147 u32 fll_in; /* FLL input frequency */
148 u32 fll_out; /* FLL output frequency */
152 * wm8900 register cache. We can't read the entire register space and we
153 * have slow control buses so we cache the registers.
155 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
184 /* Remaining registers all zero */
187 static int wm8900_volatile_register(unsigned int reg)
191 case WM8900_REG_POWER1:
198 static void wm8900_reset(struct snd_soc_codec *codec)
200 snd_soc_write(codec, WM8900_REG_RESET, 0);
202 memcpy(codec->reg_cache, wm8900_reg_defaults,
203 sizeof(wm8900_reg_defaults));
206 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
207 struct snd_kcontrol *kcontrol, int event)
209 struct snd_soc_codec *codec = w->codec;
210 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
213 case SND_SOC_DAPM_PRE_PMU:
214 /* Clamp headphone outputs */
215 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
216 WM8900_REG_HPCTL1_HP_CLAMP_OP;
217 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
220 case SND_SOC_DAPM_POST_PMU:
221 /* Enable the input stage */
222 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
223 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
224 WM8900_REG_HPCTL1_HP_SHORT2 |
225 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
226 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
230 /* Enable the output stage */
231 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
232 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
233 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
235 /* Remove the shorts */
236 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
237 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
238 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
239 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
242 case SND_SOC_DAPM_PRE_PMD:
243 /* Short the output */
244 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
245 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
247 /* Disable the output stage */
248 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
249 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
251 /* Clamp the outputs and power down input */
252 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
253 WM8900_REG_HPCTL1_HP_CLAMP_OP;
254 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
255 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
258 case SND_SOC_DAPM_POST_PMD:
259 /* Disable everything */
260 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
270 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
272 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
274 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
276 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
278 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
280 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
282 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
284 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
286 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
288 static const struct soc_enum mic_bias_level =
289 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
291 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
293 static const struct soc_enum dac_mute_rate =
294 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
296 static const char *dac_deemphasis_txt[] = {
297 "Disabled", "32kHz", "44.1kHz", "48kHz"
300 static const struct soc_enum dac_deemphasis =
301 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
303 static const char *adc_hpf_cut_txt[] = {
304 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
307 static const struct soc_enum adc_hpf_cut =
308 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
310 static const char *lr_txt[] = {
314 static const struct soc_enum aifl_src =
315 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
317 static const struct soc_enum aifr_src =
318 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
320 static const struct soc_enum dacl_src =
321 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
323 static const struct soc_enum dacr_src =
324 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
326 static const char *sidetone_txt[] = {
327 "Disabled", "Left ADC", "Right ADC"
330 static const struct soc_enum dacl_sidetone =
331 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
333 static const struct soc_enum dacr_sidetone =
334 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
336 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
337 SOC_ENUM("Mic Bias Level", mic_bias_level),
339 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
341 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
342 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
344 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
346 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
347 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
349 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
350 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
351 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
352 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
353 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
356 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
357 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
358 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
359 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
361 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
363 SOC_ENUM("Left Digital Audio Source", aifl_src),
364 SOC_ENUM("Right Digital Audio Source", aifr_src),
366 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
368 SOC_ENUM("Left DAC Source", dacl_src),
369 SOC_ENUM("Right DAC Source", dacr_src),
370 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
371 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
372 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
374 SOC_DOUBLE_R_TLV("Digital Playback Volume",
375 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
377 SOC_DOUBLE_R_TLV("Digital Capture Volume",
378 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
380 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
382 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
384 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
386 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
389 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
391 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
393 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
395 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
398 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
400 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
402 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
404 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
406 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
408 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
411 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
412 0, 63, 0, out_pga_tlv),
413 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
415 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
418 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
419 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
420 0, 63, 0, out_pga_tlv),
421 SOC_DOUBLE_R("LINEOUT2 Switch",
422 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
423 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
424 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
425 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
430 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
431 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
433 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
434 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
436 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
437 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
438 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
439 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
440 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
441 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
444 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
445 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
446 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
447 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
448 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
449 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
452 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
453 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
454 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
455 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
456 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
459 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
460 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
461 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
462 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
463 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
466 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
467 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
468 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
469 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
472 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
473 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
474 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
475 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
478 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
480 static const struct soc_enum wm8900_lineout2_lp_mux =
481 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
483 static const struct snd_kcontrol_new wm8900_lineout2_lp =
484 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
486 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
488 /* Externally visible pins */
489 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
490 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
491 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
492 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
493 SND_SOC_DAPM_OUTPUT("HP_L"),
494 SND_SOC_DAPM_OUTPUT("HP_R"),
496 SND_SOC_DAPM_INPUT("RINPUT1"),
497 SND_SOC_DAPM_INPUT("LINPUT1"),
498 SND_SOC_DAPM_INPUT("RINPUT2"),
499 SND_SOC_DAPM_INPUT("LINPUT2"),
500 SND_SOC_DAPM_INPUT("RINPUT3"),
501 SND_SOC_DAPM_INPUT("LINPUT3"),
502 SND_SOC_DAPM_INPUT("AUX"),
504 SND_SOC_DAPM_VMID("VMID"),
507 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
508 wm8900_linpga_controls,
509 ARRAY_SIZE(wm8900_linpga_controls)),
510 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
511 wm8900_rinpga_controls,
512 ARRAY_SIZE(wm8900_rinpga_controls)),
514 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
515 wm8900_linmix_controls,
516 ARRAY_SIZE(wm8900_linmix_controls)),
517 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
518 wm8900_rinmix_controls,
519 ARRAY_SIZE(wm8900_rinmix_controls)),
521 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
523 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
524 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
527 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
528 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
530 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
532 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
533 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
535 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
536 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
538 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
539 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
540 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
542 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
543 wm8900_loutmix_controls,
544 ARRAY_SIZE(wm8900_loutmix_controls)),
545 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
546 wm8900_routmix_controls,
547 ARRAY_SIZE(wm8900_routmix_controls)),
550 /* Target, Path, Source */
551 static const struct snd_soc_dapm_route audio_map[] = {
553 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
554 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
555 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
557 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
558 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
559 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
561 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
562 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
563 {"Left Input Mixer", "AUX Switch", "AUX"},
564 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
566 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
567 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
568 {"Right Input Mixer", "AUX Switch", "AUX"},
569 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
571 {"ADCL", NULL, "Left Input Mixer"},
572 {"ADCR", NULL, "Right Input Mixer"},
575 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
576 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
577 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
578 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
580 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
581 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
582 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
583 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
585 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
586 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
587 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
588 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
590 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
591 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
592 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
593 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
594 {"Left Output Mixer", "DACL Switch", "DACL"},
596 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
597 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
598 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
599 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
600 {"Right Output Mixer", "DACR Switch", "DACR"},
602 /* Note that the headphone output stage needs to be connected
603 * externally to LINEOUT2 via DC blocking capacitors. Other
604 * configurations are not supported.
606 * Note also that left and right headphone paths are treated as a
609 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
610 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
611 {"HP_L", NULL, "Headphone Amplifier"},
612 {"HP_R", NULL, "Headphone Amplifier"},
615 static int wm8900_add_widgets(struct snd_soc_codec *codec)
617 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
618 ARRAY_SIZE(wm8900_dapm_widgets));
620 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
625 static int wm8900_hw_params(struct snd_pcm_substream *substream,
626 struct snd_pcm_hw_params *params,
627 struct snd_soc_dai *dai)
629 struct snd_soc_pcm_runtime *rtd = substream->private_data;
630 struct snd_soc_device *socdev = rtd->socdev;
631 struct snd_soc_codec *codec = socdev->card->codec;
634 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
636 switch (params_format(params)) {
637 case SNDRV_PCM_FORMAT_S16_LE:
639 case SNDRV_PCM_FORMAT_S20_3LE:
642 case SNDRV_PCM_FORMAT_S24_LE:
645 case SNDRV_PCM_FORMAT_S32_LE:
652 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
655 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
657 if (params_rate(params) <= 24000)
658 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
660 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
662 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
672 u16 fll_slow_lock_ref;
677 /* The size in bits of the FLL divide multiplied by 10
678 * to allow rounding later */
679 #define FIXED_FLL_SIZE ((1 << 16) * 10)
681 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
685 unsigned int K, Ndiv, Nmod, target;
690 /* The FLL must run at 90-100MHz which is then scaled down to
691 * the output value by FLLCLK_DIV. */
694 while (target < 90000000) {
699 if (target > 100000000)
700 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
701 " Fout=%u\n", target, Fref, Fout);
703 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
704 "Fref=%u, Fout=%u, target=%u\n",
705 div, Fref, Fout, target);
709 fll_div->fllclk_div = div >> 2;
712 fll_div->fll_slow_lock_ref = 1;
714 fll_div->fll_slow_lock_ref = 0;
716 Ndiv = target / Fref;
719 fll_div->fll_ratio = 8;
721 fll_div->fll_ratio = 1;
723 fll_div->n = Ndiv / fll_div->fll_ratio;
724 Nmod = (target / fll_div->fll_ratio) % Fref;
726 /* Calculate fractional part - scale up so we can round. */
727 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
731 K = Kpart & 0xFFFFFFFF;
736 /* Move down to proper range now rounding is done */
739 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
740 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
745 static int wm8900_set_fll(struct snd_soc_codec *codec,
746 int fll_id, unsigned int freq_in, unsigned int freq_out)
748 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
749 struct _fll_div fll_div;
752 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
755 /* The digital side should be disabled during any change. */
756 reg = snd_soc_read(codec, WM8900_REG_POWER1);
757 snd_soc_write(codec, WM8900_REG_POWER1,
758 reg & (~WM8900_REG_POWER1_FLL_ENA));
760 /* Disable the FLL? */
761 if (!freq_in || !freq_out) {
762 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
763 snd_soc_write(codec, WM8900_REG_CLOCKING1,
764 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
766 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
767 snd_soc_write(codec, WM8900_REG_FLLCTL1,
768 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
770 wm8900->fll_in = freq_in;
771 wm8900->fll_out = freq_out;
776 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
779 wm8900->fll_in = freq_in;
780 wm8900->fll_out = freq_out;
782 /* The osclilator *MUST* be enabled before we enable the
783 * digital circuit. */
784 snd_soc_write(codec, WM8900_REG_FLLCTL1,
785 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
787 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
788 snd_soc_write(codec, WM8900_REG_FLLCTL5,
789 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
792 snd_soc_write(codec, WM8900_REG_FLLCTL2,
793 (fll_div.k >> 8) | 0x100);
794 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
796 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
798 if (fll_div.fll_slow_lock_ref)
799 snd_soc_write(codec, WM8900_REG_FLLCTL6,
800 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
802 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
804 reg = snd_soc_read(codec, WM8900_REG_POWER1);
805 snd_soc_write(codec, WM8900_REG_POWER1,
806 reg | WM8900_REG_POWER1_FLL_ENA);
809 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
810 snd_soc_write(codec, WM8900_REG_CLOCKING1,
811 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
816 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
817 int source, unsigned int freq_in, unsigned int freq_out)
819 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
822 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
825 struct snd_soc_codec *codec = codec_dai->codec;
829 case WM8900_BCLK_DIV:
830 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
831 snd_soc_write(codec, WM8900_REG_CLOCKING1,
832 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
834 case WM8900_OPCLK_DIV:
835 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
836 snd_soc_write(codec, WM8900_REG_CLOCKING1,
837 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
839 case WM8900_DAC_LRCLK:
840 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
841 snd_soc_write(codec, WM8900_REG_AUDIO4,
842 div | (reg & WM8900_LRC_MASK));
844 case WM8900_ADC_LRCLK:
845 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
846 snd_soc_write(codec, WM8900_REG_AUDIO3,
847 div | (reg & WM8900_LRC_MASK));
849 case WM8900_DAC_CLKDIV:
850 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
851 snd_soc_write(codec, WM8900_REG_CLOCKING2,
852 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
854 case WM8900_ADC_CLKDIV:
855 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
856 snd_soc_write(codec, WM8900_REG_CLOCKING2,
857 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
859 case WM8900_LRCLK_MODE:
860 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
861 snd_soc_write(codec, WM8900_REG_DACCTRL,
862 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
872 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
875 struct snd_soc_codec *codec = codec_dai->codec;
876 unsigned int clocking1, aif1, aif3, aif4;
878 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
879 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
880 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
881 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
883 /* set master/slave audio interface */
884 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
885 case SND_SOC_DAIFMT_CBS_CFS:
886 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
887 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
888 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
890 case SND_SOC_DAIFMT_CBS_CFM:
891 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
892 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
893 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
895 case SND_SOC_DAIFMT_CBM_CFM:
896 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
897 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
898 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
900 case SND_SOC_DAIFMT_CBM_CFS:
901 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
902 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
903 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
909 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
910 case SND_SOC_DAIFMT_DSP_A:
911 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
912 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
914 case SND_SOC_DAIFMT_DSP_B:
915 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
916 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
918 case SND_SOC_DAIFMT_I2S:
919 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
922 case SND_SOC_DAIFMT_RIGHT_J:
923 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
925 case SND_SOC_DAIFMT_LEFT_J:
926 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
933 /* Clock inversion */
934 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
935 case SND_SOC_DAIFMT_DSP_A:
936 case SND_SOC_DAIFMT_DSP_B:
937 /* frame inversion not valid for DSP modes */
938 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
939 case SND_SOC_DAIFMT_NB_NF:
940 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
942 case SND_SOC_DAIFMT_IB_NF:
943 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
949 case SND_SOC_DAIFMT_I2S:
950 case SND_SOC_DAIFMT_RIGHT_J:
951 case SND_SOC_DAIFMT_LEFT_J:
952 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
953 case SND_SOC_DAIFMT_NB_NF:
954 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
955 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
957 case SND_SOC_DAIFMT_IB_IF:
958 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
959 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
961 case SND_SOC_DAIFMT_IB_NF:
962 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
963 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
965 case SND_SOC_DAIFMT_NB_IF:
966 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
967 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
977 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
978 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
979 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
980 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
985 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
987 struct snd_soc_codec *codec = codec_dai->codec;
990 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
993 reg |= WM8900_REG_DACCTRL_MUTE;
995 reg &= ~WM8900_REG_DACCTRL_MUTE;
997 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
1002 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1003 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1004 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1006 #define WM8900_PCM_FORMATS \
1007 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1008 SNDRV_PCM_FORMAT_S24_LE)
1010 static struct snd_soc_dai_ops wm8900_dai_ops = {
1011 .hw_params = wm8900_hw_params,
1012 .set_clkdiv = wm8900_set_dai_clkdiv,
1013 .set_pll = wm8900_set_dai_pll,
1014 .set_fmt = wm8900_set_dai_fmt,
1015 .digital_mute = wm8900_digital_mute,
1018 struct snd_soc_dai wm8900_dai = {
1019 .name = "WM8900 HiFi",
1021 .stream_name = "HiFi Playback",
1024 .rates = WM8900_RATES,
1025 .formats = WM8900_PCM_FORMATS,
1028 .stream_name = "HiFi Capture",
1031 .rates = WM8900_RATES,
1032 .formats = WM8900_PCM_FORMATS,
1034 .ops = &wm8900_dai_ops,
1036 EXPORT_SYMBOL_GPL(wm8900_dai);
1038 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1039 enum snd_soc_bias_level level)
1044 case SND_SOC_BIAS_ON:
1045 /* Enable thermal shutdown */
1046 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1047 snd_soc_write(codec, WM8900_REG_GPIO,
1048 reg | WM8900_REG_GPIO_TEMP_ENA);
1049 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1050 snd_soc_write(codec, WM8900_REG_ADDCTL,
1051 reg | WM8900_REG_ADDCTL_TEMP_SD);
1054 case SND_SOC_BIAS_PREPARE:
1057 case SND_SOC_BIAS_STANDBY:
1058 /* Charge capacitors if initial power up */
1059 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1060 /* STARTUP_BIAS_ENA on */
1061 snd_soc_write(codec, WM8900_REG_POWER1,
1062 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1064 /* Startup bias mode */
1065 snd_soc_write(codec, WM8900_REG_ADDCTL,
1066 WM8900_REG_ADDCTL_BIAS_SRC |
1067 WM8900_REG_ADDCTL_VMID_SOFTST);
1070 snd_soc_write(codec, WM8900_REG_POWER1,
1071 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1073 /* Allow capacitors to charge */
1074 schedule_timeout_interruptible(msecs_to_jiffies(400));
1077 snd_soc_write(codec, WM8900_REG_POWER1,
1078 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1079 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1083 snd_soc_write(codec, WM8900_REG_POWER1,
1084 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1087 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1088 snd_soc_write(codec, WM8900_REG_POWER1,
1089 (reg & WM8900_REG_POWER1_FLL_ENA) |
1090 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1091 snd_soc_write(codec, WM8900_REG_POWER2,
1092 WM8900_REG_POWER2_SYSCLK_ENA);
1093 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1096 case SND_SOC_BIAS_OFF:
1097 /* Startup bias enable */
1098 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1099 snd_soc_write(codec, WM8900_REG_POWER1,
1100 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1101 snd_soc_write(codec, WM8900_REG_ADDCTL,
1102 WM8900_REG_ADDCTL_BIAS_SRC |
1103 WM8900_REG_ADDCTL_VMID_SOFTST);
1105 /* Discharge caps */
1106 snd_soc_write(codec, WM8900_REG_POWER1,
1107 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1108 schedule_timeout_interruptible(msecs_to_jiffies(500));
1111 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1114 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1115 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1116 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1117 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1119 /* Need to let things settle before stopping the clock
1120 * to ensure that restart works, see "Stopping the
1121 * master clock" in the datasheet. */
1122 schedule_timeout_interruptible(msecs_to_jiffies(1));
1123 snd_soc_write(codec, WM8900_REG_POWER2,
1124 WM8900_REG_POWER2_SYSCLK_ENA);
1127 codec->bias_level = level;
1131 static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1133 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1134 struct snd_soc_codec *codec = socdev->card->codec;
1135 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1136 int fll_out = wm8900->fll_out;
1137 int fll_in = wm8900->fll_in;
1140 /* Stop the FLL in an orderly fashion */
1141 ret = wm8900_set_fll(codec, 0, 0, 0);
1143 dev_err(&pdev->dev, "Failed to stop FLL\n");
1147 wm8900->fll_out = fll_out;
1148 wm8900->fll_in = fll_in;
1150 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1155 static int wm8900_resume(struct platform_device *pdev)
1157 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1158 struct snd_soc_codec *codec = socdev->card->codec;
1159 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1163 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1166 wm8900_reset(codec);
1167 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1169 /* Restart the FLL? */
1170 if (wm8900->fll_out) {
1171 int fll_out = wm8900->fll_out;
1172 int fll_in = wm8900->fll_in;
1175 wm8900->fll_out = 0;
1177 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1179 dev_err(&pdev->dev, "Failed to restart FLL\n");
1185 for (i = 0; i < WM8900_MAXREG; i++)
1186 snd_soc_write(codec, i, cache[i]);
1189 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1194 static struct snd_soc_codec *wm8900_codec;
1196 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1197 const struct i2c_device_id *id)
1199 struct wm8900_priv *wm8900;
1200 struct snd_soc_codec *codec;
1204 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1208 codec = &wm8900->codec;
1209 snd_soc_codec_set_drvdata(codec, wm8900);
1210 codec->reg_cache = &wm8900->reg_cache[0];
1211 codec->reg_cache_size = WM8900_MAXREG;
1213 mutex_init(&codec->mutex);
1214 INIT_LIST_HEAD(&codec->dapm_widgets);
1215 INIT_LIST_HEAD(&codec->dapm_paths);
1217 codec->name = "WM8900";
1218 codec->owner = THIS_MODULE;
1219 codec->dai = &wm8900_dai;
1221 codec->control_data = i2c;
1222 codec->set_bias_level = wm8900_set_bias_level;
1223 codec->volatile_register = wm8900_volatile_register;
1224 codec->dev = &i2c->dev;
1226 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1228 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1232 reg = snd_soc_read(codec, WM8900_REG_ID);
1233 if (reg != 0x8900) {
1234 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1239 /* Read back from the chip */
1240 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1241 reg = (reg >> 12) & 0xf;
1242 dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
1244 wm8900_reset(codec);
1246 /* Turn the chip on */
1247 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1249 /* Latch the volume update bits */
1250 snd_soc_write(codec, WM8900_REG_LINVOL,
1251 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1252 snd_soc_write(codec, WM8900_REG_RINVOL,
1253 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1254 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1255 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1256 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1257 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1258 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1259 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1260 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1261 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1262 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1263 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1264 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1265 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1266 snd_soc_write(codec, WM8900_REG_LADC_DV,
1267 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1268 snd_soc_write(codec, WM8900_REG_RADC_DV,
1269 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1271 /* Set the DAC and mixer output bias */
1272 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1274 wm8900_dai.dev = &i2c->dev;
1276 wm8900_codec = codec;
1278 ret = snd_soc_register_codec(codec);
1280 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1284 ret = snd_soc_register_dai(&wm8900_dai);
1286 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1293 snd_soc_unregister_codec(codec);
1296 wm8900_codec = NULL;
1300 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1302 snd_soc_unregister_dai(&wm8900_dai);
1303 snd_soc_unregister_codec(wm8900_codec);
1305 wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
1307 wm8900_dai.dev = NULL;
1308 kfree(snd_soc_codec_get_drvdata(wm8900_codec));
1309 wm8900_codec = NULL;
1314 static const struct i2c_device_id wm8900_i2c_id[] = {
1318 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1320 static struct i2c_driver wm8900_i2c_driver = {
1323 .owner = THIS_MODULE,
1325 .probe = wm8900_i2c_probe,
1326 .remove = __devexit_p(wm8900_i2c_remove),
1327 .id_table = wm8900_i2c_id,
1330 static int wm8900_probe(struct platform_device *pdev)
1332 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1333 struct snd_soc_codec *codec;
1336 if (!wm8900_codec) {
1337 dev_err(&pdev->dev, "I2C client not yet instantiated\n");
1341 codec = wm8900_codec;
1342 socdev->card->codec = codec;
1345 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1347 dev_err(&pdev->dev, "Failed to register new PCMs\n");
1351 snd_soc_add_controls(codec, wm8900_snd_controls,
1352 ARRAY_SIZE(wm8900_snd_controls));
1353 wm8900_add_widgets(codec);
1359 /* power down chip */
1360 static int wm8900_remove(struct platform_device *pdev)
1362 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1364 snd_soc_free_pcms(socdev);
1365 snd_soc_dapm_free(socdev);
1370 struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1371 .probe = wm8900_probe,
1372 .remove = wm8900_remove,
1373 .suspend = wm8900_suspend,
1374 .resume = wm8900_resume,
1376 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1378 static int __init wm8900_modinit(void)
1380 return i2c_add_driver(&wm8900_i2c_driver);
1382 module_init(wm8900_modinit);
1384 static void __exit wm8900_exit(void)
1386 i2c_del_driver(&wm8900_i2c_driver);
1388 module_exit(wm8900_exit);
1390 MODULE_DESCRIPTION("ASoC WM8900 driver");
1391 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1392 MODULE_LICENSE("GPL");