2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/spi/spi.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
38 /* WM8900 register space */
39 #define WM8900_REG_RESET 0x0
40 #define WM8900_REG_ID 0x0
41 #define WM8900_REG_POWER1 0x1
42 #define WM8900_REG_POWER2 0x2
43 #define WM8900_REG_POWER3 0x3
44 #define WM8900_REG_AUDIO1 0x4
45 #define WM8900_REG_AUDIO2 0x5
46 #define WM8900_REG_CLOCKING1 0x6
47 #define WM8900_REG_CLOCKING2 0x7
48 #define WM8900_REG_AUDIO3 0x8
49 #define WM8900_REG_AUDIO4 0x9
50 #define WM8900_REG_DACCTRL 0xa
51 #define WM8900_REG_LDAC_DV 0xb
52 #define WM8900_REG_RDAC_DV 0xc
53 #define WM8900_REG_SIDETONE 0xd
54 #define WM8900_REG_ADCCTRL 0xe
55 #define WM8900_REG_LADC_DV 0xf
56 #define WM8900_REG_RADC_DV 0x10
57 #define WM8900_REG_GPIO 0x12
58 #define WM8900_REG_INCTL 0x15
59 #define WM8900_REG_LINVOL 0x16
60 #define WM8900_REG_RINVOL 0x17
61 #define WM8900_REG_INBOOSTMIX1 0x18
62 #define WM8900_REG_INBOOSTMIX2 0x19
63 #define WM8900_REG_ADCPATH 0x1a
64 #define WM8900_REG_AUXBOOST 0x1b
65 #define WM8900_REG_ADDCTL 0x1e
66 #define WM8900_REG_FLLCTL1 0x24
67 #define WM8900_REG_FLLCTL2 0x25
68 #define WM8900_REG_FLLCTL3 0x26
69 #define WM8900_REG_FLLCTL4 0x27
70 #define WM8900_REG_FLLCTL5 0x28
71 #define WM8900_REG_FLLCTL6 0x29
72 #define WM8900_REG_LOUTMIXCTL1 0x2c
73 #define WM8900_REG_ROUTMIXCTL1 0x2d
74 #define WM8900_REG_BYPASS1 0x2e
75 #define WM8900_REG_BYPASS2 0x2f
76 #define WM8900_REG_AUXOUT_CTL 0x30
77 #define WM8900_REG_LOUT1CTL 0x33
78 #define WM8900_REG_ROUT1CTL 0x34
79 #define WM8900_REG_LOUT2CTL 0x35
80 #define WM8900_REG_ROUT2CTL 0x36
81 #define WM8900_REG_HPCTL1 0x3a
82 #define WM8900_REG_OUTBIASCTL 0x73
84 #define WM8900_MAXREG 0x80
86 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
89 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
93 #define WM8900_REG_GPIO_TEMP_ENA 0x2
95 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
97 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98 #define WM8900_REG_POWER1_FLL_ENA 0x0040
100 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
102 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
104 #define WM8900_REG_POWER3_DACL_ENA 0x0002
105 #define WM8900_REG_POWER3_DACR_ENA 0x0001
107 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
111 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
114 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
116 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
119 #define WM8900_REG_DACCTRL_MUTE 0x004
120 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
121 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
123 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
125 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
127 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
129 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
131 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
136 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
138 #define WM8900_LRC_MASK 0xfc00
141 enum snd_soc_control_type control_type;
143 u32 fll_in; /* FLL input frequency */
144 u32 fll_out; /* FLL output frequency */
148 * wm8900 register cache. We can't read the entire register space and we
149 * have slow control buses so we cache the registers.
151 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
180 /* Remaining registers all zero */
183 static int wm8900_volatile_register(unsigned int reg)
193 static void wm8900_reset(struct snd_soc_codec *codec)
195 snd_soc_write(codec, WM8900_REG_RESET, 0);
197 memcpy(codec->reg_cache, wm8900_reg_defaults,
198 sizeof(wm8900_reg_defaults));
201 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
202 struct snd_kcontrol *kcontrol, int event)
204 struct snd_soc_codec *codec = w->codec;
205 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
208 case SND_SOC_DAPM_PRE_PMU:
209 /* Clamp headphone outputs */
210 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
211 WM8900_REG_HPCTL1_HP_CLAMP_OP;
212 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
215 case SND_SOC_DAPM_POST_PMU:
216 /* Enable the input stage */
217 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
218 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
219 WM8900_REG_HPCTL1_HP_SHORT2 |
220 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
221 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
225 /* Enable the output stage */
226 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
227 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
228 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
230 /* Remove the shorts */
231 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
233 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
234 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
237 case SND_SOC_DAPM_PRE_PMD:
238 /* Short the output */
239 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
240 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
242 /* Disable the output stage */
243 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
246 /* Clamp the outputs and power down input */
247 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
248 WM8900_REG_HPCTL1_HP_CLAMP_OP;
249 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
250 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
253 case SND_SOC_DAPM_POST_PMD:
254 /* Disable everything */
255 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
265 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
267 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
269 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
271 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
273 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
275 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
277 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
279 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
281 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
283 static const struct soc_enum mic_bias_level =
284 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
286 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
288 static const struct soc_enum dac_mute_rate =
289 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
291 static const char *dac_deemphasis_txt[] = {
292 "Disabled", "32kHz", "44.1kHz", "48kHz"
295 static const struct soc_enum dac_deemphasis =
296 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
298 static const char *adc_hpf_cut_txt[] = {
299 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
302 static const struct soc_enum adc_hpf_cut =
303 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
305 static const char *lr_txt[] = {
309 static const struct soc_enum aifl_src =
310 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
312 static const struct soc_enum aifr_src =
313 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
315 static const struct soc_enum dacl_src =
316 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
318 static const struct soc_enum dacr_src =
319 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
321 static const char *sidetone_txt[] = {
322 "Disabled", "Left ADC", "Right ADC"
325 static const struct soc_enum dacl_sidetone =
326 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
328 static const struct soc_enum dacr_sidetone =
329 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
331 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
332 SOC_ENUM("Mic Bias Level", mic_bias_level),
334 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
336 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
337 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
339 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
341 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
342 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
344 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
345 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
346 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
347 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
348 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
351 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
352 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
353 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
354 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
356 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
358 SOC_ENUM("Left Digital Audio Source", aifl_src),
359 SOC_ENUM("Right Digital Audio Source", aifr_src),
361 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
363 SOC_ENUM("Left DAC Source", dacl_src),
364 SOC_ENUM("Right DAC Source", dacr_src),
365 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
366 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
367 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
369 SOC_DOUBLE_R_TLV("Digital Playback Volume",
370 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
372 SOC_DOUBLE_R_TLV("Digital Capture Volume",
373 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
375 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
377 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
379 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
381 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
384 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
386 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
388 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
390 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
393 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
395 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
397 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
399 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
401 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
403 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
406 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
407 0, 63, 0, out_pga_tlv),
408 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
410 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
413 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
414 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
415 0, 63, 0, out_pga_tlv),
416 SOC_DOUBLE_R("LINEOUT2 Switch",
417 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
418 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
419 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
420 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
425 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
426 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
428 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
429 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
431 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
432 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
433 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
434 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
435 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
436 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
439 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
440 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
441 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
442 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
443 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
444 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
447 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
448 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
449 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
450 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
451 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
454 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
455 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
456 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
457 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
458 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
461 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
462 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
463 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
464 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
467 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
468 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
469 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
470 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
473 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
475 static const struct soc_enum wm8900_lineout2_lp_mux =
476 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
478 static const struct snd_kcontrol_new wm8900_lineout2_lp =
479 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
481 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
483 /* Externally visible pins */
484 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
485 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
486 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
487 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
488 SND_SOC_DAPM_OUTPUT("HP_L"),
489 SND_SOC_DAPM_OUTPUT("HP_R"),
491 SND_SOC_DAPM_INPUT("RINPUT1"),
492 SND_SOC_DAPM_INPUT("LINPUT1"),
493 SND_SOC_DAPM_INPUT("RINPUT2"),
494 SND_SOC_DAPM_INPUT("LINPUT2"),
495 SND_SOC_DAPM_INPUT("RINPUT3"),
496 SND_SOC_DAPM_INPUT("LINPUT3"),
497 SND_SOC_DAPM_INPUT("AUX"),
499 SND_SOC_DAPM_VMID("VMID"),
502 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
503 wm8900_linpga_controls,
504 ARRAY_SIZE(wm8900_linpga_controls)),
505 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
506 wm8900_rinpga_controls,
507 ARRAY_SIZE(wm8900_rinpga_controls)),
509 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
510 wm8900_linmix_controls,
511 ARRAY_SIZE(wm8900_linmix_controls)),
512 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
513 wm8900_rinmix_controls,
514 ARRAY_SIZE(wm8900_rinmix_controls)),
516 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
518 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
519 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
522 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
523 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
525 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
528 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
530 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
531 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
533 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
534 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
535 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
537 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
538 wm8900_loutmix_controls,
539 ARRAY_SIZE(wm8900_loutmix_controls)),
540 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
541 wm8900_routmix_controls,
542 ARRAY_SIZE(wm8900_routmix_controls)),
545 /* Target, Path, Source */
546 static const struct snd_soc_dapm_route audio_map[] = {
548 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
549 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
550 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
552 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
553 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
554 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
556 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
557 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
558 {"Left Input Mixer", "AUX Switch", "AUX"},
559 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
561 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
562 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
563 {"Right Input Mixer", "AUX Switch", "AUX"},
564 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
566 {"ADCL", NULL, "Left Input Mixer"},
567 {"ADCR", NULL, "Right Input Mixer"},
570 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
571 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
572 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
573 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
575 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
576 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
577 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
578 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
580 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
581 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
582 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
583 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
585 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
586 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
587 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
588 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
589 {"Left Output Mixer", "DACL Switch", "DACL"},
591 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
592 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
593 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
594 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
595 {"Right Output Mixer", "DACR Switch", "DACR"},
597 /* Note that the headphone output stage needs to be connected
598 * externally to LINEOUT2 via DC blocking capacitors. Other
599 * configurations are not supported.
601 * Note also that left and right headphone paths are treated as a
604 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
605 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
606 {"HP_L", NULL, "Headphone Amplifier"},
607 {"HP_R", NULL, "Headphone Amplifier"},
610 static int wm8900_add_widgets(struct snd_soc_codec *codec)
612 struct snd_soc_dapm_context *dapm = &codec->dapm;
614 snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
615 ARRAY_SIZE(wm8900_dapm_widgets));
616 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
621 static int wm8900_hw_params(struct snd_pcm_substream *substream,
622 struct snd_pcm_hw_params *params,
623 struct snd_soc_dai *dai)
625 struct snd_soc_pcm_runtime *rtd = substream->private_data;
626 struct snd_soc_codec *codec = rtd->codec;
629 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
631 switch (params_format(params)) {
632 case SNDRV_PCM_FORMAT_S16_LE:
634 case SNDRV_PCM_FORMAT_S20_3LE:
637 case SNDRV_PCM_FORMAT_S24_LE:
640 case SNDRV_PCM_FORMAT_S32_LE:
647 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
649 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
650 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
652 if (params_rate(params) <= 24000)
653 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
655 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
657 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
667 u16 fll_slow_lock_ref;
672 /* The size in bits of the FLL divide multiplied by 10
673 * to allow rounding later */
674 #define FIXED_FLL_SIZE ((1 << 16) * 10)
676 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
680 unsigned int K, Ndiv, Nmod, target;
685 /* The FLL must run at 90-100MHz which is then scaled down to
686 * the output value by FLLCLK_DIV. */
689 while (target < 90000000) {
694 if (target > 100000000)
695 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
696 " Fout=%u\n", target, Fref, Fout);
698 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
699 "Fref=%u, Fout=%u, target=%u\n",
700 div, Fref, Fout, target);
704 fll_div->fllclk_div = div >> 2;
707 fll_div->fll_slow_lock_ref = 1;
709 fll_div->fll_slow_lock_ref = 0;
711 Ndiv = target / Fref;
714 fll_div->fll_ratio = 8;
716 fll_div->fll_ratio = 1;
718 fll_div->n = Ndiv / fll_div->fll_ratio;
719 Nmod = (target / fll_div->fll_ratio) % Fref;
721 /* Calculate fractional part - scale up so we can round. */
722 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
726 K = Kpart & 0xFFFFFFFF;
731 /* Move down to proper range now rounding is done */
734 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
735 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
740 static int wm8900_set_fll(struct snd_soc_codec *codec,
741 int fll_id, unsigned int freq_in, unsigned int freq_out)
743 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
744 struct _fll_div fll_div;
747 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
750 /* The digital side should be disabled during any change. */
751 reg = snd_soc_read(codec, WM8900_REG_POWER1);
752 snd_soc_write(codec, WM8900_REG_POWER1,
753 reg & (~WM8900_REG_POWER1_FLL_ENA));
755 /* Disable the FLL? */
756 if (!freq_in || !freq_out) {
757 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
758 snd_soc_write(codec, WM8900_REG_CLOCKING1,
759 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
761 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
762 snd_soc_write(codec, WM8900_REG_FLLCTL1,
763 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
765 wm8900->fll_in = freq_in;
766 wm8900->fll_out = freq_out;
771 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
774 wm8900->fll_in = freq_in;
775 wm8900->fll_out = freq_out;
777 /* The osclilator *MUST* be enabled before we enable the
778 * digital circuit. */
779 snd_soc_write(codec, WM8900_REG_FLLCTL1,
780 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
782 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
783 snd_soc_write(codec, WM8900_REG_FLLCTL5,
784 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
787 snd_soc_write(codec, WM8900_REG_FLLCTL2,
788 (fll_div.k >> 8) | 0x100);
789 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
791 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
793 if (fll_div.fll_slow_lock_ref)
794 snd_soc_write(codec, WM8900_REG_FLLCTL6,
795 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
797 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
799 reg = snd_soc_read(codec, WM8900_REG_POWER1);
800 snd_soc_write(codec, WM8900_REG_POWER1,
801 reg | WM8900_REG_POWER1_FLL_ENA);
804 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
805 snd_soc_write(codec, WM8900_REG_CLOCKING1,
806 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
811 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
812 int source, unsigned int freq_in, unsigned int freq_out)
814 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
817 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
820 struct snd_soc_codec *codec = codec_dai->codec;
824 case WM8900_BCLK_DIV:
825 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
826 snd_soc_write(codec, WM8900_REG_CLOCKING1,
827 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
829 case WM8900_OPCLK_DIV:
830 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
831 snd_soc_write(codec, WM8900_REG_CLOCKING1,
832 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
834 case WM8900_DAC_LRCLK:
835 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
836 snd_soc_write(codec, WM8900_REG_AUDIO4,
837 div | (reg & WM8900_LRC_MASK));
839 case WM8900_ADC_LRCLK:
840 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
841 snd_soc_write(codec, WM8900_REG_AUDIO3,
842 div | (reg & WM8900_LRC_MASK));
844 case WM8900_DAC_CLKDIV:
845 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
846 snd_soc_write(codec, WM8900_REG_CLOCKING2,
847 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
849 case WM8900_ADC_CLKDIV:
850 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
851 snd_soc_write(codec, WM8900_REG_CLOCKING2,
852 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
854 case WM8900_LRCLK_MODE:
855 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
856 snd_soc_write(codec, WM8900_REG_DACCTRL,
857 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
867 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
870 struct snd_soc_codec *codec = codec_dai->codec;
871 unsigned int clocking1, aif1, aif3, aif4;
873 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
874 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
875 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
876 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
878 /* set master/slave audio interface */
879 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
880 case SND_SOC_DAIFMT_CBS_CFS:
881 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
882 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
883 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
885 case SND_SOC_DAIFMT_CBS_CFM:
886 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
887 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
888 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
890 case SND_SOC_DAIFMT_CBM_CFM:
891 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
892 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
893 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
895 case SND_SOC_DAIFMT_CBM_CFS:
896 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
897 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
898 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
904 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
905 case SND_SOC_DAIFMT_DSP_A:
906 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
907 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
909 case SND_SOC_DAIFMT_DSP_B:
910 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
911 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
913 case SND_SOC_DAIFMT_I2S:
914 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
917 case SND_SOC_DAIFMT_RIGHT_J:
918 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
920 case SND_SOC_DAIFMT_LEFT_J:
921 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
928 /* Clock inversion */
929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
930 case SND_SOC_DAIFMT_DSP_A:
931 case SND_SOC_DAIFMT_DSP_B:
932 /* frame inversion not valid for DSP modes */
933 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
934 case SND_SOC_DAIFMT_NB_NF:
935 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
937 case SND_SOC_DAIFMT_IB_NF:
938 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
944 case SND_SOC_DAIFMT_I2S:
945 case SND_SOC_DAIFMT_RIGHT_J:
946 case SND_SOC_DAIFMT_LEFT_J:
947 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
948 case SND_SOC_DAIFMT_NB_NF:
949 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
950 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
952 case SND_SOC_DAIFMT_IB_IF:
953 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
954 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
956 case SND_SOC_DAIFMT_IB_NF:
957 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
958 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
960 case SND_SOC_DAIFMT_NB_IF:
961 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
962 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
972 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
973 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
974 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
975 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
980 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
982 struct snd_soc_codec *codec = codec_dai->codec;
985 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
988 reg |= WM8900_REG_DACCTRL_MUTE;
990 reg &= ~WM8900_REG_DACCTRL_MUTE;
992 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
997 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
998 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
999 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1001 #define WM8900_PCM_FORMATS \
1002 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1003 SNDRV_PCM_FORMAT_S24_LE)
1005 static struct snd_soc_dai_ops wm8900_dai_ops = {
1006 .hw_params = wm8900_hw_params,
1007 .set_clkdiv = wm8900_set_dai_clkdiv,
1008 .set_pll = wm8900_set_dai_pll,
1009 .set_fmt = wm8900_set_dai_fmt,
1010 .digital_mute = wm8900_digital_mute,
1013 static struct snd_soc_dai_driver wm8900_dai = {
1014 .name = "wm8900-hifi",
1016 .stream_name = "HiFi Playback",
1019 .rates = WM8900_RATES,
1020 .formats = WM8900_PCM_FORMATS,
1023 .stream_name = "HiFi Capture",
1026 .rates = WM8900_RATES,
1027 .formats = WM8900_PCM_FORMATS,
1029 .ops = &wm8900_dai_ops,
1032 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1033 enum snd_soc_bias_level level)
1038 case SND_SOC_BIAS_ON:
1039 /* Enable thermal shutdown */
1040 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1041 snd_soc_write(codec, WM8900_REG_GPIO,
1042 reg | WM8900_REG_GPIO_TEMP_ENA);
1043 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1044 snd_soc_write(codec, WM8900_REG_ADDCTL,
1045 reg | WM8900_REG_ADDCTL_TEMP_SD);
1048 case SND_SOC_BIAS_PREPARE:
1051 case SND_SOC_BIAS_STANDBY:
1052 /* Charge capacitors if initial power up */
1053 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1054 /* STARTUP_BIAS_ENA on */
1055 snd_soc_write(codec, WM8900_REG_POWER1,
1056 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1058 /* Startup bias mode */
1059 snd_soc_write(codec, WM8900_REG_ADDCTL,
1060 WM8900_REG_ADDCTL_BIAS_SRC |
1061 WM8900_REG_ADDCTL_VMID_SOFTST);
1064 snd_soc_write(codec, WM8900_REG_POWER1,
1065 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1067 /* Allow capacitors to charge */
1068 schedule_timeout_interruptible(msecs_to_jiffies(400));
1071 snd_soc_write(codec, WM8900_REG_POWER1,
1072 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1073 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1075 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1077 snd_soc_write(codec, WM8900_REG_POWER1,
1078 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1082 snd_soc_write(codec, WM8900_REG_POWER1,
1083 (reg & WM8900_REG_POWER1_FLL_ENA) |
1084 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1085 snd_soc_write(codec, WM8900_REG_POWER2,
1086 WM8900_REG_POWER2_SYSCLK_ENA);
1087 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1090 case SND_SOC_BIAS_OFF:
1091 /* Startup bias enable */
1092 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1093 snd_soc_write(codec, WM8900_REG_POWER1,
1094 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1095 snd_soc_write(codec, WM8900_REG_ADDCTL,
1096 WM8900_REG_ADDCTL_BIAS_SRC |
1097 WM8900_REG_ADDCTL_VMID_SOFTST);
1099 /* Discharge caps */
1100 snd_soc_write(codec, WM8900_REG_POWER1,
1101 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1102 schedule_timeout_interruptible(msecs_to_jiffies(500));
1105 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1108 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1109 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1110 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1111 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1113 /* Need to let things settle before stopping the clock
1114 * to ensure that restart works, see "Stopping the
1115 * master clock" in the datasheet. */
1116 schedule_timeout_interruptible(msecs_to_jiffies(1));
1117 snd_soc_write(codec, WM8900_REG_POWER2,
1118 WM8900_REG_POWER2_SYSCLK_ENA);
1121 codec->dapm.bias_level = level;
1125 static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
1127 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1128 int fll_out = wm8900->fll_out;
1129 int fll_in = wm8900->fll_in;
1132 /* Stop the FLL in an orderly fashion */
1133 ret = wm8900_set_fll(codec, 0, 0, 0);
1135 dev_err(codec->dev, "Failed to stop FLL\n");
1139 wm8900->fll_out = fll_out;
1140 wm8900->fll_in = fll_in;
1142 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1147 static int wm8900_resume(struct snd_soc_codec *codec)
1149 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1153 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1156 wm8900_reset(codec);
1157 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1159 /* Restart the FLL? */
1160 if (wm8900->fll_out) {
1161 int fll_out = wm8900->fll_out;
1162 int fll_in = wm8900->fll_in;
1165 wm8900->fll_out = 0;
1167 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1169 dev_err(codec->dev, "Failed to restart FLL\n");
1175 for (i = 0; i < WM8900_MAXREG; i++)
1176 snd_soc_write(codec, i, cache[i]);
1179 dev_err(codec->dev, "Unable to allocate register cache\n");
1184 static int wm8900_probe(struct snd_soc_codec *codec)
1186 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1189 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
1191 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1195 reg = snd_soc_read(codec, WM8900_REG_ID);
1196 if (reg != 0x8900) {
1197 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1201 wm8900_reset(codec);
1203 /* Turn the chip on */
1204 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1206 /* Latch the volume update bits */
1207 snd_soc_write(codec, WM8900_REG_LINVOL,
1208 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1209 snd_soc_write(codec, WM8900_REG_RINVOL,
1210 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1211 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1212 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1213 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1214 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1215 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1216 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1217 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1218 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1219 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1220 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1221 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1222 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1223 snd_soc_write(codec, WM8900_REG_LADC_DV,
1224 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1225 snd_soc_write(codec, WM8900_REG_RADC_DV,
1226 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1228 /* Set the DAC and mixer output bias */
1229 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1231 snd_soc_add_controls(codec, wm8900_snd_controls,
1232 ARRAY_SIZE(wm8900_snd_controls));
1233 wm8900_add_widgets(codec);
1238 /* power down chip */
1239 static int wm8900_remove(struct snd_soc_codec *codec)
1241 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1245 static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1246 .probe = wm8900_probe,
1247 .remove = wm8900_remove,
1248 .suspend = wm8900_suspend,
1249 .resume = wm8900_resume,
1250 .set_bias_level = wm8900_set_bias_level,
1251 .volatile_register = wm8900_volatile_register,
1252 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
1253 .reg_word_size = sizeof(u16),
1254 .reg_cache_default = wm8900_reg_defaults,
1257 #if defined(CONFIG_SPI_MASTER)
1258 static int __devinit wm8900_spi_probe(struct spi_device *spi)
1260 struct wm8900_priv *wm8900;
1263 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1267 wm8900->control_type = SND_SOC_SPI;
1268 spi_set_drvdata(spi, wm8900);
1270 ret = snd_soc_register_codec(&spi->dev,
1271 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1277 static int __devexit wm8900_spi_remove(struct spi_device *spi)
1279 snd_soc_unregister_codec(&spi->dev);
1280 kfree(spi_get_drvdata(spi));
1284 static struct spi_driver wm8900_spi_driver = {
1286 .name = "wm8900-codec",
1287 .owner = THIS_MODULE,
1289 .probe = wm8900_spi_probe,
1290 .remove = __devexit_p(wm8900_spi_remove),
1292 #endif /* CONFIG_SPI_MASTER */
1294 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1295 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1296 const struct i2c_device_id *id)
1298 struct wm8900_priv *wm8900;
1301 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1305 i2c_set_clientdata(i2c, wm8900);
1306 wm8900->control_type = SND_SOC_I2C;
1308 ret = snd_soc_register_codec(&i2c->dev,
1309 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1315 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1317 snd_soc_unregister_codec(&client->dev);
1318 kfree(i2c_get_clientdata(client));
1322 static const struct i2c_device_id wm8900_i2c_id[] = {
1326 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1328 static struct i2c_driver wm8900_i2c_driver = {
1330 .name = "wm8900-codec",
1331 .owner = THIS_MODULE,
1333 .probe = wm8900_i2c_probe,
1334 .remove = __devexit_p(wm8900_i2c_remove),
1335 .id_table = wm8900_i2c_id,
1339 static int __init wm8900_modinit(void)
1342 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1343 ret = i2c_add_driver(&wm8900_i2c_driver);
1345 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1349 #if defined(CONFIG_SPI_MASTER)
1350 ret = spi_register_driver(&wm8900_spi_driver);
1352 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1358 module_init(wm8900_modinit);
1360 static void __exit wm8900_exit(void)
1362 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1363 i2c_del_driver(&wm8900_i2c_driver);
1365 #if defined(CONFIG_SPI_MASTER)
1366 spi_unregister_driver(&wm8900_spi_driver);
1369 module_exit(wm8900_exit);
1371 MODULE_DESCRIPTION("ASoC WM8900 driver");
1372 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1373 MODULE_LICENSE("GPL");