2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/spi/spi.h>
27 #include <linux/slab.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/initval.h>
33 #include <sound/tlv.h>
37 /* WM8900 register space */
38 #define WM8900_REG_RESET 0x0
39 #define WM8900_REG_ID 0x0
40 #define WM8900_REG_POWER1 0x1
41 #define WM8900_REG_POWER2 0x2
42 #define WM8900_REG_POWER3 0x3
43 #define WM8900_REG_AUDIO1 0x4
44 #define WM8900_REG_AUDIO2 0x5
45 #define WM8900_REG_CLOCKING1 0x6
46 #define WM8900_REG_CLOCKING2 0x7
47 #define WM8900_REG_AUDIO3 0x8
48 #define WM8900_REG_AUDIO4 0x9
49 #define WM8900_REG_DACCTRL 0xa
50 #define WM8900_REG_LDAC_DV 0xb
51 #define WM8900_REG_RDAC_DV 0xc
52 #define WM8900_REG_SIDETONE 0xd
53 #define WM8900_REG_ADCCTRL 0xe
54 #define WM8900_REG_LADC_DV 0xf
55 #define WM8900_REG_RADC_DV 0x10
56 #define WM8900_REG_GPIO 0x12
57 #define WM8900_REG_INCTL 0x15
58 #define WM8900_REG_LINVOL 0x16
59 #define WM8900_REG_RINVOL 0x17
60 #define WM8900_REG_INBOOSTMIX1 0x18
61 #define WM8900_REG_INBOOSTMIX2 0x19
62 #define WM8900_REG_ADCPATH 0x1a
63 #define WM8900_REG_AUXBOOST 0x1b
64 #define WM8900_REG_ADDCTL 0x1e
65 #define WM8900_REG_FLLCTL1 0x24
66 #define WM8900_REG_FLLCTL2 0x25
67 #define WM8900_REG_FLLCTL3 0x26
68 #define WM8900_REG_FLLCTL4 0x27
69 #define WM8900_REG_FLLCTL5 0x28
70 #define WM8900_REG_FLLCTL6 0x29
71 #define WM8900_REG_LOUTMIXCTL1 0x2c
72 #define WM8900_REG_ROUTMIXCTL1 0x2d
73 #define WM8900_REG_BYPASS1 0x2e
74 #define WM8900_REG_BYPASS2 0x2f
75 #define WM8900_REG_AUXOUT_CTL 0x30
76 #define WM8900_REG_LOUT1CTL 0x33
77 #define WM8900_REG_ROUT1CTL 0x34
78 #define WM8900_REG_LOUT2CTL 0x35
79 #define WM8900_REG_ROUT2CTL 0x36
80 #define WM8900_REG_HPCTL1 0x3a
81 #define WM8900_REG_OUTBIASCTL 0x73
83 #define WM8900_MAXREG 0x80
85 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
88 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
92 #define WM8900_REG_GPIO_TEMP_ENA 0x2
94 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
96 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97 #define WM8900_REG_POWER1_FLL_ENA 0x0040
99 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
101 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
103 #define WM8900_REG_POWER3_DACL_ENA 0x0002
104 #define WM8900_REG_POWER3_DACR_ENA 0x0001
106 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
112 #define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
113 #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
115 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118 #define WM8900_REG_DACCTRL_MUTE 0x004
119 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
120 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
122 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
124 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
126 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
128 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
130 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
131 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
132 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
133 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
134 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
135 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
137 #define WM8900_LRC_MASK 0x03ff
140 enum snd_soc_control_type control_type;
142 u32 fll_in; /* FLL input frequency */
143 u32 fll_out; /* FLL output frequency */
147 * wm8900 register cache. We can't read the entire register space and we
148 * have slow control buses so we cache the registers.
150 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
179 /* Remaining registers all zero */
182 static int wm8900_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
192 static void wm8900_reset(struct snd_soc_codec *codec)
194 snd_soc_write(codec, WM8900_REG_RESET, 0);
196 memcpy(codec->reg_cache, wm8900_reg_defaults,
197 sizeof(wm8900_reg_defaults));
200 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
201 struct snd_kcontrol *kcontrol, int event)
203 struct snd_soc_codec *codec = w->codec;
204 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
207 case SND_SOC_DAPM_PRE_PMU:
208 /* Clamp headphone outputs */
209 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
210 WM8900_REG_HPCTL1_HP_CLAMP_OP;
211 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
214 case SND_SOC_DAPM_POST_PMU:
215 /* Enable the input stage */
216 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
217 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
218 WM8900_REG_HPCTL1_HP_SHORT2 |
219 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
220 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
224 /* Enable the output stage */
225 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
226 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
227 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
229 /* Remove the shorts */
230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
231 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
232 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
233 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
236 case SND_SOC_DAPM_PRE_PMD:
237 /* Short the output */
238 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
239 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
241 /* Disable the output stage */
242 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
243 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
245 /* Clamp the outputs and power down input */
246 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
247 WM8900_REG_HPCTL1_HP_CLAMP_OP;
248 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
249 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
252 case SND_SOC_DAPM_POST_PMD:
253 /* Disable everything */
254 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
264 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
266 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
268 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
270 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
272 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
274 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
276 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
278 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
280 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
282 static const struct soc_enum mic_bias_level =
283 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
285 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
287 static const struct soc_enum dac_mute_rate =
288 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
290 static const char *dac_deemphasis_txt[] = {
291 "Disabled", "32kHz", "44.1kHz", "48kHz"
294 static const struct soc_enum dac_deemphasis =
295 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
297 static const char *adc_hpf_cut_txt[] = {
298 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
301 static const struct soc_enum adc_hpf_cut =
302 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
304 static const char *lr_txt[] = {
308 static const struct soc_enum aifl_src =
309 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
311 static const struct soc_enum aifr_src =
312 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
314 static const struct soc_enum dacl_src =
315 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
317 static const struct soc_enum dacr_src =
318 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
320 static const char *sidetone_txt[] = {
321 "Disabled", "Left ADC", "Right ADC"
324 static const struct soc_enum dacl_sidetone =
325 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
327 static const struct soc_enum dacr_sidetone =
328 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
330 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
331 SOC_ENUM("Mic Bias Level", mic_bias_level),
333 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
335 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
336 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
338 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
340 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
341 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
343 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
344 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
345 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
346 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
347 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
350 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
351 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
352 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
353 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
355 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
357 SOC_ENUM("Left Digital Audio Source", aifl_src),
358 SOC_ENUM("Right Digital Audio Source", aifr_src),
360 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
362 SOC_ENUM("Left DAC Source", dacl_src),
363 SOC_ENUM("Right DAC Source", dacr_src),
364 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
365 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
366 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
368 SOC_DOUBLE_R_TLV("Digital Playback Volume",
369 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
371 SOC_DOUBLE_R_TLV("Digital Capture Volume",
372 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
374 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
376 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
378 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
380 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
383 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
385 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
387 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
389 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
392 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
394 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
396 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
398 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
400 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
402 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
405 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
406 0, 63, 0, out_pga_tlv),
407 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
409 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
412 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
413 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
414 0, 63, 0, out_pga_tlv),
415 SOC_DOUBLE_R("LINEOUT2 Switch",
416 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
417 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
418 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
419 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
424 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
425 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
427 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
428 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
430 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
431 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
432 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
433 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
434 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
435 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
438 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
439 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
440 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
441 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
442 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
443 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
446 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
447 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
448 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
449 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
450 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
453 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
454 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
455 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
456 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
457 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
460 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
461 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
462 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
463 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
466 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
467 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
468 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
469 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
472 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
474 static const struct soc_enum wm8900_lineout2_lp_mux =
475 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
477 static const struct snd_kcontrol_new wm8900_lineout2_lp =
478 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
480 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
482 /* Externally visible pins */
483 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
484 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
485 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
486 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
487 SND_SOC_DAPM_OUTPUT("HP_L"),
488 SND_SOC_DAPM_OUTPUT("HP_R"),
490 SND_SOC_DAPM_INPUT("RINPUT1"),
491 SND_SOC_DAPM_INPUT("LINPUT1"),
492 SND_SOC_DAPM_INPUT("RINPUT2"),
493 SND_SOC_DAPM_INPUT("LINPUT2"),
494 SND_SOC_DAPM_INPUT("RINPUT3"),
495 SND_SOC_DAPM_INPUT("LINPUT3"),
496 SND_SOC_DAPM_INPUT("AUX"),
498 SND_SOC_DAPM_VMID("VMID"),
501 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
502 wm8900_linpga_controls,
503 ARRAY_SIZE(wm8900_linpga_controls)),
504 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
505 wm8900_rinpga_controls,
506 ARRAY_SIZE(wm8900_rinpga_controls)),
508 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
509 wm8900_linmix_controls,
510 ARRAY_SIZE(wm8900_linmix_controls)),
511 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
512 wm8900_rinmix_controls,
513 ARRAY_SIZE(wm8900_rinmix_controls)),
515 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
517 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
518 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
521 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
522 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
524 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
526 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
527 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
529 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
532 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
533 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
534 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
536 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
537 wm8900_loutmix_controls,
538 ARRAY_SIZE(wm8900_loutmix_controls)),
539 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
540 wm8900_routmix_controls,
541 ARRAY_SIZE(wm8900_routmix_controls)),
544 /* Target, Path, Source */
545 static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
547 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
548 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
549 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
551 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
552 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
553 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
555 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
556 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
557 {"Left Input Mixer", "AUX Switch", "AUX"},
558 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
560 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
561 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
562 {"Right Input Mixer", "AUX Switch", "AUX"},
563 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
565 {"ADCL", NULL, "Left Input Mixer"},
566 {"ADCR", NULL, "Right Input Mixer"},
569 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
570 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
571 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
572 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
574 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
575 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
576 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
577 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
579 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
580 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
581 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
582 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
584 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
585 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
586 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
587 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
588 {"Left Output Mixer", "DACL Switch", "DACL"},
590 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
591 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
592 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
593 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
594 {"Right Output Mixer", "DACR Switch", "DACR"},
596 /* Note that the headphone output stage needs to be connected
597 * externally to LINEOUT2 via DC blocking capacitors. Other
598 * configurations are not supported.
600 * Note also that left and right headphone paths are treated as a
603 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
604 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
605 {"HP_L", NULL, "Headphone Amplifier"},
606 {"HP_R", NULL, "Headphone Amplifier"},
609 static int wm8900_hw_params(struct snd_pcm_substream *substream,
610 struct snd_pcm_hw_params *params,
611 struct snd_soc_dai *dai)
613 struct snd_soc_pcm_runtime *rtd = substream->private_data;
614 struct snd_soc_codec *codec = rtd->codec;
617 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
619 switch (params_format(params)) {
620 case SNDRV_PCM_FORMAT_S16_LE:
622 case SNDRV_PCM_FORMAT_S20_3LE:
625 case SNDRV_PCM_FORMAT_S24_LE:
628 case SNDRV_PCM_FORMAT_S32_LE:
635 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
637 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
638 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
640 if (params_rate(params) <= 24000)
641 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
643 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
645 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
655 u16 fll_slow_lock_ref;
660 /* The size in bits of the FLL divide multiplied by 10
661 * to allow rounding later */
662 #define FIXED_FLL_SIZE ((1 << 16) * 10)
664 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
668 unsigned int K, Ndiv, Nmod, target;
673 /* The FLL must run at 90-100MHz which is then scaled down to
674 * the output value by FLLCLK_DIV. */
677 while (target < 90000000) {
682 if (target > 100000000)
683 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
684 " Fout=%u\n", target, Fref, Fout);
686 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
687 "Fref=%u, Fout=%u, target=%u\n",
688 div, Fref, Fout, target);
692 fll_div->fllclk_div = div >> 2;
695 fll_div->fll_slow_lock_ref = 1;
697 fll_div->fll_slow_lock_ref = 0;
699 Ndiv = target / Fref;
702 fll_div->fll_ratio = 8;
704 fll_div->fll_ratio = 1;
706 fll_div->n = Ndiv / fll_div->fll_ratio;
707 Nmod = (target / fll_div->fll_ratio) % Fref;
709 /* Calculate fractional part - scale up so we can round. */
710 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
714 K = Kpart & 0xFFFFFFFF;
719 /* Move down to proper range now rounding is done */
722 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
723 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
728 static int wm8900_set_fll(struct snd_soc_codec *codec,
729 int fll_id, unsigned int freq_in, unsigned int freq_out)
731 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
732 struct _fll_div fll_div;
734 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
737 /* The digital side should be disabled during any change. */
738 snd_soc_update_bits(codec, WM8900_REG_POWER1,
739 WM8900_REG_POWER1_FLL_ENA, 0);
741 /* Disable the FLL? */
742 if (!freq_in || !freq_out) {
743 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
744 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
745 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
746 WM8900_REG_FLLCTL1_OSC_ENA, 0);
747 wm8900->fll_in = freq_in;
748 wm8900->fll_out = freq_out;
753 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
756 wm8900->fll_in = freq_in;
757 wm8900->fll_out = freq_out;
759 /* The osclilator *MUST* be enabled before we enable the
760 * digital circuit. */
761 snd_soc_write(codec, WM8900_REG_FLLCTL1,
762 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
764 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
765 snd_soc_write(codec, WM8900_REG_FLLCTL5,
766 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
769 snd_soc_write(codec, WM8900_REG_FLLCTL2,
770 (fll_div.k >> 8) | 0x100);
771 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
773 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
775 if (fll_div.fll_slow_lock_ref)
776 snd_soc_write(codec, WM8900_REG_FLLCTL6,
777 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
779 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
781 snd_soc_update_bits(codec, WM8900_REG_POWER1,
782 WM8900_REG_POWER1_FLL_ENA,
783 WM8900_REG_POWER1_FLL_ENA);
786 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
787 WM8900_REG_CLOCKING1_MCLK_SRC,
788 WM8900_REG_CLOCKING1_MCLK_SRC);
792 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
793 int source, unsigned int freq_in, unsigned int freq_out)
795 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
798 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
801 struct snd_soc_codec *codec = codec_dai->codec;
804 case WM8900_BCLK_DIV:
805 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
806 WM8900_REG_CLOCKING1_BCLK_MASK, div);
808 case WM8900_OPCLK_DIV:
809 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
810 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
812 case WM8900_DAC_LRCLK:
813 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
814 WM8900_LRC_MASK, div);
816 case WM8900_ADC_LRCLK:
817 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
818 WM8900_LRC_MASK, div);
820 case WM8900_DAC_CLKDIV:
821 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
822 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
824 case WM8900_ADC_CLKDIV:
825 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
826 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
828 case WM8900_LRCLK_MODE:
829 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
830 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
840 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
843 struct snd_soc_codec *codec = codec_dai->codec;
844 unsigned int clocking1, aif1, aif3, aif4;
846 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
847 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
848 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
849 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
851 /* set master/slave audio interface */
852 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
853 case SND_SOC_DAIFMT_CBS_CFS:
854 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
855 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
856 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
858 case SND_SOC_DAIFMT_CBS_CFM:
859 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
860 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
861 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
863 case SND_SOC_DAIFMT_CBM_CFM:
864 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
865 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
866 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
868 case SND_SOC_DAIFMT_CBM_CFS:
869 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
870 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
871 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
877 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
878 case SND_SOC_DAIFMT_DSP_A:
879 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
880 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
882 case SND_SOC_DAIFMT_DSP_B:
883 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
884 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
886 case SND_SOC_DAIFMT_I2S:
887 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
890 case SND_SOC_DAIFMT_RIGHT_J:
891 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
893 case SND_SOC_DAIFMT_LEFT_J:
894 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
901 /* Clock inversion */
902 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
903 case SND_SOC_DAIFMT_DSP_A:
904 case SND_SOC_DAIFMT_DSP_B:
905 /* frame inversion not valid for DSP modes */
906 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
907 case SND_SOC_DAIFMT_NB_NF:
908 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
910 case SND_SOC_DAIFMT_IB_NF:
911 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
917 case SND_SOC_DAIFMT_I2S:
918 case SND_SOC_DAIFMT_RIGHT_J:
919 case SND_SOC_DAIFMT_LEFT_J:
920 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
921 case SND_SOC_DAIFMT_NB_NF:
922 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
923 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
925 case SND_SOC_DAIFMT_IB_IF:
926 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
927 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
929 case SND_SOC_DAIFMT_IB_NF:
930 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
931 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
933 case SND_SOC_DAIFMT_NB_IF:
934 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
935 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
945 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
946 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
947 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
948 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
953 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
955 struct snd_soc_codec *codec = codec_dai->codec;
958 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
961 reg |= WM8900_REG_DACCTRL_MUTE;
963 reg &= ~WM8900_REG_DACCTRL_MUTE;
965 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
970 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
971 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
972 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
974 #define WM8900_PCM_FORMATS \
975 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
976 SNDRV_PCM_FORMAT_S24_LE)
978 static const struct snd_soc_dai_ops wm8900_dai_ops = {
979 .hw_params = wm8900_hw_params,
980 .set_clkdiv = wm8900_set_dai_clkdiv,
981 .set_pll = wm8900_set_dai_pll,
982 .set_fmt = wm8900_set_dai_fmt,
983 .digital_mute = wm8900_digital_mute,
986 static struct snd_soc_dai_driver wm8900_dai = {
987 .name = "wm8900-hifi",
989 .stream_name = "HiFi Playback",
992 .rates = WM8900_RATES,
993 .formats = WM8900_PCM_FORMATS,
996 .stream_name = "HiFi Capture",
999 .rates = WM8900_RATES,
1000 .formats = WM8900_PCM_FORMATS,
1002 .ops = &wm8900_dai_ops,
1005 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1006 enum snd_soc_bias_level level)
1011 case SND_SOC_BIAS_ON:
1012 /* Enable thermal shutdown */
1013 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1014 WM8900_REG_GPIO_TEMP_ENA,
1015 WM8900_REG_GPIO_TEMP_ENA);
1016 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1017 WM8900_REG_ADDCTL_TEMP_SD,
1018 WM8900_REG_ADDCTL_TEMP_SD);
1021 case SND_SOC_BIAS_PREPARE:
1024 case SND_SOC_BIAS_STANDBY:
1025 /* Charge capacitors if initial power up */
1026 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1027 /* STARTUP_BIAS_ENA on */
1028 snd_soc_write(codec, WM8900_REG_POWER1,
1029 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1031 /* Startup bias mode */
1032 snd_soc_write(codec, WM8900_REG_ADDCTL,
1033 WM8900_REG_ADDCTL_BIAS_SRC |
1034 WM8900_REG_ADDCTL_VMID_SOFTST);
1037 snd_soc_write(codec, WM8900_REG_POWER1,
1038 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1040 /* Allow capacitors to charge */
1041 schedule_timeout_interruptible(msecs_to_jiffies(400));
1044 snd_soc_write(codec, WM8900_REG_POWER1,
1045 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1046 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1048 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1050 snd_soc_write(codec, WM8900_REG_POWER1,
1051 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1054 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1055 snd_soc_write(codec, WM8900_REG_POWER1,
1056 (reg & WM8900_REG_POWER1_FLL_ENA) |
1057 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1058 snd_soc_write(codec, WM8900_REG_POWER2,
1059 WM8900_REG_POWER2_SYSCLK_ENA);
1060 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1063 case SND_SOC_BIAS_OFF:
1064 /* Startup bias enable */
1065 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1066 snd_soc_write(codec, WM8900_REG_POWER1,
1067 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1068 snd_soc_write(codec, WM8900_REG_ADDCTL,
1069 WM8900_REG_ADDCTL_BIAS_SRC |
1070 WM8900_REG_ADDCTL_VMID_SOFTST);
1072 /* Discharge caps */
1073 snd_soc_write(codec, WM8900_REG_POWER1,
1074 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1075 schedule_timeout_interruptible(msecs_to_jiffies(500));
1078 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1081 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1082 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1083 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1084 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1086 /* Need to let things settle before stopping the clock
1087 * to ensure that restart works, see "Stopping the
1088 * master clock" in the datasheet. */
1089 schedule_timeout_interruptible(msecs_to_jiffies(1));
1090 snd_soc_write(codec, WM8900_REG_POWER2,
1091 WM8900_REG_POWER2_SYSCLK_ENA);
1094 codec->dapm.bias_level = level;
1098 static int wm8900_suspend(struct snd_soc_codec *codec)
1100 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1101 int fll_out = wm8900->fll_out;
1102 int fll_in = wm8900->fll_in;
1105 /* Stop the FLL in an orderly fashion */
1106 ret = wm8900_set_fll(codec, 0, 0, 0);
1108 dev_err(codec->dev, "Failed to stop FLL\n");
1112 wm8900->fll_out = fll_out;
1113 wm8900->fll_in = fll_in;
1115 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1120 static int wm8900_resume(struct snd_soc_codec *codec)
1122 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1126 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1129 wm8900_reset(codec);
1130 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1132 /* Restart the FLL? */
1133 if (wm8900->fll_out) {
1134 int fll_out = wm8900->fll_out;
1135 int fll_in = wm8900->fll_in;
1138 wm8900->fll_out = 0;
1140 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1142 dev_err(codec->dev, "Failed to restart FLL\n");
1149 for (i = 0; i < WM8900_MAXREG; i++)
1150 snd_soc_write(codec, i, cache[i]);
1153 dev_err(codec->dev, "Unable to allocate register cache\n");
1158 static int wm8900_probe(struct snd_soc_codec *codec)
1160 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1163 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
1165 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1169 reg = snd_soc_read(codec, WM8900_REG_ID);
1170 if (reg != 0x8900) {
1171 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1175 wm8900_reset(codec);
1177 /* Turn the chip on */
1178 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1180 /* Latch the volume update bits */
1181 snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1182 snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1183 snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1184 snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1185 snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1186 snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1187 snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1188 snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1189 snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1190 snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
1192 /* Set the DAC and mixer output bias */
1193 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1198 /* power down chip */
1199 static int wm8900_remove(struct snd_soc_codec *codec)
1201 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1205 static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1206 .probe = wm8900_probe,
1207 .remove = wm8900_remove,
1208 .suspend = wm8900_suspend,
1209 .resume = wm8900_resume,
1210 .set_bias_level = wm8900_set_bias_level,
1211 .volatile_register = wm8900_volatile_register,
1212 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
1213 .reg_word_size = sizeof(u16),
1214 .reg_cache_default = wm8900_reg_defaults,
1216 .controls = wm8900_snd_controls,
1217 .num_controls = ARRAY_SIZE(wm8900_snd_controls),
1218 .dapm_widgets = wm8900_dapm_widgets,
1219 .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
1220 .dapm_routes = wm8900_dapm_routes,
1221 .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
1224 #if defined(CONFIG_SPI_MASTER)
1225 static int __devinit wm8900_spi_probe(struct spi_device *spi)
1227 struct wm8900_priv *wm8900;
1230 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1234 wm8900->control_type = SND_SOC_SPI;
1235 spi_set_drvdata(spi, wm8900);
1237 ret = snd_soc_register_codec(&spi->dev,
1238 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1244 static int __devexit wm8900_spi_remove(struct spi_device *spi)
1246 snd_soc_unregister_codec(&spi->dev);
1247 kfree(spi_get_drvdata(spi));
1251 static struct spi_driver wm8900_spi_driver = {
1254 .owner = THIS_MODULE,
1256 .probe = wm8900_spi_probe,
1257 .remove = __devexit_p(wm8900_spi_remove),
1259 #endif /* CONFIG_SPI_MASTER */
1261 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1262 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1263 const struct i2c_device_id *id)
1265 struct wm8900_priv *wm8900;
1268 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1272 i2c_set_clientdata(i2c, wm8900);
1273 wm8900->control_type = SND_SOC_I2C;
1275 ret = snd_soc_register_codec(&i2c->dev,
1276 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1282 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1284 snd_soc_unregister_codec(&client->dev);
1285 kfree(i2c_get_clientdata(client));
1289 static const struct i2c_device_id wm8900_i2c_id[] = {
1293 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1295 static struct i2c_driver wm8900_i2c_driver = {
1298 .owner = THIS_MODULE,
1300 .probe = wm8900_i2c_probe,
1301 .remove = __devexit_p(wm8900_i2c_remove),
1302 .id_table = wm8900_i2c_id,
1306 static int __init wm8900_modinit(void)
1309 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1310 ret = i2c_add_driver(&wm8900_i2c_driver);
1312 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1316 #if defined(CONFIG_SPI_MASTER)
1317 ret = spi_register_driver(&wm8900_spi_driver);
1319 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1325 module_init(wm8900_modinit);
1327 static void __exit wm8900_exit(void)
1329 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1330 i2c_del_driver(&wm8900_i2c_driver);
1332 #if defined(CONFIG_SPI_MASTER)
1333 spi_unregister_driver(&wm8900_spi_driver);
1336 module_exit(wm8900_exit);
1338 MODULE_DESCRIPTION("ASoC WM8900 driver");
1339 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1340 MODULE_LICENSE("GPL");