2 * wm8903.c -- WM8903 ALSA SoC Audio driver
4 * Copyright 2008 Wolfson Microelectronics
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - TDM mode configuration.
14 * - Digital microphone support.
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/init.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
23 #include <linux/i2c.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/jack.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/tlv.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/wm8903.h>
38 /* Register defaults at reset */
39 static u16 wm8903_reg_defaults[] = {
40 0x8903, /* R0 - SW Reset and ID */
41 0x0000, /* R1 - Revision Number */
44 0x0018, /* R4 - Bias Control 0 */
45 0x0000, /* R5 - VMID Control 0 */
46 0x0000, /* R6 - Mic Bias Control 0 */
48 0x0001, /* R8 - Analogue DAC 0 */
50 0x0001, /* R10 - Analogue ADC 0 */
52 0x0000, /* R12 - Power Management 0 */
53 0x0000, /* R13 - Power Management 1 */
54 0x0000, /* R14 - Power Management 2 */
55 0x0000, /* R15 - Power Management 3 */
56 0x0000, /* R16 - Power Management 4 */
57 0x0000, /* R17 - Power Management 5 */
58 0x0000, /* R18 - Power Management 6 */
60 0x0400, /* R20 - Clock Rates 0 */
61 0x0D07, /* R21 - Clock Rates 1 */
62 0x0000, /* R22 - Clock Rates 2 */
64 0x0050, /* R24 - Audio Interface 0 */
65 0x0242, /* R25 - Audio Interface 1 */
66 0x0008, /* R26 - Audio Interface 2 */
67 0x0022, /* R27 - Audio Interface 3 */
70 0x00C0, /* R30 - DAC Digital Volume Left */
71 0x00C0, /* R31 - DAC Digital Volume Right */
72 0x0000, /* R32 - DAC Digital 0 */
73 0x0000, /* R33 - DAC Digital 1 */
76 0x00C0, /* R36 - ADC Digital Volume Left */
77 0x00C0, /* R37 - ADC Digital Volume Right */
78 0x0000, /* R38 - ADC Digital 0 */
79 0x0073, /* R39 - Digital Microphone 0 */
80 0x09BF, /* R40 - DRC 0 */
81 0x3241, /* R41 - DRC 1 */
82 0x0020, /* R42 - DRC 2 */
83 0x0000, /* R43 - DRC 3 */
84 0x0085, /* R44 - Analogue Left Input 0 */
85 0x0085, /* R45 - Analogue Right Input 0 */
86 0x0044, /* R46 - Analogue Left Input 1 */
87 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0008, /* R50 - Analogue Left Mix 0 */
91 0x0004, /* R51 - Analogue Right Mix 0 */
92 0x0000, /* R52 - Analogue Spk Mix Left 0 */
93 0x0000, /* R53 - Analogue Spk Mix Left 1 */
94 0x0000, /* R54 - Analogue Spk Mix Right 0 */
95 0x0000, /* R55 - Analogue Spk Mix Right 1 */
97 0x002D, /* R57 - Analogue OUT1 Left */
98 0x002D, /* R58 - Analogue OUT1 Right */
99 0x0039, /* R59 - Analogue OUT2 Left */
100 0x0039, /* R60 - Analogue OUT2 Right */
102 0x0139, /* R62 - Analogue OUT3 Left */
103 0x0139, /* R63 - Analogue OUT3 Right */
105 0x0000, /* R65 - Analogue SPK Output Control 0 */
107 0x0010, /* R67 - DC Servo 0 */
109 0x00A4, /* R69 - DC Servo 2 */
130 0x0000, /* R90 - Analogue HP 0 */
134 0x0000, /* R94 - Analogue Lineout 0 */
138 0x0000, /* R98 - Charge Pump 0 */
144 0x0000, /* R104 - Class W 0 */
148 0x0000, /* R108 - Write Sequencer 0 */
149 0x0000, /* R109 - Write Sequencer 1 */
150 0x0000, /* R110 - Write Sequencer 2 */
151 0x0000, /* R111 - Write Sequencer 3 */
152 0x0000, /* R112 - Write Sequencer 4 */
154 0x0000, /* R114 - Control Interface */
156 0x00A8, /* R116 - GPIO Control 1 */
157 0x00A8, /* R117 - GPIO Control 2 */
158 0x00A8, /* R118 - GPIO Control 3 */
159 0x0220, /* R119 - GPIO Control 4 */
160 0x01A0, /* R120 - GPIO Control 5 */
161 0x0000, /* R121 - Interrupt Status 1 */
162 0xFFFF, /* R122 - Interrupt Status 1 Mask */
163 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R129 - Control Interface Test 1 */
189 0x6810, /* R149 - Charge Pump Test 1 */
204 0x0028, /* R164 - Clock Rate Test 4 */
212 0x0000, /* R172 - Analogue Output Bias 0 */
216 struct snd_soc_codec codec;
217 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
221 /* Reference counts */
226 struct completion wseq;
228 struct snd_soc_jack *mic_jack;
234 struct snd_pcm_substream *master_substream;
235 struct snd_pcm_substream *slave_substream;
238 static int wm8903_volatile_register(unsigned int reg)
241 case WM8903_SW_RESET_AND_ID:
242 case WM8903_REVISION_NUMBER:
243 case WM8903_INTERRUPT_STATUS_1:
244 case WM8903_WRITE_SEQUENCER_4:
252 static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
255 struct i2c_client *i2c = codec->control_data;
256 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
260 /* Enable the sequencer if it's not already on */
261 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
262 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
263 reg[0] | WM8903_WSEQ_ENA);
265 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
267 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
268 start | WM8903_WSEQ_START);
270 /* Wait for it to complete. If we have the interrupt wired up then
271 * that will break us out of the poll early.
274 wait_for_completion_timeout(&wm8903->wseq,
275 msecs_to_jiffies(10));
277 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
278 } while (reg[4] & WM8903_WSEQ_BUSY);
280 dev_dbg(&i2c->dev, "Sequence complete\n");
282 /* Disable the sequencer again if we enabled it */
283 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
288 static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
292 /* There really ought to be something better we can do here :/ */
293 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
294 cache[i] = codec->hw_read(codec, i);
297 static void wm8903_reset(struct snd_soc_codec *codec)
299 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
300 memcpy(codec->reg_cache, wm8903_reg_defaults,
301 sizeof(wm8903_reg_defaults));
304 #define WM8903_OUTPUT_SHORT 0x8
305 #define WM8903_OUTPUT_OUT 0x4
306 #define WM8903_OUTPUT_INT 0x2
307 #define WM8903_OUTPUT_IN 0x1
309 static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
310 struct snd_kcontrol *kcontrol, int event)
312 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
319 * Event for headphone and line out amplifier power changes. Special
320 * power up/down sequences are required in order to maximise pop/click
323 static int wm8903_output_event(struct snd_soc_dapm_widget *w,
324 struct snd_kcontrol *kcontrol, int event)
326 struct snd_soc_codec *codec = w->codec;
334 case WM8903_POWER_MANAGEMENT_2:
335 reg = WM8903_ANALOGUE_HP_0;
336 dcs_bit = 0 + w->shift;
338 case WM8903_POWER_MANAGEMENT_3:
339 reg = WM8903_ANALOGUE_LINEOUT_0;
340 dcs_bit = 2 + w->shift;
344 return -EINVAL; /* Spurious warning from some compilers */
356 return -EINVAL; /* Spurious warning from some compilers */
359 if (event & SND_SOC_DAPM_PRE_PMU) {
360 val = snd_soc_read(codec, reg);
362 /* Short the output */
363 val &= ~(WM8903_OUTPUT_SHORT << shift);
364 snd_soc_write(codec, reg, val);
367 if (event & SND_SOC_DAPM_POST_PMU) {
368 val = snd_soc_read(codec, reg);
370 val |= (WM8903_OUTPUT_IN << shift);
371 snd_soc_write(codec, reg, val);
373 val |= (WM8903_OUTPUT_INT << shift);
374 snd_soc_write(codec, reg, val);
376 /* Turn on the output ENA_OUTP */
377 val |= (WM8903_OUTPUT_OUT << shift);
378 snd_soc_write(codec, reg, val);
380 /* Enable the DC servo */
381 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
383 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
385 /* Remove the short */
386 val |= (WM8903_OUTPUT_SHORT << shift);
387 snd_soc_write(codec, reg, val);
390 if (event & SND_SOC_DAPM_PRE_PMD) {
391 val = snd_soc_read(codec, reg);
393 /* Short the output */
394 val &= ~(WM8903_OUTPUT_SHORT << shift);
395 snd_soc_write(codec, reg, val);
397 /* Disable the DC servo */
398 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
400 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
402 /* Then disable the intermediate and output stages */
403 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
404 WM8903_OUTPUT_IN) << shift);
405 snd_soc_write(codec, reg, val);
412 * When used with DAC outputs only the WM8903 charge pump supports
413 * operation in class W mode, providing very low power consumption
414 * when used with digital sources. Enable and disable this mode
415 * automatically depending on the mixer configuration.
417 * All the relevant controls are simple switches.
419 static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
422 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
423 struct snd_soc_codec *codec = widget->codec;
424 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
425 struct i2c_client *i2c = codec->control_data;
429 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
431 /* Turn it off if we're about to enable bypass */
432 if (ucontrol->value.integer.value[0]) {
433 if (wm8903->class_w_users == 0) {
434 dev_dbg(&i2c->dev, "Disabling Class W\n");
435 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
436 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
438 wm8903->class_w_users++;
441 /* Implement the change */
442 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
444 /* If we've just disabled the last bypass path turn Class W on */
445 if (!ucontrol->value.integer.value[0]) {
446 if (wm8903->class_w_users == 1) {
447 dev_dbg(&i2c->dev, "Enabling Class W\n");
448 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
449 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
451 wm8903->class_w_users--;
454 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
455 wm8903->class_w_users);
460 #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
461 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
462 .info = snd_soc_info_volsw, \
463 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
464 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
467 /* ALSA can only do steps of .01dB */
468 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
470 static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
471 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
473 static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
474 static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
475 static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
476 static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
477 static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
479 static const char *drc_slope_text[] = {
480 "1", "1/2", "1/4", "1/8", "1/16", "0"
483 static const struct soc_enum drc_slope_r0 =
484 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
486 static const struct soc_enum drc_slope_r1 =
487 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
489 static const char *drc_attack_text[] = {
491 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
492 "46.4ms", "92.8ms", "185.6ms"
495 static const struct soc_enum drc_attack =
496 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
498 static const char *drc_decay_text[] = {
499 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
503 static const struct soc_enum drc_decay =
504 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
506 static const char *drc_ff_delay_text[] = {
507 "5 samples", "9 samples"
510 static const struct soc_enum drc_ff_delay =
511 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
513 static const char *drc_qr_decay_text[] = {
514 "0.725ms", "1.45ms", "5.8ms"
517 static const struct soc_enum drc_qr_decay =
518 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
520 static const char *drc_smoothing_text[] = {
521 "Low", "Medium", "High"
524 static const struct soc_enum drc_smoothing =
525 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
527 static const char *soft_mute_text[] = {
528 "Fast (fs/2)", "Slow (fs/32)"
531 static const struct soc_enum soft_mute =
532 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
534 static const char *mute_mode_text[] = {
538 static const struct soc_enum mute_mode =
539 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
541 static const char *dac_deemphasis_text[] = {
542 "Disabled", "32kHz", "44.1kHz", "48kHz"
545 static const struct soc_enum dac_deemphasis =
546 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
548 static const char *companding_text[] = {
552 static const struct soc_enum dac_companding =
553 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
555 static const struct soc_enum adc_companding =
556 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
558 static const char *input_mode_text[] = {
559 "Single-Ended", "Differential Line", "Differential Mic"
562 static const struct soc_enum linput_mode_enum =
563 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
565 static const struct soc_enum rinput_mode_enum =
566 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
568 static const char *linput_mux_text[] = {
569 "IN1L", "IN2L", "IN3L"
572 static const struct soc_enum linput_enum =
573 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
575 static const struct soc_enum linput_inv_enum =
576 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
578 static const char *rinput_mux_text[] = {
579 "IN1R", "IN2R", "IN3R"
582 static const struct soc_enum rinput_enum =
583 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
585 static const struct soc_enum rinput_inv_enum =
586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
589 static const char *sidetone_text[] = {
590 "None", "Left", "Right"
593 static const struct soc_enum lsidetone_enum =
594 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
596 static const struct soc_enum rsidetone_enum =
597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
599 static const struct snd_kcontrol_new wm8903_snd_controls[] = {
601 /* Input PGAs - No TLV since the scale depends on PGA mode */
602 SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
604 SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
606 SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
609 SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
611 SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
613 SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
617 SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
618 SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
619 SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
620 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
622 SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
623 SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
624 SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
625 SOC_ENUM("DRC Attack Rate", drc_attack),
626 SOC_ENUM("DRC Decay Rate", drc_decay),
627 SOC_ENUM("DRC FF Delay", drc_ff_delay),
628 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
629 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
630 SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
631 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
632 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
633 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
634 SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
635 SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
637 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
638 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
639 SOC_ENUM("ADC Companding Mode", adc_companding),
640 SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
642 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
643 12, 0, digital_sidetone_tlv),
646 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
647 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
648 SOC_ENUM("DAC Soft Mute Rate", soft_mute),
649 SOC_ENUM("DAC Mute Mode", mute_mode),
650 SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
651 SOC_ENUM("DAC De-emphasis", dac_deemphasis),
652 SOC_ENUM("DAC Companding Mode", dac_companding),
653 SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
656 SOC_DOUBLE_R("Headphone Switch",
657 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
659 SOC_DOUBLE_R("Headphone ZC Switch",
660 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
662 SOC_DOUBLE_R_TLV("Headphone Volume",
663 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
667 SOC_DOUBLE_R("Line Out Switch",
668 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
670 SOC_DOUBLE_R("Line Out ZC Switch",
671 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
673 SOC_DOUBLE_R_TLV("Line Out Volume",
674 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
678 SOC_DOUBLE_R("Speaker Switch",
679 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
680 SOC_DOUBLE_R("Speaker ZC Switch",
681 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
682 SOC_DOUBLE_R_TLV("Speaker Volume",
683 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
687 static const struct snd_kcontrol_new linput_mode_mux =
688 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
690 static const struct snd_kcontrol_new rinput_mode_mux =
691 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
693 static const struct snd_kcontrol_new linput_mux =
694 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
696 static const struct snd_kcontrol_new linput_inv_mux =
697 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
699 static const struct snd_kcontrol_new rinput_mux =
700 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
702 static const struct snd_kcontrol_new rinput_inv_mux =
703 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
705 static const struct snd_kcontrol_new lsidetone_mux =
706 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
708 static const struct snd_kcontrol_new rsidetone_mux =
709 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
711 static const struct snd_kcontrol_new left_output_mixer[] = {
712 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
713 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
714 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
715 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
718 static const struct snd_kcontrol_new right_output_mixer[] = {
719 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
720 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
721 SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
722 SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
725 static const struct snd_kcontrol_new left_speaker_mixer[] = {
726 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
727 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
728 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
729 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
733 static const struct snd_kcontrol_new right_speaker_mixer[] = {
734 SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
735 SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
736 SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
738 SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
742 static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
743 SND_SOC_DAPM_INPUT("IN1L"),
744 SND_SOC_DAPM_INPUT("IN1R"),
745 SND_SOC_DAPM_INPUT("IN2L"),
746 SND_SOC_DAPM_INPUT("IN2R"),
747 SND_SOC_DAPM_INPUT("IN3L"),
748 SND_SOC_DAPM_INPUT("IN3R"),
750 SND_SOC_DAPM_OUTPUT("HPOUTL"),
751 SND_SOC_DAPM_OUTPUT("HPOUTR"),
752 SND_SOC_DAPM_OUTPUT("LINEOUTL"),
753 SND_SOC_DAPM_OUTPUT("LINEOUTR"),
754 SND_SOC_DAPM_OUTPUT("LOP"),
755 SND_SOC_DAPM_OUTPUT("LON"),
756 SND_SOC_DAPM_OUTPUT("ROP"),
757 SND_SOC_DAPM_OUTPUT("RON"),
759 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
761 SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
762 SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
764 SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
766 SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
767 SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
769 SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
771 SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
772 SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
774 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
775 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
777 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
778 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
780 SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
781 SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
783 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
784 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
785 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
786 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
788 SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
789 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
790 SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
791 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
793 SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
794 1, 0, NULL, 0, wm8903_output_event,
795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
796 SND_SOC_DAPM_PRE_PMD),
797 SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
798 0, 0, NULL, 0, wm8903_output_event,
799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
800 SND_SOC_DAPM_PRE_PMD),
802 SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
803 NULL, 0, wm8903_output_event,
804 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
805 SND_SOC_DAPM_PRE_PMD),
806 SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
807 NULL, 0, wm8903_output_event,
808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
809 SND_SOC_DAPM_PRE_PMD),
811 SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
813 SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
816 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
817 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
818 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
821 static const struct snd_soc_dapm_route intercon[] = {
823 { "Left Input Mux", "IN1L", "IN1L" },
824 { "Left Input Mux", "IN2L", "IN2L" },
825 { "Left Input Mux", "IN3L", "IN3L" },
827 { "Left Input Inverting Mux", "IN1L", "IN1L" },
828 { "Left Input Inverting Mux", "IN2L", "IN2L" },
829 { "Left Input Inverting Mux", "IN3L", "IN3L" },
831 { "Right Input Mux", "IN1R", "IN1R" },
832 { "Right Input Mux", "IN2R", "IN2R" },
833 { "Right Input Mux", "IN3R", "IN3R" },
835 { "Right Input Inverting Mux", "IN1R", "IN1R" },
836 { "Right Input Inverting Mux", "IN2R", "IN2R" },
837 { "Right Input Inverting Mux", "IN3R", "IN3R" },
839 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
840 { "Left Input Mode Mux", "Differential Line",
842 { "Left Input Mode Mux", "Differential Line",
843 "Left Input Inverting Mux" },
844 { "Left Input Mode Mux", "Differential Mic",
846 { "Left Input Mode Mux", "Differential Mic",
847 "Left Input Inverting Mux" },
849 { "Right Input Mode Mux", "Single-Ended",
850 "Right Input Inverting Mux" },
851 { "Right Input Mode Mux", "Differential Line",
853 { "Right Input Mode Mux", "Differential Line",
854 "Right Input Inverting Mux" },
855 { "Right Input Mode Mux", "Differential Mic",
857 { "Right Input Mode Mux", "Differential Mic",
858 "Right Input Inverting Mux" },
860 { "Left Input PGA", NULL, "Left Input Mode Mux" },
861 { "Right Input PGA", NULL, "Right Input Mode Mux" },
863 { "ADCL", NULL, "Left Input PGA" },
864 { "ADCL", NULL, "CLK_DSP" },
865 { "ADCR", NULL, "Right Input PGA" },
866 { "ADCR", NULL, "CLK_DSP" },
868 { "DACL Sidetone", "Left", "ADCL" },
869 { "DACL Sidetone", "Right", "ADCR" },
870 { "DACR Sidetone", "Left", "ADCL" },
871 { "DACR Sidetone", "Right", "ADCR" },
873 { "DACL", NULL, "DACL Sidetone" },
874 { "DACL", NULL, "CLK_DSP" },
875 { "DACR", NULL, "DACR Sidetone" },
876 { "DACR", NULL, "CLK_DSP" },
878 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
879 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
880 { "Left Output Mixer", "DACL Switch", "DACL" },
881 { "Left Output Mixer", "DACR Switch", "DACR" },
883 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
884 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
885 { "Right Output Mixer", "DACL Switch", "DACL" },
886 { "Right Output Mixer", "DACR Switch", "DACR" },
888 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
889 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
890 { "Left Speaker Mixer", "DACL Switch", "DACL" },
891 { "Left Speaker Mixer", "DACR Switch", "DACR" },
893 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
894 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
895 { "Right Speaker Mixer", "DACL Switch", "DACL" },
896 { "Right Speaker Mixer", "DACR Switch", "DACR" },
898 { "Left Line Output PGA", NULL, "Left Output Mixer" },
899 { "Right Line Output PGA", NULL, "Right Output Mixer" },
901 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
902 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
904 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
905 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
907 { "HPOUTL", NULL, "Left Headphone Output PGA" },
908 { "HPOUTR", NULL, "Right Headphone Output PGA" },
910 { "LINEOUTL", NULL, "Left Line Output PGA" },
911 { "LINEOUTR", NULL, "Right Line Output PGA" },
913 { "LOP", NULL, "Left Speaker PGA" },
914 { "LON", NULL, "Left Speaker PGA" },
916 { "ROP", NULL, "Right Speaker PGA" },
917 { "RON", NULL, "Right Speaker PGA" },
919 { "Left Headphone Output PGA", NULL, "Charge Pump" },
920 { "Right Headphone Output PGA", NULL, "Charge Pump" },
921 { "Left Line Output PGA", NULL, "Charge Pump" },
922 { "Right Line Output PGA", NULL, "Charge Pump" },
925 static int wm8903_add_widgets(struct snd_soc_codec *codec)
927 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
928 ARRAY_SIZE(wm8903_dapm_widgets));
930 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
935 static int wm8903_set_bias_level(struct snd_soc_codec *codec,
936 enum snd_soc_bias_level level)
938 struct i2c_client *i2c = codec->control_data;
942 case SND_SOC_BIAS_ON:
943 case SND_SOC_BIAS_PREPARE:
944 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
945 reg &= ~(WM8903_VMID_RES_MASK);
946 reg |= WM8903_VMID_RES_50K;
947 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
950 case SND_SOC_BIAS_STANDBY:
951 if (codec->bias_level == SND_SOC_BIAS_OFF) {
952 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
955 /* Change DC servo dither level in startup sequence */
956 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
957 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
958 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
960 wm8903_run_sequence(codec, 0);
961 wm8903_sync_reg_cache(codec, codec->reg_cache);
963 /* Enable low impedence charge pump output */
964 reg = snd_soc_read(codec,
965 WM8903_CONTROL_INTERFACE_TEST_1);
966 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
967 reg | WM8903_TEST_KEY);
968 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
969 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
970 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
971 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
974 /* By default no bypass paths are enabled so
975 * enable Class W support.
977 dev_dbg(&i2c->dev, "Enabling Class W\n");
978 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
979 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
982 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
983 reg &= ~(WM8903_VMID_RES_MASK);
984 reg |= WM8903_VMID_RES_250K;
985 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
988 case SND_SOC_BIAS_OFF:
989 wm8903_run_sequence(codec, 32);
990 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
991 reg &= ~WM8903_CLK_SYS_ENA;
992 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
996 codec->bias_level = level;
1001 static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1002 int clk_id, unsigned int freq, int dir)
1004 struct snd_soc_codec *codec = codec_dai->codec;
1005 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1007 wm8903->sysclk = freq;
1012 static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1015 struct snd_soc_codec *codec = codec_dai->codec;
1016 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1018 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1019 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1021 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1022 case SND_SOC_DAIFMT_CBS_CFS:
1024 case SND_SOC_DAIFMT_CBS_CFM:
1025 aif1 |= WM8903_LRCLK_DIR;
1027 case SND_SOC_DAIFMT_CBM_CFM:
1028 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1030 case SND_SOC_DAIFMT_CBM_CFS:
1031 aif1 |= WM8903_BCLK_DIR;
1037 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1038 case SND_SOC_DAIFMT_DSP_A:
1041 case SND_SOC_DAIFMT_DSP_B:
1042 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1044 case SND_SOC_DAIFMT_I2S:
1047 case SND_SOC_DAIFMT_RIGHT_J:
1050 case SND_SOC_DAIFMT_LEFT_J:
1056 /* Clock inversion */
1057 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1058 case SND_SOC_DAIFMT_DSP_A:
1059 case SND_SOC_DAIFMT_DSP_B:
1060 /* frame inversion not valid for DSP modes */
1061 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1062 case SND_SOC_DAIFMT_NB_NF:
1064 case SND_SOC_DAIFMT_IB_NF:
1065 aif1 |= WM8903_AIF_BCLK_INV;
1071 case SND_SOC_DAIFMT_I2S:
1072 case SND_SOC_DAIFMT_RIGHT_J:
1073 case SND_SOC_DAIFMT_LEFT_J:
1074 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1075 case SND_SOC_DAIFMT_NB_NF:
1077 case SND_SOC_DAIFMT_IB_IF:
1078 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1080 case SND_SOC_DAIFMT_IB_NF:
1081 aif1 |= WM8903_AIF_BCLK_INV;
1083 case SND_SOC_DAIFMT_NB_IF:
1084 aif1 |= WM8903_AIF_LRCLK_INV;
1094 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1099 static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1101 struct snd_soc_codec *codec = codec_dai->codec;
1104 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1107 reg |= WM8903_DAC_MUTE;
1109 reg &= ~WM8903_DAC_MUTE;
1111 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
1116 /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1117 * for optimal performance so we list the lower rates first and match
1118 * on the last match we find. */
1124 } clk_sys_ratios[] = {
1125 { 64, 0x0, 0x0, 1 },
1126 { 68, 0x0, 0x1, 1 },
1127 { 125, 0x0, 0x2, 1 },
1128 { 128, 0x1, 0x0, 1 },
1129 { 136, 0x1, 0x1, 1 },
1130 { 192, 0x2, 0x0, 1 },
1131 { 204, 0x2, 0x1, 1 },
1133 { 64, 0x0, 0x0, 2 },
1134 { 68, 0x0, 0x1, 2 },
1135 { 125, 0x0, 0x2, 2 },
1136 { 128, 0x1, 0x0, 2 },
1137 { 136, 0x1, 0x1, 2 },
1138 { 192, 0x2, 0x0, 2 },
1139 { 204, 0x2, 0x1, 2 },
1141 { 250, 0x2, 0x2, 1 },
1142 { 256, 0x3, 0x0, 1 },
1143 { 272, 0x3, 0x1, 1 },
1144 { 384, 0x4, 0x0, 1 },
1145 { 408, 0x4, 0x1, 1 },
1146 { 375, 0x4, 0x2, 1 },
1147 { 512, 0x5, 0x0, 1 },
1148 { 544, 0x5, 0x1, 1 },
1149 { 500, 0x5, 0x2, 1 },
1150 { 768, 0x6, 0x0, 1 },
1151 { 816, 0x6, 0x1, 1 },
1152 { 750, 0x6, 0x2, 1 },
1153 { 1024, 0x7, 0x0, 1 },
1154 { 1088, 0x7, 0x1, 1 },
1155 { 1000, 0x7, 0x2, 1 },
1156 { 1408, 0x8, 0x0, 1 },
1157 { 1496, 0x8, 0x1, 1 },
1158 { 1536, 0x9, 0x0, 1 },
1159 { 1632, 0x9, 0x1, 1 },
1160 { 1500, 0x9, 0x2, 1 },
1162 { 250, 0x2, 0x2, 2 },
1163 { 256, 0x3, 0x0, 2 },
1164 { 272, 0x3, 0x1, 2 },
1165 { 384, 0x4, 0x0, 2 },
1166 { 408, 0x4, 0x1, 2 },
1167 { 375, 0x4, 0x2, 2 },
1168 { 512, 0x5, 0x0, 2 },
1169 { 544, 0x5, 0x1, 2 },
1170 { 500, 0x5, 0x2, 2 },
1171 { 768, 0x6, 0x0, 2 },
1172 { 816, 0x6, 0x1, 2 },
1173 { 750, 0x6, 0x2, 2 },
1174 { 1024, 0x7, 0x0, 2 },
1175 { 1088, 0x7, 0x1, 2 },
1176 { 1000, 0x7, 0x2, 2 },
1177 { 1408, 0x8, 0x0, 2 },
1178 { 1496, 0x8, 0x1, 2 },
1179 { 1536, 0x9, 0x0, 2 },
1180 { 1632, 0x9, 0x1, 2 },
1181 { 1500, 0x9, 0x2, 2 },
1184 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1208 /* Sample rates for DSP */
1212 } sample_rates[] = {
1227 static int wm8903_startup(struct snd_pcm_substream *substream,
1228 struct snd_soc_dai *dai)
1230 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1231 struct snd_soc_device *socdev = rtd->socdev;
1232 struct snd_soc_codec *codec = socdev->card->codec;
1233 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1234 struct i2c_client *i2c = codec->control_data;
1235 struct snd_pcm_runtime *master_runtime;
1237 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1238 wm8903->playback_active++;
1240 wm8903->capture_active++;
1242 /* The DAI has shared clocks so if we already have a playback or
1243 * capture going then constrain this substream to match it.
1245 if (wm8903->master_substream) {
1246 master_runtime = wm8903->master_substream->runtime;
1248 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1249 master_runtime->sample_bits);
1251 snd_pcm_hw_constraint_minmax(substream->runtime,
1252 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1253 master_runtime->sample_bits,
1254 master_runtime->sample_bits);
1256 wm8903->slave_substream = substream;
1258 wm8903->master_substream = substream;
1263 static void wm8903_shutdown(struct snd_pcm_substream *substream,
1264 struct snd_soc_dai *dai)
1266 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1267 struct snd_soc_device *socdev = rtd->socdev;
1268 struct snd_soc_codec *codec = socdev->card->codec;
1269 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1271 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1272 wm8903->playback_active--;
1274 wm8903->capture_active--;
1276 if (wm8903->master_substream == substream)
1277 wm8903->master_substream = wm8903->slave_substream;
1279 wm8903->slave_substream = NULL;
1282 static int wm8903_hw_params(struct snd_pcm_substream *substream,
1283 struct snd_pcm_hw_params *params,
1284 struct snd_soc_dai *dai)
1286 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1287 struct snd_soc_device *socdev = rtd->socdev;
1288 struct snd_soc_codec *codec = socdev->card->codec;
1289 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1290 struct i2c_client *i2c = codec->control_data;
1291 int fs = params_rate(params);
1301 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1302 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1303 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1304 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1305 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1306 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1308 if (substream == wm8903->slave_substream) {
1309 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1313 /* Enable sloping stopband filter for low sample rates */
1315 dac_digital1 |= WM8903_DAC_SB_FILT;
1317 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1319 /* Configure sample rate logic for DSP - choose nearest rate */
1321 best_val = abs(sample_rates[dsp_config].rate - fs);
1322 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1323 cur_val = abs(sample_rates[i].rate - fs);
1324 if (cur_val <= best_val) {
1330 /* Constraints should stop us hitting this but let's make sure */
1331 if (wm8903->capture_active)
1332 switch (sample_rates[dsp_config].rate) {
1335 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1343 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1344 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1345 clock1 |= sample_rates[dsp_config].value;
1347 aif1 &= ~WM8903_AIF_WL_MASK;
1349 switch (params_format(params)) {
1350 case SNDRV_PCM_FORMAT_S16_LE:
1353 case SNDRV_PCM_FORMAT_S20_3LE:
1357 case SNDRV_PCM_FORMAT_S24_LE:
1361 case SNDRV_PCM_FORMAT_S32_LE:
1369 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1370 wm8903->sysclk, fs);
1372 /* We may not have an MCLK which allows us to generate exactly
1373 * the clock we want, particularly with USB derived inputs, so
1377 best_val = abs((wm8903->sysclk /
1378 (clk_sys_ratios[0].mclk_div *
1379 clk_sys_ratios[0].div)) - fs);
1380 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1381 cur_val = abs((wm8903->sysclk /
1382 (clk_sys_ratios[i].mclk_div *
1383 clk_sys_ratios[i].div)) - fs);
1385 if (cur_val <= best_val) {
1391 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1392 clock0 |= WM8903_MCLKDIV2;
1393 clk_sys = wm8903->sysclk / 2;
1395 clock0 &= ~WM8903_MCLKDIV2;
1396 clk_sys = wm8903->sysclk;
1399 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1400 WM8903_CLK_SYS_MODE_MASK);
1401 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1402 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1404 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1405 clk_sys_ratios[clk_config].rate,
1406 clk_sys_ratios[clk_config].mode,
1407 clk_sys_ratios[clk_config].div);
1409 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1411 /* We may not get quite the right frequency if using
1412 * approximate clocks so look for the closest match that is
1413 * higher than the target (we need to ensure that there enough
1414 * BCLKs to clock out the samples).
1417 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1419 while (i < ARRAY_SIZE(bclk_divs)) {
1420 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1421 if (cur_val < 0) /* BCLK table is sorted */
1428 aif2 &= ~WM8903_BCLK_DIV_MASK;
1429 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1431 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1432 bclk_divs[bclk_div].ratio / 10, bclk,
1433 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1435 aif2 |= bclk_divs[bclk_div].div;
1438 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1439 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1440 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1441 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1442 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1443 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
1449 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1451 * @codec: WM8903 codec
1452 * @jack: jack to report detection events on
1453 * @det: value to report for presence detection
1454 * @shrt: value to report for short detection
1456 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1457 * being used to bring out signals to the processor then only platform
1458 * data configuration is needed for WM8903 and processor GPIOs should
1459 * be configured using snd_soc_jack_add_gpios() instead.
1461 * The current threasholds for detection should be configured using
1462 * micdet_cfg in the platform data. Using this function will force on
1463 * the microphone bias for the device.
1465 int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1468 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1469 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
1471 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1474 /* Store the configuration */
1475 wm8903->mic_jack = jack;
1476 wm8903->mic_det = det;
1477 wm8903->mic_short = shrt;
1479 /* Enable interrupts we've got a report configured for */
1481 irq_mask &= ~WM8903_MICDET_EINT;
1483 irq_mask &= ~WM8903_MICSHRT_EINT;
1485 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1486 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1490 /* Enable mic detection, this may not have been set through
1491 * platform data (eg, if the defaults are OK). */
1492 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1493 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1494 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1495 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1497 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1498 WM8903_MICDET_ENA, 0);
1503 EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1505 static irqreturn_t wm8903_irq(int irq, void *data)
1507 struct wm8903_priv *wm8903 = data;
1508 struct snd_soc_codec *codec = &wm8903->codec;
1512 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
1514 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
1516 if (int_val & WM8903_WSEQ_BUSY_EINT) {
1517 dev_dbg(codec->dev, "Write sequencer done\n");
1518 complete(&wm8903->wseq);
1522 * The rest is microphone jack detection. We need to manually
1523 * invert the polarity of the interrupt after each event - to
1524 * simplify the code keep track of the last state we reported
1525 * and just invert the relevant bits in both the report and
1526 * the polarity register.
1528 mic_report = wm8903->mic_last_report;
1529 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1531 if (int_val & WM8903_MICSHRT_EINT) {
1532 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1534 mic_report ^= wm8903->mic_short;
1535 int_pol ^= WM8903_MICSHRT_INV;
1538 if (int_val & WM8903_MICDET_EINT) {
1539 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1541 mic_report ^= wm8903->mic_det;
1542 int_pol ^= WM8903_MICDET_INV;
1544 msleep(wm8903->mic_delay);
1547 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1548 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1550 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1551 wm8903->mic_short | wm8903->mic_det);
1553 wm8903->mic_last_report = mic_report;
1558 #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1559 SNDRV_PCM_RATE_11025 | \
1560 SNDRV_PCM_RATE_16000 | \
1561 SNDRV_PCM_RATE_22050 | \
1562 SNDRV_PCM_RATE_32000 | \
1563 SNDRV_PCM_RATE_44100 | \
1564 SNDRV_PCM_RATE_48000 | \
1565 SNDRV_PCM_RATE_88200 | \
1566 SNDRV_PCM_RATE_96000)
1568 #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1569 SNDRV_PCM_RATE_11025 | \
1570 SNDRV_PCM_RATE_16000 | \
1571 SNDRV_PCM_RATE_22050 | \
1572 SNDRV_PCM_RATE_32000 | \
1573 SNDRV_PCM_RATE_44100 | \
1574 SNDRV_PCM_RATE_48000)
1576 #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1577 SNDRV_PCM_FMTBIT_S20_3LE |\
1578 SNDRV_PCM_FMTBIT_S24_LE)
1580 static struct snd_soc_dai_ops wm8903_dai_ops = {
1581 .startup = wm8903_startup,
1582 .shutdown = wm8903_shutdown,
1583 .hw_params = wm8903_hw_params,
1584 .digital_mute = wm8903_digital_mute,
1585 .set_fmt = wm8903_set_dai_fmt,
1586 .set_sysclk = wm8903_set_dai_sysclk,
1589 struct snd_soc_dai wm8903_dai = {
1592 .stream_name = "Playback",
1595 .rates = WM8903_PLAYBACK_RATES,
1596 .formats = WM8903_FORMATS,
1599 .stream_name = "Capture",
1602 .rates = WM8903_CAPTURE_RATES,
1603 .formats = WM8903_FORMATS,
1605 .ops = &wm8903_dai_ops,
1606 .symmetric_rates = 1,
1608 EXPORT_SYMBOL_GPL(wm8903_dai);
1610 static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1612 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1613 struct snd_soc_codec *codec = socdev->card->codec;
1615 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1620 static int wm8903_resume(struct platform_device *pdev)
1622 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1623 struct snd_soc_codec *codec = socdev->card->codec;
1624 struct i2c_client *i2c = codec->control_data;
1626 u16 *reg_cache = codec->reg_cache;
1627 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
1630 /* Bring the codec back up to standby first to minimise pop/clicks */
1631 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1633 /* Sync back everything else */
1635 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1636 if (tmp_cache[i] != reg_cache[i])
1637 snd_soc_write(codec, i, tmp_cache[i]);
1640 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1646 static struct snd_soc_codec *wm8903_codec;
1648 static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1649 const struct i2c_device_id *id)
1651 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
1652 struct wm8903_priv *wm8903;
1653 struct snd_soc_codec *codec;
1655 int trigger, irq_pol;
1658 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1662 codec = &wm8903->codec;
1664 mutex_init(&codec->mutex);
1665 INIT_LIST_HEAD(&codec->dapm_widgets);
1666 INIT_LIST_HEAD(&codec->dapm_paths);
1668 codec->dev = &i2c->dev;
1669 codec->name = "WM8903";
1670 codec->owner = THIS_MODULE;
1671 codec->bias_level = SND_SOC_BIAS_OFF;
1672 codec->set_bias_level = wm8903_set_bias_level;
1673 codec->dai = &wm8903_dai;
1675 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1676 codec->reg_cache = &wm8903->reg_cache[0];
1677 snd_soc_codec_set_drvdata(codec, wm8903);
1678 codec->volatile_register = wm8903_volatile_register;
1679 init_completion(&wm8903->wseq);
1681 i2c_set_clientdata(i2c, codec);
1682 codec->control_data = i2c;
1684 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1686 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1690 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
1691 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1693 "Device with ID register %x is not a WM8903\n", val);
1697 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1698 dev_info(&i2c->dev, "WM8903 revision %d\n",
1699 val & WM8903_CHIP_REV_MASK);
1701 wm8903_reset(codec);
1703 /* Set up GPIOs and microphone detection */
1705 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1706 if (!pdata->gpio_cfg[i])
1709 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1710 pdata->gpio_cfg[i] & 0xffff);
1713 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1716 /* Microphone detection needs the WSEQ clock */
1717 if (pdata->micdet_cfg)
1718 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1719 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1721 wm8903->mic_delay = pdata->micdet_delay;
1725 if (pdata && pdata->irq_active_low) {
1726 trigger = IRQF_TRIGGER_LOW;
1727 irq_pol = WM8903_IRQ_POL;
1729 trigger = IRQF_TRIGGER_HIGH;
1733 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1734 WM8903_IRQ_POL, irq_pol);
1736 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
1737 trigger | IRQF_ONESHOT,
1740 dev_err(&i2c->dev, "Failed to request IRQ: %d\n",
1745 /* Enable write sequencer interrupts */
1746 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1747 WM8903_IM_WSEQ_BUSY_EINT, 0);
1750 /* power on device */
1751 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1753 /* Latch volume update bits */
1754 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1755 val |= WM8903_ADCVU;
1756 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1757 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1759 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1760 val |= WM8903_DACVU;
1761 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1762 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1764 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1765 val |= WM8903_HPOUTVU;
1766 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1767 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1769 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1770 val |= WM8903_LINEOUTVU;
1771 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1772 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1774 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1775 val |= WM8903_SPKVU;
1776 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1777 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1779 /* Enable DAC soft mute by default */
1780 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
1781 val |= WM8903_DAC_MUTEMODE;
1782 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
1784 wm8903_dai.dev = &i2c->dev;
1785 wm8903_codec = codec;
1787 ret = snd_soc_register_codec(codec);
1789 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1793 ret = snd_soc_register_dai(&wm8903_dai);
1795 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1802 snd_soc_unregister_codec(codec);
1805 free_irq(i2c->irq, wm8903);
1807 wm8903_codec = NULL;
1812 static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1814 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1815 struct wm8903_priv *priv = snd_soc_codec_get_drvdata(codec);
1817 snd_soc_unregister_dai(&wm8903_dai);
1818 snd_soc_unregister_codec(codec);
1820 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1823 free_irq(client->irq, priv);
1827 wm8903_codec = NULL;
1828 wm8903_dai.dev = NULL;
1833 /* i2c codec control layer */
1834 static const struct i2c_device_id wm8903_i2c_id[] = {
1838 MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1840 static struct i2c_driver wm8903_i2c_driver = {
1843 .owner = THIS_MODULE,
1845 .probe = wm8903_i2c_probe,
1846 .remove = __devexit_p(wm8903_i2c_remove),
1847 .id_table = wm8903_i2c_id,
1850 static int wm8903_probe(struct platform_device *pdev)
1852 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1855 if (!wm8903_codec) {
1856 dev_err(&pdev->dev, "I2C device not yet probed\n");
1860 socdev->card->codec = wm8903_codec;
1863 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1865 dev_err(&pdev->dev, "failed to create pcms\n");
1869 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
1870 ARRAY_SIZE(wm8903_snd_controls));
1871 wm8903_add_widgets(socdev->card->codec);
1879 /* power down chip */
1880 static int wm8903_remove(struct platform_device *pdev)
1882 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1883 struct snd_soc_codec *codec = socdev->card->codec;
1885 if (codec->control_data)
1886 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1888 snd_soc_free_pcms(socdev);
1889 snd_soc_dapm_free(socdev);
1894 struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1895 .probe = wm8903_probe,
1896 .remove = wm8903_remove,
1897 .suspend = wm8903_suspend,
1898 .resume = wm8903_resume,
1900 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1902 static int __init wm8903_modinit(void)
1904 return i2c_add_driver(&wm8903_i2c_driver);
1906 module_init(wm8903_modinit);
1908 static void __exit wm8903_exit(void)
1910 i2c_del_driver(&wm8903_i2c_driver);
1912 module_exit(wm8903_exit);
1914 MODULE_DESCRIPTION("ASoC WM8903 driver");
1915 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1916 MODULE_LICENSE("GPL");