2 * wm8961.c -- WM8961 ALSA SoC Audio driver
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Currently unimplemented features:
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
32 #define WM8961_MAX_REGISTER 0xFC
34 static u16 wm8961_reg_defaults[] = {
35 0x009F, /* R0 - Left Input volume */
36 0x009F, /* R1 - Right Input volume */
37 0x0000, /* R2 - LOUT1 volume */
38 0x0000, /* R3 - ROUT1 volume */
39 0x0020, /* R4 - Clocking1 */
40 0x0008, /* R5 - ADC & DAC Control 1 */
41 0x0000, /* R6 - ADC & DAC Control 2 */
42 0x000A, /* R7 - Audio Interface 0 */
43 0x01F4, /* R8 - Clocking2 */
44 0x0000, /* R9 - Audio Interface 1 */
45 0x00FF, /* R10 - Left DAC volume */
46 0x00FF, /* R11 - Right DAC volume */
49 0x0040, /* R14 - Audio Interface 2 */
50 0x0000, /* R15 - Software Reset */
52 0x007B, /* R17 - ALC1 */
53 0x0000, /* R18 - ALC2 */
54 0x0032, /* R19 - ALC3 */
55 0x0000, /* R20 - Noise Gate */
56 0x00C0, /* R21 - Left ADC volume */
57 0x00C0, /* R22 - Right ADC volume */
58 0x0120, /* R23 - Additional control(1) */
59 0x0000, /* R24 - Additional control(2) */
60 0x0000, /* R25 - Pwr Mgmt (1) */
61 0x0000, /* R26 - Pwr Mgmt (2) */
62 0x0000, /* R27 - Additional Control (3) */
63 0x0000, /* R28 - Anti-pop */
65 0x005F, /* R30 - Clocking 3 */
67 0x0000, /* R32 - ADCL signal path */
68 0x0000, /* R33 - ADCR signal path */
75 0x0000, /* R40 - LOUT2 volume */
76 0x0000, /* R41 - ROUT2 volume */
82 0x0000, /* R47 - Pwr Mgmt (3) */
83 0x0023, /* R48 - Additional Control (4) */
84 0x0000, /* R49 - Class D Control 1 */
86 0x0003, /* R51 - Class D Control 2 */
91 0x0106, /* R56 - Clocking 4 */
92 0x0000, /* R57 - DSP Sidetone 0 */
93 0x0000, /* R58 - DSP Sidetone 1 */
95 0x0000, /* R60 - DC Servo 0 */
96 0x0000, /* R61 - DC Servo 1 */
98 0x015E, /* R63 - DC Servo 3 */
100 0x0010, /* R65 - DC Servo 5 */
103 0x0003, /* R68 - Analogue PGA Bias */
104 0x0000, /* R69 - Analogue HP 0 */
106 0x01FB, /* R71 - Analogue HP 2 */
107 0x0000, /* R72 - Charge Pump 1 */
117 0x0000, /* R82 - Charge Pump B */
122 0x0000, /* R87 - Write Sequencer 1 */
123 0x0000, /* R88 - Write Sequencer 2 */
124 0x0000, /* R89 - Write Sequencer 3 */
125 0x0000, /* R90 - Write Sequencer 4 */
126 0x0000, /* R91 - Write Sequencer 5 */
127 0x0000, /* R92 - Write Sequencer 6 */
128 0x0000, /* R93 - Write Sequencer 7 */
287 0x0001, /* R252 - General test 1 */
291 struct snd_soc_codec codec;
293 u16 reg_cache[WM8961_MAX_REGISTER];
296 static int wm8961_volatile_register(unsigned int reg)
299 case WM8961_SOFTWARE_RESET:
300 case WM8961_WRITE_SEQUENCER_7:
301 case WM8961_DC_SERVO_1:
309 static int wm8961_reset(struct snd_soc_codec *codec)
311 return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
315 * The headphone output supports special anti-pop sequences giving
316 * silent power up and power down.
318 static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
319 struct snd_kcontrol *kcontrol, int event)
321 struct snd_soc_codec *codec = w->codec;
322 u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
323 u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
324 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
325 u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
328 if (event & SND_SOC_DAPM_POST_PMU) {
329 /* Make sure the output is shorted */
330 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
331 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
333 /* Enable the charge pump */
334 cp_reg |= WM8961_CP_ENA;
335 snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
339 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
340 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
342 /* Enable the amplifier */
343 hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
344 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
346 /* Second stage enable */
347 hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
348 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
350 /* Enable the DC servo & trigger startup */
352 WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
353 WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
354 dev_dbg(codec->dev, "Enabling DC servo\n");
356 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
359 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
360 } while (--timeout &&
361 dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
362 WM8961_DCS_TRIG_STARTUP_HPL));
363 if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
364 WM8961_DCS_TRIG_STARTUP_HPL))
365 dev_err(codec->dev, "DC servo timed out\n");
367 dev_dbg(codec->dev, "DC servo startup complete\n");
369 /* Enable the output stage */
370 hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
371 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
373 /* Remove the short on the output stage */
374 hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
375 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
378 if (event & SND_SOC_DAPM_PRE_PMD) {
379 /* Short the output */
380 hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
381 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
383 /* Disable the output stage */
384 hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
385 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
387 /* Disable DC offset cancellation */
388 dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
389 WM8961_DCS_ENA_CHAN_HPL);
390 snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
393 hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
394 WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
395 snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
397 /* Disable the PGA */
398 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
399 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
401 /* Disable the charge pump */
402 dev_dbg(codec->dev, "Disabling charge pump\n");
403 snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
404 cp_reg & ~WM8961_CP_ENA);
410 static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
411 struct snd_kcontrol *kcontrol, int event)
413 struct snd_soc_codec *codec = w->codec;
414 u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
415 u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
417 if (event & SND_SOC_DAPM_POST_PMU) {
419 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
420 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
422 /* Enable the amplifier */
423 spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
424 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
427 if (event & SND_SOC_DAPM_PRE_PMD) {
428 /* Enable the amplifier */
429 spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
430 snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
433 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
434 snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
440 static const char *adc_hpf_text[] = {
441 "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
444 static const struct soc_enum adc_hpf =
445 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
447 static const char *dac_deemph_text[] = {
448 "None", "32kHz", "44.1kHz", "48kHz",
451 static const struct soc_enum dac_deemph =
452 SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
454 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
455 static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
456 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
457 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
458 static unsigned int boost_tlv[] = {
459 TLV_DB_RANGE_HEAD(4),
460 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
461 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
462 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
463 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
465 static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
467 static const struct snd_kcontrol_new wm8961_snd_controls[] = {
468 SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
470 SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
471 6, 3, 7, 0, hp_sec_tlv),
472 SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
475 SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
477 SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
479 SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
481 SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
482 SOC_ENUM("DAC Deemphasis", dac_deemph),
483 SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
485 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
486 WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
488 SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
489 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
491 SOC_DOUBLE_R_TLV("Capture Volume",
492 WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
494 SOC_DOUBLE_R_TLV("Capture Boost Volume",
495 WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
497 SOC_DOUBLE_R_TLV("Capture PGA Volume",
498 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
500 SOC_DOUBLE_R("Capture PGA ZC Switch",
501 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
503 SOC_DOUBLE_R("Capture PGA Switch",
504 WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
508 static const char *sidetone_text[] = {
509 "None", "Left", "Right"
512 static const struct soc_enum dacl_sidetone =
513 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
515 static const struct soc_enum dacr_sidetone =
516 SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
518 static const struct snd_kcontrol_new dacl_mux =
519 SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
521 static const struct snd_kcontrol_new dacr_mux =
522 SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
524 static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
525 SND_SOC_DAPM_INPUT("LINPUT"),
526 SND_SOC_DAPM_INPUT("RINPUT"),
528 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
530 SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
531 SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
533 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
534 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
536 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8961_PWR_MGMT_1, 1, 0),
538 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
539 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
541 SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
542 SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
544 /* Handle as a mono path for DCS */
545 SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
546 4, 0, NULL, 0, wm8961_hp_event,
547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
548 SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
549 4, 0, NULL, 0, wm8961_spk_event,
550 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
552 SND_SOC_DAPM_OUTPUT("HP_L"),
553 SND_SOC_DAPM_OUTPUT("HP_R"),
554 SND_SOC_DAPM_OUTPUT("SPK_LN"),
555 SND_SOC_DAPM_OUTPUT("SPK_LP"),
556 SND_SOC_DAPM_OUTPUT("SPK_RN"),
557 SND_SOC_DAPM_OUTPUT("SPK_RP"),
561 static const struct snd_soc_dapm_route audio_paths[] = {
562 { "DACL", NULL, "CLK_DSP" },
563 { "DACL", NULL, "DACL Sidetone" },
564 { "DACR", NULL, "CLK_DSP" },
565 { "DACR", NULL, "DACR Sidetone" },
567 { "DACL Sidetone", "Left", "ADCL" },
568 { "DACL Sidetone", "Right", "ADCR" },
570 { "DACR Sidetone", "Left", "ADCL" },
571 { "DACR Sidetone", "Right", "ADCR" },
573 { "HP_L", NULL, "Headphone Output" },
574 { "HP_R", NULL, "Headphone Output" },
575 { "Headphone Output", NULL, "DACL" },
576 { "Headphone Output", NULL, "DACR" },
578 { "SPK_LN", NULL, "Speaker Output" },
579 { "SPK_LP", NULL, "Speaker Output" },
580 { "SPK_RN", NULL, "Speaker Output" },
581 { "SPK_RP", NULL, "Speaker Output" },
583 { "Speaker Output", NULL, "DACL" },
584 { "Speaker Output", NULL, "DACR" },
586 { "ADCL", NULL, "Left Input" },
587 { "ADCL", NULL, "CLK_DSP" },
588 { "ADCR", NULL, "Right Input" },
589 { "ADCR", NULL, "CLK_DSP" },
591 { "Left Input", NULL, "LINPUT" },
592 { "Right Input", NULL, "RINPUT" },
596 /* Values for CLK_SYS_RATE */
600 } wm8961_clk_sys_ratio[] = {
613 /* Values for SAMPLE_RATE */
629 static int wm8961_hw_params(struct snd_pcm_substream *substream,
630 struct snd_pcm_hw_params *params,
631 struct snd_soc_dai *dai)
633 struct snd_soc_codec *codec = dai->codec;
634 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
635 int i, best, target, fs;
638 fs = params_rate(params);
640 if (!wm8961->sysclk) {
641 dev_err(codec->dev, "MCLK has not been specified\n");
645 /* Find the closest sample rate for the filters */
647 for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
648 if (abs(wm8961_srate[i].rate - fs) <
649 abs(wm8961_srate[best].rate - fs))
652 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
653 reg &= ~WM8961_SAMPLE_RATE_MASK;
654 reg |= wm8961_srate[best].val;
655 snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
656 dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
657 wm8961_srate[best].rate, fs);
659 /* Select a CLK_SYS/fs ratio equal to or higher than required */
660 target = wm8961->sysclk / fs;
662 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
664 "SYSCLK must be at least 64*fs for DAC\n");
667 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
669 "SYSCLK must be at least 256*fs for ADC\n");
673 for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
674 if (wm8961_clk_sys_ratio[i].ratio >= target)
677 if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
678 dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
681 dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
682 wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
683 wm8961->sysclk / fs);
685 reg = snd_soc_read(codec, WM8961_CLOCKING_4);
686 reg &= ~WM8961_CLK_SYS_RATE_MASK;
687 reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
688 snd_soc_write(codec, WM8961_CLOCKING_4, reg);
690 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
691 reg &= ~WM8961_WL_MASK;
692 switch (params_format(params)) {
693 case SNDRV_PCM_FORMAT_S16_LE:
695 case SNDRV_PCM_FORMAT_S20_3LE:
696 reg |= 1 << WM8961_WL_SHIFT;
698 case SNDRV_PCM_FORMAT_S24_LE:
699 reg |= 2 << WM8961_WL_SHIFT;
701 case SNDRV_PCM_FORMAT_S32_LE:
702 reg |= 3 << WM8961_WL_SHIFT;
707 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
709 /* Sloping stop-band filter is recommended for <= 24kHz */
710 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
712 reg |= WM8961_DACSLOPE;
714 reg &= WM8961_DACSLOPE;
715 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
720 static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
724 struct snd_soc_codec *codec = dai->codec;
725 struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
726 u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
728 if (freq > 33000000) {
729 dev_err(codec->dev, "MCLK must be <33MHz\n");
733 if (freq > 16500000) {
734 dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
735 reg |= WM8961_MCLKDIV;
738 dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
739 reg &= WM8961_MCLKDIV;
742 snd_soc_write(codec, WM8961_CLOCKING1, reg);
744 wm8961->sysclk = freq;
749 static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
751 struct snd_soc_codec *codec = dai->codec;
752 u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
754 aif &= ~(WM8961_BCLKINV | WM8961_LRP |
755 WM8961_MS | WM8961_FORMAT_MASK);
757 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
758 case SND_SOC_DAIFMT_CBM_CFM:
761 case SND_SOC_DAIFMT_CBS_CFS:
767 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
768 case SND_SOC_DAIFMT_RIGHT_J:
771 case SND_SOC_DAIFMT_LEFT_J:
775 case SND_SOC_DAIFMT_I2S:
779 case SND_SOC_DAIFMT_DSP_B:
781 case SND_SOC_DAIFMT_DSP_A:
783 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
784 case SND_SOC_DAIFMT_NB_NF:
785 case SND_SOC_DAIFMT_IB_NF:
796 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
797 case SND_SOC_DAIFMT_NB_NF:
799 case SND_SOC_DAIFMT_NB_IF:
802 case SND_SOC_DAIFMT_IB_NF:
803 aif |= WM8961_BCLKINV;
805 case SND_SOC_DAIFMT_IB_IF:
806 aif |= WM8961_BCLKINV | WM8961_LRP;
812 return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
815 static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
817 struct snd_soc_codec *codec = dai->codec;
818 u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
825 return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
828 static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
830 struct snd_soc_codec *codec = dai->codec;
831 u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
836 reg &= ~WM8961_DACMU;
840 return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
843 static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
845 struct snd_soc_codec *codec = dai->codec;
850 reg = snd_soc_read(codec, WM8961_CLOCKING2);
851 reg &= ~WM8961_BCLKDIV_MASK;
853 snd_soc_write(codec, WM8961_CLOCKING2, reg);
857 reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
858 reg &= ~WM8961_LRCLK_RATE_MASK;
860 snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
870 static int wm8961_set_bias_level(struct snd_soc_codec *codec,
871 enum snd_soc_bias_level level)
875 /* This is all slightly unusual since we have no bypass paths
876 * and the output amplifier structure means we can just slam
877 * the biases straight up rather than having to ramp them
881 case SND_SOC_BIAS_ON:
884 case SND_SOC_BIAS_PREPARE:
885 if (codec->bias_level == SND_SOC_BIAS_STANDBY) {
886 /* Enable bias generation */
887 reg = snd_soc_read(codec, WM8961_ANTI_POP);
888 reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
889 snd_soc_write(codec, WM8961_ANTI_POP, reg);
891 /* VMID=2*50k, VREF */
892 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
893 reg &= ~WM8961_VMIDSEL_MASK;
894 reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
895 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
899 case SND_SOC_BIAS_STANDBY:
900 if (codec->bias_level == SND_SOC_BIAS_PREPARE) {
902 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
904 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
906 /* Bias generation off */
907 reg = snd_soc_read(codec, WM8961_ANTI_POP);
908 reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
909 snd_soc_write(codec, WM8961_ANTI_POP, reg);
912 reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
913 reg &= ~WM8961_VMIDSEL_MASK;
914 snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
918 case SND_SOC_BIAS_OFF:
922 codec->bias_level = level;
928 #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
930 #define WM8961_FORMATS \
931 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
932 SNDRV_PCM_FMTBIT_S24_LE)
934 static struct snd_soc_dai_ops wm8961_dai_ops = {
935 .hw_params = wm8961_hw_params,
936 .set_sysclk = wm8961_set_sysclk,
937 .set_fmt = wm8961_set_fmt,
938 .digital_mute = wm8961_digital_mute,
939 .set_tristate = wm8961_set_tristate,
940 .set_clkdiv = wm8961_set_clkdiv,
943 struct snd_soc_dai wm8961_dai = {
946 .stream_name = "HiFi Playback",
949 .rates = WM8961_RATES,
950 .formats = WM8961_FORMATS,},
952 .stream_name = "HiFi Capture",
955 .rates = WM8961_RATES,
956 .formats = WM8961_FORMATS,},
957 .ops = &wm8961_dai_ops,
959 EXPORT_SYMBOL_GPL(wm8961_dai);
962 static struct snd_soc_codec *wm8961_codec;
964 static int wm8961_probe(struct platform_device *pdev)
966 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
967 struct snd_soc_codec *codec;
970 if (wm8961_codec == NULL) {
971 dev_err(&pdev->dev, "Codec device not registered\n");
975 socdev->card->codec = wm8961_codec;
976 codec = wm8961_codec;
979 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
981 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
985 snd_soc_add_controls(codec, wm8961_snd_controls,
986 ARRAY_SIZE(wm8961_snd_controls));
987 snd_soc_dapm_new_controls(codec, wm8961_dapm_widgets,
988 ARRAY_SIZE(wm8961_dapm_widgets));
989 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
997 static int wm8961_remove(struct platform_device *pdev)
999 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1001 snd_soc_free_pcms(socdev);
1002 snd_soc_dapm_free(socdev);
1008 static int wm8961_suspend(struct platform_device *pdev, pm_message_t state)
1010 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1011 struct snd_soc_codec *codec = socdev->card->codec;
1013 wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
1018 static int wm8961_resume(struct platform_device *pdev)
1020 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1021 struct snd_soc_codec *codec = socdev->card->codec;
1022 u16 *reg_cache = codec->reg_cache;
1025 for (i = 0; i < codec->reg_cache_size; i++) {
1026 if (reg_cache[i] == wm8961_reg_defaults[i])
1029 if (i == WM8961_SOFTWARE_RESET)
1032 snd_soc_write(codec, i, reg_cache[i]);
1035 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1040 #define wm8961_suspend NULL
1041 #define wm8961_resume NULL
1044 struct snd_soc_codec_device soc_codec_dev_wm8961 = {
1045 .probe = wm8961_probe,
1046 .remove = wm8961_remove,
1047 .suspend = wm8961_suspend,
1048 .resume = wm8961_resume,
1050 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8961);
1052 static int wm8961_register(struct wm8961_priv *wm8961)
1054 struct snd_soc_codec *codec = &wm8961->codec;
1059 dev_err(codec->dev, "Another WM8961 is registered\n");
1064 mutex_init(&codec->mutex);
1065 INIT_LIST_HEAD(&codec->dapm_widgets);
1066 INIT_LIST_HEAD(&codec->dapm_paths);
1068 snd_soc_codec_set_drvdata(codec, wm8961);
1069 codec->name = "WM8961";
1070 codec->owner = THIS_MODULE;
1071 codec->dai = &wm8961_dai;
1073 codec->reg_cache_size = ARRAY_SIZE(wm8961->reg_cache);
1074 codec->reg_cache = &wm8961->reg_cache;
1075 codec->bias_level = SND_SOC_BIAS_OFF;
1076 codec->set_bias_level = wm8961_set_bias_level;
1077 codec->volatile_register = wm8961_volatile_register;
1079 memcpy(codec->reg_cache, wm8961_reg_defaults,
1080 sizeof(wm8961_reg_defaults));
1082 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1084 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1088 reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
1089 if (reg != 0x1801) {
1090 dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
1095 /* This isn't volatile - readback doesn't correspond to write */
1096 reg = codec->hw_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1097 dev_info(codec->dev, "WM8961 family %d revision %c\n",
1098 (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
1099 ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
1102 ret = wm8961_reset(codec);
1104 dev_err(codec->dev, "Failed to issue reset\n");
1108 /* Enable class W */
1109 reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
1110 reg |= WM8961_CP_DYN_PWR_MASK;
1111 snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
1113 /* Latch volume update bits (right channel only, we always
1114 * write both out) and default ZC on. */
1115 reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
1116 snd_soc_write(codec, WM8961_ROUT1_VOLUME,
1117 reg | WM8961_LO1ZC | WM8961_OUT1VU);
1118 snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
1119 reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
1120 snd_soc_write(codec, WM8961_ROUT2_VOLUME,
1121 reg | WM8961_SPKRZC | WM8961_SPKVU);
1122 snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
1124 reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
1125 snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
1126 reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
1127 snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
1129 /* Use soft mute by default */
1130 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
1131 reg |= WM8961_DACSMM;
1132 snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
1134 /* Use automatic clocking mode by default; for now this is all
1137 reg = snd_soc_read(codec, WM8961_CLOCKING_3);
1138 reg &= ~WM8961_MANUAL_MODE;
1139 snd_soc_write(codec, WM8961_CLOCKING_3, reg);
1141 wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1143 wm8961_dai.dev = codec->dev;
1145 wm8961_codec = codec;
1147 ret = snd_soc_register_codec(codec);
1149 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1153 ret = snd_soc_register_dai(&wm8961_dai);
1155 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1162 snd_soc_unregister_codec(codec);
1168 static void wm8961_unregister(struct wm8961_priv *wm8961)
1170 wm8961_set_bias_level(&wm8961->codec, SND_SOC_BIAS_OFF);
1171 snd_soc_unregister_dai(&wm8961_dai);
1172 snd_soc_unregister_codec(&wm8961->codec);
1174 wm8961_codec = NULL;
1177 static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
1178 const struct i2c_device_id *id)
1180 struct wm8961_priv *wm8961;
1181 struct snd_soc_codec *codec;
1183 wm8961 = kzalloc(sizeof(struct wm8961_priv), GFP_KERNEL);
1187 codec = &wm8961->codec;
1189 i2c_set_clientdata(i2c, wm8961);
1190 codec->control_data = i2c;
1192 codec->dev = &i2c->dev;
1194 return wm8961_register(wm8961);
1197 static __devexit int wm8961_i2c_remove(struct i2c_client *client)
1199 struct wm8961_priv *wm8961 = i2c_get_clientdata(client);
1200 wm8961_unregister(wm8961);
1204 static const struct i2c_device_id wm8961_i2c_id[] = {
1208 MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
1210 static struct i2c_driver wm8961_i2c_driver = {
1213 .owner = THIS_MODULE,
1215 .probe = wm8961_i2c_probe,
1216 .remove = __devexit_p(wm8961_i2c_remove),
1217 .id_table = wm8961_i2c_id,
1220 static int __init wm8961_modinit(void)
1224 ret = i2c_add_driver(&wm8961_i2c_driver);
1226 printk(KERN_ERR "Failed to register WM8961 I2C driver: %d\n",
1232 module_init(wm8961_modinit);
1234 static void __exit wm8961_exit(void)
1236 i2c_del_driver(&wm8961_i2c_driver);
1238 module_exit(wm8961_exit);
1241 MODULE_DESCRIPTION("ASoC WM8961 driver");
1242 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1243 MODULE_LICENSE("GPL");