sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009-12 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static struct {
  50         unsigned int reg;
  51         unsigned int mask;
  52 } wm8994_vu_bits[] = {
  53         { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  54         { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
  55         { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  56         { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
  57         { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
  58         { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
  59         { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  60         { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
  61         { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  62         { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
  63
  64         { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
  65         { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
  66         { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
  67         { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
  68         { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
  69         { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
  70         { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
  71         { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
  72         { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
  73         { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  74         { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
  75         { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
  76         { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
  77         { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
  78         { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
  79         { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
  80 };
  81
  82 static int wm8994_drc_base[] = {
  83         WM8994_AIF1_DRC1_1,
  84         WM8994_AIF1_DRC2_1,
  85         WM8994_AIF2_DRC_1,
  86 };
  87
  88 static int wm8994_retune_mobile_base[] = {
  89         WM8994_AIF1_DAC1_EQ_GAINS_1,
  90         WM8994_AIF1_DAC2_EQ_GAINS_1,
  91         WM8994_AIF2_EQ_GAINS_1,
  92 };
  93
  94 static void wm8958_default_micdet(u16 status, void *data);
  95
  96 static const struct wm8958_micd_rate micdet_rates[] = {
  97         { 32768,       true,  1, 4 },
  98         { 32768,       false, 1, 1 },
  99         { 44100 * 256, true,  7, 10 },
 100         { 44100 * 256, false, 7, 10 },
 101 };
 102
 103 static const struct wm8958_micd_rate jackdet_rates[] = {
 104         { 32768,       true,  0, 1 },
 105         { 32768,       false, 0, 1 },
 106         { 44100 * 256, true,  10, 10 },
 107         { 44100 * 256, false, 7, 8 },
 108 };
 109
 110 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
 111 {
 112         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 113         int best, i, sysclk, val;
 114         bool idle;
 115         const struct wm8958_micd_rate *rates;
 116         int num_rates;
 117
 118         if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
 119             wm8994->jack_cb != wm8958_default_micdet)
 120                 return;
 121
 122         idle = !wm8994->jack_mic;
 123
 124         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
 125         if (sysclk & WM8994_SYSCLK_SRC)
 126                 sysclk = wm8994->aifclk[1];
 127         else
 128                 sysclk = wm8994->aifclk[0];
 129
 130         if (wm8994->pdata && wm8994->pdata->micd_rates) {
 131                 rates = wm8994->pdata->micd_rates;
 132                 num_rates = wm8994->pdata->num_micd_rates;
 133         } else if (wm8994->jackdet) {
 134                 rates = jackdet_rates;
 135                 num_rates = ARRAY_SIZE(jackdet_rates);
 136         } else {
 137                 rates = micdet_rates;
 138                 num_rates = ARRAY_SIZE(micdet_rates);
 139         }
 140
 141         best = 0;
 142         for (i = 0; i < num_rates; i++) {
 143                 if (rates[i].idle != idle)
 144                         continue;
 145                 if (abs(rates[i].sysclk - sysclk) <
 146                     abs(rates[best].sysclk - sysclk))
 147                         best = i;
 148                 else if (rates[best].idle != idle)
 149                         best = i;
 150         }
 151
 152         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 153                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 154
 155         dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
 156                 rates[best].start, rates[best].rate, sysclk,
 157                 idle ? "idle" : "active");
 158
 159         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 160                             WM8958_MICD_BIAS_STARTTIME_MASK |
 161                             WM8958_MICD_RATE_MASK, val);
 162 }
 163
 164 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 165 {
 166         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 167         int rate;
 168         int reg1 = 0;
 169         int offset;
 170
 171         if (aif)
 172                 offset = 4;
 173         else
 174                 offset = 0;
 175
 176         switch (wm8994->sysclk[aif]) {
 177         case WM8994_SYSCLK_MCLK1:
 178                 rate = wm8994->mclk[0];
 179                 break;
 180
 181         case WM8994_SYSCLK_MCLK2:
 182                 reg1 |= 0x8;
 183                 rate = wm8994->mclk[1];
 184                 break;
 185
 186         case WM8994_SYSCLK_FLL1:
 187                 reg1 |= 0x10;
 188                 rate = wm8994->fll[0].out;
 189                 break;
 190
 191         case WM8994_SYSCLK_FLL2:
 192                 reg1 |= 0x18;
 193                 rate = wm8994->fll[1].out;
 194                 break;
 195
 196         default:
 197                 return -EINVAL;
 198         }
 199
 200         if (rate >= 13500000) {
 201                 rate /= 2;
 202                 reg1 |= WM8994_AIF1CLK_DIV;
 203
 204                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 205                         aif + 1, rate);
 206         }
 207
 208         wm8994->aifclk[aif] = rate;
 209
 210         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 211                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 212                             reg1);
 213
 214         return 0;
 215 }
 216
 217 static int configure_clock(struct snd_soc_codec *codec)
 218 {
 219         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 220         int change, new;
 221
 222         /* Bring up the AIF clocks first */
 223         configure_aif_clock(codec, 0);
 224         configure_aif_clock(codec, 1);
 225
 226         /* Then switch CLK_SYS over to the higher of them; a change
 227          * can only happen as a result of a clocking change which can
 228          * only be made outside of DAPM so we can safely redo the
 229          * clocking.
 230          */
 231
 232         /* If they're equal it doesn't matter which is used */
 233         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 234                 wm8958_micd_set_rate(codec);
 235                 return 0;
 236         }
 237
 238         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 239                 new = WM8994_SYSCLK_SRC;
 240         else
 241                 new = 0;
 242
 243         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 244                                      WM8994_SYSCLK_SRC, new);
 245         if (change)
 246                 snd_soc_dapm_sync(&codec->dapm);
 247
 248         wm8958_micd_set_rate(codec);
 249
 250         return 0;
 251 }
 252
 253 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 254                          struct snd_soc_dapm_widget *sink)
 255 {
 256         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 257         const char *clk;
 258
 259         /* Check what we're currently using for CLK_SYS */
 260         if (reg & WM8994_SYSCLK_SRC)
 261                 clk = "AIF2CLK";
 262         else
 263                 clk = "AIF1CLK";
 264
 265         return strcmp(source->name, clk) == 0;
 266 }
 267
 268 static const char *sidetone_hpf_text[] = {
 269         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 270 };
 271
 272 static const struct soc_enum sidetone_hpf =
 273         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 274
 275 static const char *adc_hpf_text[] = {
 276         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 277 };
 278
 279 static const struct soc_enum aif1adc1_hpf =
 280         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 281
 282 static const struct soc_enum aif1adc2_hpf =
 283         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 284
 285 static const struct soc_enum aif2adc_hpf =
 286         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 287
 288 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 289 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 290 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 291 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 292 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 293 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 294 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 295
 296 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 297 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 298         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 299         .put = wm8994_put_drc_sw, \
 300         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 301
 302 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 303                              struct snd_ctl_elem_value *ucontrol)
 304 {
 305         struct soc_mixer_control *mc =
 306                 (struct soc_mixer_control *)kcontrol->private_value;
 307         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 308         int mask, ret;
 309
 310         /* Can't enable both ADC and DAC paths simultaneously */
 311         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 312                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 313                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 314         else
 315                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 316
 317         ret = snd_soc_read(codec, mc->reg);
 318         if (ret < 0)
 319                 return ret;
 320         if (ret & mask)
 321                 return -EINVAL;
 322
 323         return snd_soc_put_volsw(kcontrol, ucontrol);
 324 }
 325
 326 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 327 {
 328         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 329         struct wm8994_pdata *pdata = wm8994->pdata;
 330         int base = wm8994_drc_base[drc];
 331         int cfg = wm8994->drc_cfg[drc];
 332         int save, i;
 333
 334         /* Save any enables; the configuration should clear them. */
 335         save = snd_soc_read(codec, base);
 336         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 337                 WM8994_AIF1ADC1R_DRC_ENA;
 338
 339         for (i = 0; i < WM8994_DRC_REGS; i++)
 340                 snd_soc_update_bits(codec, base + i, 0xffff,
 341                                     pdata->drc_cfgs[cfg].regs[i]);
 342
 343         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 344                              WM8994_AIF1ADC1L_DRC_ENA |
 345                              WM8994_AIF1ADC1R_DRC_ENA, save);
 346 }
 347
 348 /* Icky as hell but saves code duplication */
 349 static int wm8994_get_drc(const char *name)
 350 {
 351         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 352                 return 0;
 353         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 354                 return 1;
 355         if (strcmp(name, "AIF2DRC Mode") == 0)
 356                 return 2;
 357         return -EINVAL;
 358 }
 359
 360 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 361                                struct snd_ctl_elem_value *ucontrol)
 362 {
 363         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 364         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 365         struct wm8994_pdata *pdata = wm8994->pdata;
 366         int drc = wm8994_get_drc(kcontrol->id.name);
 367         int value = ucontrol->value.integer.value[0];
 368
 369         if (drc < 0)
 370                 return drc;
 371
 372         if (value >= pdata->num_drc_cfgs)
 373                 return -EINVAL;
 374
 375         wm8994->drc_cfg[drc] = value;
 376
 377         wm8994_set_drc(codec, drc);
 378
 379         return 0;
 380 }
 381
 382 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 383                                struct snd_ctl_elem_value *ucontrol)
 384 {
 385         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 386         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 387         int drc = wm8994_get_drc(kcontrol->id.name);
 388
 389         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 390
 391         return 0;
 392 }
 393
 394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 395 {
 396         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 397         struct wm8994_pdata *pdata = wm8994->pdata;
 398         int base = wm8994_retune_mobile_base[block];
 399         int iface, best, best_val, save, i, cfg;
 400
 401         if (!pdata || !wm8994->num_retune_mobile_texts)
 402                 return;
 403
 404         switch (block) {
 405         case 0:
 406         case 1:
 407                 iface = 0;
 408                 break;
 409         case 2:
 410                 iface = 1;
 411                 break;
 412         default:
 413                 return;
 414         }
 415
 416         /* Find the version of the currently selected configuration
 417          * with the nearest sample rate. */
 418         cfg = wm8994->retune_mobile_cfg[block];
 419         best = 0;
 420         best_val = INT_MAX;
 421         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 422                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 423                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 424                     abs(pdata->retune_mobile_cfgs[i].rate
 425                         - wm8994->dac_rates[iface]) < best_val) {
 426                         best = i;
 427                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 428                                        - wm8994->dac_rates[iface]);
 429                 }
 430         }
 431
 432         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 433                 block,
 434                 pdata->retune_mobile_cfgs[best].name,
 435                 pdata->retune_mobile_cfgs[best].rate,
 436                 wm8994->dac_rates[iface]);
 437
 438         /* The EQ will be disabled while reconfiguring it, remember the
 439          * current configuration.
 440          */
 441         save = snd_soc_read(codec, base);
 442         save &= WM8994_AIF1DAC1_EQ_ENA;
 443
 444         for (i = 0; i < WM8994_EQ_REGS; i++)
 445                 snd_soc_update_bits(codec, base + i, 0xffff,
 446                                 pdata->retune_mobile_cfgs[best].regs[i]);
 447
 448         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 449 }
 450
 451 /* Icky as hell but saves code duplication */
 452 static int wm8994_get_retune_mobile_block(const char *name)
 453 {
 454         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 455                 return 0;
 456         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 457                 return 1;
 458         if (strcmp(name, "AIF2 EQ Mode") == 0)
 459                 return 2;
 460         return -EINVAL;
 461 }
 462
 463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 464                                          struct snd_ctl_elem_value *ucontrol)
 465 {
 466         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 467         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 468         struct wm8994_pdata *pdata = wm8994->pdata;
 469         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 470         int value = ucontrol->value.integer.value[0];
 471
 472         if (block < 0)
 473                 return block;
 474
 475         if (value >= pdata->num_retune_mobile_cfgs)
 476                 return -EINVAL;
 477
 478         wm8994->retune_mobile_cfg[block] = value;
 479
 480         wm8994_set_retune_mobile(codec, block);
 481
 482         return 0;
 483 }
 484
 485 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 486                                          struct snd_ctl_elem_value *ucontrol)
 487 {
 488         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 489         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 490         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 491
 492         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 493
 494         return 0;
 495 }
 496
 497 static const char *aif_chan_src_text[] = {
 498         "Left", "Right"
 499 };
 500
 501 static const struct soc_enum aif1adcl_src =
 502         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 503
 504 static const struct soc_enum aif1adcr_src =
 505         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 506
 507 static const struct soc_enum aif2adcl_src =
 508         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 509
 510 static const struct soc_enum aif2adcr_src =
 511         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 512
 513 static const struct soc_enum aif1dacl_src =
 514         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 515
 516 static const struct soc_enum aif1dacr_src =
 517         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 518
 519 static const struct soc_enum aif2dacl_src =
 520         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 521
 522 static const struct soc_enum aif2dacr_src =
 523         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 524
 525 static const char *osr_text[] = {
 526         "Low Power", "High Performance",
 527 };
 528
 529 static const struct soc_enum dac_osr =
 530         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 531
 532 static const struct soc_enum adc_osr =
 533         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 534
 535 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 537                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 538                  1, 119, 0, digital_tlv),
 539 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 540                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 541                  1, 119, 0, digital_tlv),
 542 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 543                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 544                  1, 119, 0, digital_tlv),
 545
 546 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 547 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 548 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 549 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 550
 551 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 552 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 553 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 554 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 555
 556 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 557                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 558 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 559                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 560 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 561                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 562
 563 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 564 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 565
 566 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 567 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 568 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 569
 570 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 571 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 572 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 573
 574 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 575 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 576 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 577
 578 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 579 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 580 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 581
 582 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 583                5, 12, 0, st_tlv),
 584 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 585                0, 12, 0, st_tlv),
 586 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 587                5, 12, 0, st_tlv),
 588 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 589                0, 12, 0, st_tlv),
 590 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 591 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 592
 593 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 594 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 595
 596 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 597 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 598
 599 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 600 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 601
 602 SOC_ENUM("ADC OSR", adc_osr),
 603 SOC_ENUM("DAC OSR", dac_osr),
 604
 605 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 606                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 607 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 608              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 609
 610 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 611                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 612 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 613              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 614
 615 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 616                6, 1, 1, wm_hubs_spkmix_tlv),
 617 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 618                2, 1, 1, wm_hubs_spkmix_tlv),
 619
 620 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 621                6, 1, 1, wm_hubs_spkmix_tlv),
 622 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 623                2, 1, 1, wm_hubs_spkmix_tlv),
 624
 625 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 626                10, 15, 0, wm8994_3d_tlv),
 627 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 628            8, 1, 0),
 629 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 630                10, 15, 0, wm8994_3d_tlv),
 631 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 632            8, 1, 0),
 633 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 634                10, 15, 0, wm8994_3d_tlv),
 635 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 636            8, 1, 0),
 637 };
 638
 639 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 640 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 649                eq_tlv),
 650
 651 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 660                eq_tlv),
 661
 662 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 663                eq_tlv),
 664 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 665                eq_tlv),
 666 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 667                eq_tlv),
 668 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 669                eq_tlv),
 670 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 671                eq_tlv),
 672 };
 673
 674 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
 675 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
 676                    WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 677                    WM8994_AIF1ADC1R_DRC_ENA),
 678 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
 679                    WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
 680                    WM8994_AIF1ADC2R_DRC_ENA),
 681 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
 682                    WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
 683                    WM8994_AIF2ADCR_DRC_ENA),
 684 };
 685
 686 static const char *wm8958_ng_text[] = {
 687         "30ms", "125ms", "250ms", "500ms",
 688 };
 689
 690 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 691         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 692                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 693
 694 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 695         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 696                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 697
 698 static const struct soc_enum wm8958_aif2dac_ng_hold =
 699         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 700                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 701
 702 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 703 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 704
 705 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 706            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 707 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 708 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 709                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 710                7, 1, ng_tlv),
 711
 712 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 713            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 714 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 715 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 716                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 717                7, 1, ng_tlv),
 718
 719 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 720            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 721 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 722 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 723                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 724                7, 1, ng_tlv),
 725 };
 726
 727 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 728 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 729                mixin_boost_tlv),
 730 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 731                mixin_boost_tlv),
 732 };
 733
 734 /* We run all mode setting through a function to enforce audio mode */
 735 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 736 {
 737         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 738
 739         if (!wm8994->jackdet || !wm8994->jack_cb)
 740                 return;
 741
 742         if (wm8994->active_refcount)
 743                 mode = WM1811_JACKDET_MODE_AUDIO;
 744
 745         if (mode == wm8994->jackdet_mode)
 746                 return;
 747
 748         wm8994->jackdet_mode = mode;
 749
 750         /* Always use audio mode to detect while the system is active */
 751         if (mode != WM1811_JACKDET_MODE_NONE)
 752                 mode = WM1811_JACKDET_MODE_AUDIO;
 753
 754         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 755                             WM1811_JACKDET_MODE_MASK, mode);
 756 }
 757
 758 static void active_reference(struct snd_soc_codec *codec)
 759 {
 760         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 761
 762         mutex_lock(&wm8994->accdet_lock);
 763
 764         wm8994->active_refcount++;
 765
 766         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 767                 wm8994->active_refcount);
 768
 769         /* If we're using jack detection go into audio mode */
 770         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
 771
 772         mutex_unlock(&wm8994->accdet_lock);
 773 }
 774
 775 static void active_dereference(struct snd_soc_codec *codec)
 776 {
 777         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 778         u16 mode;
 779
 780         mutex_lock(&wm8994->accdet_lock);
 781
 782         wm8994->active_refcount--;
 783
 784         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 785                 wm8994->active_refcount);
 786
 787         if (wm8994->active_refcount == 0) {
 788                 /* Go into appropriate detection only mode */
 789                 if (wm8994->jack_mic || wm8994->mic_detecting)
 790                         mode = WM1811_JACKDET_MODE_MIC;
 791                 else
 792                         mode = WM1811_JACKDET_MODE_JACK;
 793
 794                 wm1811_jackdet_set_mode(codec, mode);
 795         }
 796
 797         mutex_unlock(&wm8994->accdet_lock);
 798 }
 799
 800 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 801                          struct snd_kcontrol *kcontrol, int event)
 802 {
 803         struct snd_soc_codec *codec = w->codec;
 804         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 805
 806         switch (event) {
 807         case SND_SOC_DAPM_PRE_PMU:
 808                 return configure_clock(codec);
 809
 810         case SND_SOC_DAPM_POST_PMU:
 811                 /*
 812                  * JACKDET won't run until we start the clock and it
 813                  * only reports deltas, make sure we notify the state
 814                  * up the stack on startup.  Use a *very* generous
 815                  * timeout for paranoia, there's no urgency and we
 816                  * don't want false reports.
 817                  */
 818                 if (wm8994->jackdet && !wm8994->clk_has_run) {
 819                         schedule_delayed_work(&wm8994->jackdet_bootstrap,
 820                                               msecs_to_jiffies(1000));
 821                         wm8994->clk_has_run = true;
 822                 }
 823                 break;
 824
 825         case SND_SOC_DAPM_POST_PMD:
 826                 configure_clock(codec);
 827                 break;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static void vmid_reference(struct snd_soc_codec *codec)
 834 {
 835         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 836
 837         pm_runtime_get_sync(codec->dev);
 838
 839         wm8994->vmid_refcount++;
 840
 841         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 842                 wm8994->vmid_refcount);
 843
 844         if (wm8994->vmid_refcount == 1) {
 845                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 846                                     WM8994_LINEOUT1_DISCH |
 847                                     WM8994_LINEOUT2_DISCH, 0);
 848
 849                 wm_hubs_vmid_ena(codec);
 850
 851                 switch (wm8994->vmid_mode) {
 852                 default:
 853                         WARN_ON(NULL == "Invalid VMID mode");
 854                 case WM8994_VMID_NORMAL:
 855                         /* Startup bias, VMID ramp & buffer */
 856                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 857                                             WM8994_BIAS_SRC |
 858                                             WM8994_VMID_DISCH |
 859                                             WM8994_STARTUP_BIAS_ENA |
 860                                             WM8994_VMID_BUF_ENA |
 861                                             WM8994_VMID_RAMP_MASK,
 862                                             WM8994_BIAS_SRC |
 863                                             WM8994_STARTUP_BIAS_ENA |
 864                                             WM8994_VMID_BUF_ENA |
 865                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 866
 867                         /* Main bias enable, VMID=2x40k */
 868                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 869                                             WM8994_BIAS_ENA |
 870                                             WM8994_VMID_SEL_MASK,
 871                                             WM8994_BIAS_ENA | 0x2);
 872
 873                         msleep(300);
 874
 875                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 876                                             WM8994_VMID_RAMP_MASK |
 877                                             WM8994_BIAS_SRC,
 878                                             0);
 879                         break;
 880
 881                 case WM8994_VMID_FORCE:
 882                         /* Startup bias, slow VMID ramp & buffer */
 883                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 884                                             WM8994_BIAS_SRC |
 885                                             WM8994_VMID_DISCH |
 886                                             WM8994_STARTUP_BIAS_ENA |
 887                                             WM8994_VMID_BUF_ENA |
 888                                             WM8994_VMID_RAMP_MASK,
 889                                             WM8994_BIAS_SRC |
 890                                             WM8994_STARTUP_BIAS_ENA |
 891                                             WM8994_VMID_BUF_ENA |
 892                                             (0x2 << WM8994_VMID_RAMP_SHIFT));
 893
 894                         /* Main bias enable, VMID=2x40k */
 895                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 896                                             WM8994_BIAS_ENA |
 897                                             WM8994_VMID_SEL_MASK,
 898                                             WM8994_BIAS_ENA | 0x2);
 899
 900                         msleep(400);
 901
 902                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 903                                             WM8994_VMID_RAMP_MASK |
 904                                             WM8994_BIAS_SRC,
 905                                             0);
 906                         break;
 907                 }
 908         }
 909 }
 910
 911 static void vmid_dereference(struct snd_soc_codec *codec)
 912 {
 913         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 914
 915         wm8994->vmid_refcount--;
 916
 917         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 918                 wm8994->vmid_refcount);
 919
 920         if (wm8994->vmid_refcount == 0) {
 921                 if (wm8994->hubs.lineout1_se)
 922                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 923                                             WM8994_LINEOUT1N_ENA |
 924                                             WM8994_LINEOUT1P_ENA,
 925                                             WM8994_LINEOUT1N_ENA |
 926                                             WM8994_LINEOUT1P_ENA);
 927
 928                 if (wm8994->hubs.lineout2_se)
 929                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 930                                             WM8994_LINEOUT2N_ENA |
 931                                             WM8994_LINEOUT2P_ENA,
 932                                             WM8994_LINEOUT2N_ENA |
 933                                             WM8994_LINEOUT2P_ENA);
 934
 935                 /* Start discharging VMID */
 936                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 937                                     WM8994_BIAS_SRC |
 938                                     WM8994_VMID_DISCH,
 939                                     WM8994_BIAS_SRC |
 940                                     WM8994_VMID_DISCH);
 941
 942                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 943                                     WM8994_VMID_SEL_MASK, 0);
 944
 945                 msleep(400);
 946
 947                 /* Active discharge */
 948                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 949                                     WM8994_LINEOUT1_DISCH |
 950                                     WM8994_LINEOUT2_DISCH,
 951                                     WM8994_LINEOUT1_DISCH |
 952                                     WM8994_LINEOUT2_DISCH);
 953
 954                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
 955                                     WM8994_LINEOUT1N_ENA |
 956                                     WM8994_LINEOUT1P_ENA |
 957                                     WM8994_LINEOUT2N_ENA |
 958                                     WM8994_LINEOUT2P_ENA, 0);
 959
 960                 /* Switch off startup biases */
 961                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 962                                     WM8994_BIAS_SRC |
 963                                     WM8994_STARTUP_BIAS_ENA |
 964                                     WM8994_VMID_BUF_ENA |
 965                                     WM8994_VMID_RAMP_MASK, 0);
 966
 967                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 968                                     WM8994_VMID_SEL_MASK, 0);
 969         }
 970
 971         pm_runtime_put(codec->dev);
 972 }
 973
 974 static int vmid_event(struct snd_soc_dapm_widget *w,
 975                       struct snd_kcontrol *kcontrol, int event)
 976 {
 977         struct snd_soc_codec *codec = w->codec;
 978
 979         switch (event) {
 980         case SND_SOC_DAPM_PRE_PMU:
 981                 vmid_reference(codec);
 982                 break;
 983
 984         case SND_SOC_DAPM_POST_PMD:
 985                 vmid_dereference(codec);
 986                 break;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
 993 {
 994         int source = 0;  /* GCC flow analysis can't track enable */
 995         int reg, reg_r;
 996
 997         /* We also need the same AIF source for L/R and only one path */
 998         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 999         switch (reg) {
1000         case WM8994_AIF2DACL_TO_DAC1L:
1001                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1002                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003                 break;
1004         case WM8994_AIF1DAC2L_TO_DAC1L:
1005                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1006                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007                 break;
1008         case WM8994_AIF1DAC1L_TO_DAC1L:
1009                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1010                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011                 break;
1012         default:
1013                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1014                 return false;
1015         }
1016
1017         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018         if (reg_r != reg) {
1019                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1020                 return false;
1021         }
1022
1023         /* Set the source up */
1024         snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025                             WM8994_CP_DYN_SRC_SEL_MASK, source);
1026
1027         return true;
1028 }
1029
1030 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031                       struct snd_kcontrol *kcontrol, int event)
1032 {
1033         struct snd_soc_codec *codec = w->codec;
1034         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1035         struct wm8994 *control = codec->control_data;
1036         int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1037         int i;
1038         int dac;
1039         int adc;
1040         int val;
1041
1042         switch (control->type) {
1043         case WM8994:
1044         case WM8958:
1045                 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1046                 break;
1047         default:
1048                 break;
1049         }
1050
1051         switch (event) {
1052         case SND_SOC_DAPM_PRE_PMU:
1053                 /* Don't enable timeslot 2 if not in use */
1054                 if (wm8994->channels[0] <= 2)
1055                         mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1056
1057                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1058                 if ((val & WM8994_AIF1ADCL_SRC) &&
1059                     (val & WM8994_AIF1ADCR_SRC))
1060                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1061                 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1062                          !(val & WM8994_AIF1ADCR_SRC))
1063                         adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1064                 else
1065                         adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1066                                 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1067
1068                 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1069                 if ((val & WM8994_AIF1DACL_SRC) &&
1070                     (val & WM8994_AIF1DACR_SRC))
1071                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1072                 else if (!(val & WM8994_AIF1DACL_SRC) &&
1073                          !(val & WM8994_AIF1DACR_SRC))
1074                         dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1075                 else
1076                         dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1077                                 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1078
1079                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080                                     mask, adc);
1081                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1082                                     mask, dac);
1083                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1084                                     WM8994_AIF1DSPCLK_ENA |
1085                                     WM8994_SYSDSPCLK_ENA,
1086                                     WM8994_AIF1DSPCLK_ENA |
1087                                     WM8994_SYSDSPCLK_ENA);
1088                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1089                                     WM8994_AIF1ADC1R_ENA |
1090                                     WM8994_AIF1ADC1L_ENA |
1091                                     WM8994_AIF1ADC2R_ENA |
1092                                     WM8994_AIF1ADC2L_ENA);
1093                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1094                                     WM8994_AIF1DAC1R_ENA |
1095                                     WM8994_AIF1DAC1L_ENA |
1096                                     WM8994_AIF1DAC2R_ENA |
1097                                     WM8994_AIF1DAC2L_ENA);
1098                 break;
1099
1100         case SND_SOC_DAPM_POST_PMU:
1101                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1102                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1103                                       snd_soc_read(codec,
1104                                                    wm8994_vu_bits[i].reg));
1105                 break;
1106
1107         case SND_SOC_DAPM_PRE_PMD:
1108         case SND_SOC_DAPM_POST_PMD:
1109                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1110                                     mask, 0);
1111                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1112                                     mask, 0);
1113
1114                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1115                 if (val & WM8994_AIF2DSPCLK_ENA)
1116                         val = WM8994_SYSDSPCLK_ENA;
1117                 else
1118                         val = 0;
1119                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1120                                     WM8994_SYSDSPCLK_ENA |
1121                                     WM8994_AIF1DSPCLK_ENA, val);
1122                 break;
1123         }
1124
1125         return 0;
1126 }
1127
1128 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1129                       struct snd_kcontrol *kcontrol, int event)
1130 {
1131         struct snd_soc_codec *codec = w->codec;
1132         int i;
1133         int dac;
1134         int adc;
1135         int val;
1136
1137         switch (event) {
1138         case SND_SOC_DAPM_PRE_PMU:
1139                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1140                 if ((val & WM8994_AIF2ADCL_SRC) &&
1141                     (val & WM8994_AIF2ADCR_SRC))
1142                         adc = WM8994_AIF2ADCR_ENA;
1143                 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1144                          !(val & WM8994_AIF2ADCR_SRC))
1145                         adc = WM8994_AIF2ADCL_ENA;
1146                 else
1147                         adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1148
1149
1150                 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1151                 if ((val & WM8994_AIF2DACL_SRC) &&
1152                     (val & WM8994_AIF2DACR_SRC))
1153                         dac = WM8994_AIF2DACR_ENA;
1154                 else if (!(val & WM8994_AIF2DACL_SRC) &&
1155                          !(val & WM8994_AIF2DACR_SRC))
1156                         dac = WM8994_AIF2DACL_ENA;
1157                 else
1158                         dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1159
1160                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1161                                     WM8994_AIF2ADCL_ENA |
1162                                     WM8994_AIF2ADCR_ENA, adc);
1163                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1164                                     WM8994_AIF2DACL_ENA |
1165                                     WM8994_AIF2DACR_ENA, dac);
1166                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1167                                     WM8994_AIF2DSPCLK_ENA |
1168                                     WM8994_SYSDSPCLK_ENA,
1169                                     WM8994_AIF2DSPCLK_ENA |
1170                                     WM8994_SYSDSPCLK_ENA);
1171                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1172                                     WM8994_AIF2ADCL_ENA |
1173                                     WM8994_AIF2ADCR_ENA,
1174                                     WM8994_AIF2ADCL_ENA |
1175                                     WM8994_AIF2ADCR_ENA);
1176                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1177                                     WM8994_AIF2DACL_ENA |
1178                                     WM8994_AIF2DACR_ENA,
1179                                     WM8994_AIF2DACL_ENA |
1180                                     WM8994_AIF2DACR_ENA);
1181                 break;
1182
1183         case SND_SOC_DAPM_POST_PMU:
1184                 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1185                         snd_soc_write(codec, wm8994_vu_bits[i].reg,
1186                                       snd_soc_read(codec,
1187                                                    wm8994_vu_bits[i].reg));
1188                 break;
1189
1190         case SND_SOC_DAPM_PRE_PMD:
1191         case SND_SOC_DAPM_POST_PMD:
1192                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1193                                     WM8994_AIF2DACL_ENA |
1194                                     WM8994_AIF2DACR_ENA, 0);
1195                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1196                                     WM8994_AIF2ADCL_ENA |
1197                                     WM8994_AIF2ADCR_ENA, 0);
1198
1199                 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1200                 if (val & WM8994_AIF1DSPCLK_ENA)
1201                         val = WM8994_SYSDSPCLK_ENA;
1202                 else
1203                         val = 0;
1204                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1205                                     WM8994_SYSDSPCLK_ENA |
1206                                     WM8994_AIF2DSPCLK_ENA, val);
1207                 break;
1208         }
1209
1210         return 0;
1211 }
1212
1213 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1214                            struct snd_kcontrol *kcontrol, int event)
1215 {
1216         struct snd_soc_codec *codec = w->codec;
1217         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1218
1219         switch (event) {
1220         case SND_SOC_DAPM_PRE_PMU:
1221                 wm8994->aif1clk_enable = 1;
1222                 break;
1223         case SND_SOC_DAPM_POST_PMD:
1224                 wm8994->aif1clk_disable = 1;
1225                 break;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1232                            struct snd_kcontrol *kcontrol, int event)
1233 {
1234         struct snd_soc_codec *codec = w->codec;
1235         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1236
1237         switch (event) {
1238         case SND_SOC_DAPM_PRE_PMU:
1239                 wm8994->aif2clk_enable = 1;
1240                 break;
1241         case SND_SOC_DAPM_POST_PMD:
1242                 wm8994->aif2clk_disable = 1;
1243                 break;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1250                           struct snd_kcontrol *kcontrol, int event)
1251 {
1252         struct snd_soc_codec *codec = w->codec;
1253         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1254
1255         switch (event) {
1256         case SND_SOC_DAPM_PRE_PMU:
1257                 if (wm8994->aif1clk_enable) {
1258                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1259                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1260                                             WM8994_AIF1CLK_ENA_MASK,
1261                                             WM8994_AIF1CLK_ENA);
1262                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1263                         wm8994->aif1clk_enable = 0;
1264                 }
1265                 if (wm8994->aif2clk_enable) {
1266                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1267                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1268                                             WM8994_AIF2CLK_ENA_MASK,
1269                                             WM8994_AIF2CLK_ENA);
1270                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1271                         wm8994->aif2clk_enable = 0;
1272                 }
1273                 break;
1274         }
1275
1276         /* We may also have postponed startup of DSP, handle that. */
1277         wm8958_aif_ev(w, kcontrol, event);
1278
1279         return 0;
1280 }
1281
1282 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1283                            struct snd_kcontrol *kcontrol, int event)
1284 {
1285         struct snd_soc_codec *codec = w->codec;
1286         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1287
1288         switch (event) {
1289         case SND_SOC_DAPM_POST_PMD:
1290                 if (wm8994->aif1clk_disable) {
1291                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1292                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1293                                             WM8994_AIF1CLK_ENA_MASK, 0);
1294                         aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1295                         wm8994->aif1clk_disable = 0;
1296                 }
1297                 if (wm8994->aif2clk_disable) {
1298                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1299                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1300                                             WM8994_AIF2CLK_ENA_MASK, 0);
1301                         aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1302                         wm8994->aif2clk_disable = 0;
1303                 }
1304                 break;
1305         }
1306
1307         return 0;
1308 }
1309
1310 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1311                       struct snd_kcontrol *kcontrol, int event)
1312 {
1313         late_enable_ev(w, kcontrol, event);
1314         return 0;
1315 }
1316
1317 static int micbias_ev(struct snd_soc_dapm_widget *w,
1318                       struct snd_kcontrol *kcontrol, int event)
1319 {
1320         late_enable_ev(w, kcontrol, event);
1321         return 0;
1322 }
1323
1324 static int dac_ev(struct snd_soc_dapm_widget *w,
1325                   struct snd_kcontrol *kcontrol, int event)
1326 {
1327         struct snd_soc_codec *codec = w->codec;
1328         unsigned int mask = 1 << w->shift;
1329
1330         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1331                             mask, mask);
1332         return 0;
1333 }
1334
1335 static const char *adc_mux_text[] = {
1336         "ADC",
1337         "DMIC",
1338 };
1339
1340 static const struct soc_enum adc_enum =
1341         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1342
1343 static const struct snd_kcontrol_new adcl_mux =
1344         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1345
1346 static const struct snd_kcontrol_new adcr_mux =
1347         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1348
1349 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1350 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1351 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1352 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1353 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1354 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1355 };
1356
1357 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1358 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1359 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1360 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1361 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1362 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1363 };
1364
1365 /* Debugging; dump chip status after DAPM transitions */
1366 static int post_ev(struct snd_soc_dapm_widget *w,
1367             struct snd_kcontrol *kcontrol, int event)
1368 {
1369         struct snd_soc_codec *codec = w->codec;
1370         dev_dbg(codec->dev, "SRC status: %x\n",
1371                 snd_soc_read(codec,
1372                              WM8994_RATE_STATUS));
1373         return 0;
1374 }
1375
1376 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1377 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1378                 1, 1, 0),
1379 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1380                 0, 1, 0),
1381 };
1382
1383 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1384 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1385                 1, 1, 0),
1386 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1387                 0, 1, 0),
1388 };
1389
1390 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1391 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1392                 1, 1, 0),
1393 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1394                 0, 1, 0),
1395 };
1396
1397 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1398 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1399                 1, 1, 0),
1400 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1401                 0, 1, 0),
1402 };
1403
1404 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1405 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1406                 5, 1, 0),
1407 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408                 4, 1, 0),
1409 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410                 2, 1, 0),
1411 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412                 1, 1, 0),
1413 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414                 0, 1, 0),
1415 };
1416
1417 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1418 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1419                 5, 1, 0),
1420 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421                 4, 1, 0),
1422 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423                 2, 1, 0),
1424 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425                 1, 1, 0),
1426 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427                 0, 1, 0),
1428 };
1429
1430 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1431 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1432         .info = snd_soc_info_volsw, \
1433         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1434         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1435
1436 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1437                               struct snd_ctl_elem_value *ucontrol)
1438 {
1439         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1440         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1441         struct snd_soc_codec *codec = w->codec;
1442         int ret;
1443
1444         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
1446         wm_hubs_update_class_w(codec);
1447
1448         return ret;
1449 }
1450
1451 static const struct snd_kcontrol_new dac1l_mix[] = {
1452 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453                       5, 1, 0),
1454 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455                       4, 1, 0),
1456 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457                       2, 1, 0),
1458 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459                       1, 1, 0),
1460 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461                       0, 1, 0),
1462 };
1463
1464 static const struct snd_kcontrol_new dac1r_mix[] = {
1465 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466                       5, 1, 0),
1467 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468                       4, 1, 0),
1469 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470                       2, 1, 0),
1471 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472                       1, 1, 0),
1473 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474                       0, 1, 0),
1475 };
1476
1477 static const char *sidetone_text[] = {
1478         "ADC/DMIC1", "DMIC2",
1479 };
1480
1481 static const struct soc_enum sidetone1_enum =
1482         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484 static const struct snd_kcontrol_new sidetone1_mux =
1485         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487 static const struct soc_enum sidetone2_enum =
1488         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490 static const struct snd_kcontrol_new sidetone2_mux =
1491         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493 static const char *aif1dac_text[] = {
1494         "AIF1DACDAT", "AIF3DACDAT",
1495 };
1496
1497 static const struct soc_enum aif1dac_enum =
1498         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1499
1500 static const struct snd_kcontrol_new aif1dac_mux =
1501         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1502
1503 static const char *aif2dac_text[] = {
1504         "AIF2DACDAT", "AIF3DACDAT",
1505 };
1506
1507 static const struct soc_enum aif2dac_enum =
1508         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1509
1510 static const struct snd_kcontrol_new aif2dac_mux =
1511         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1512
1513 static const char *aif2adc_text[] = {
1514         "AIF2ADCDAT", "AIF3DACDAT",
1515 };
1516
1517 static const struct soc_enum aif2adc_enum =
1518         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1519
1520 static const struct snd_kcontrol_new aif2adc_mux =
1521         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1522
1523 static const char *aif3adc_text[] = {
1524         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1525 };
1526
1527 static const struct soc_enum wm8994_aif3adc_enum =
1528         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1529
1530 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1531         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1532
1533 static const struct soc_enum wm8958_aif3adc_enum =
1534         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1535
1536 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1537         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1538
1539 static const char *mono_pcm_out_text[] = {
1540         "None", "AIF2ADCL", "AIF2ADCR",
1541 };
1542
1543 static const struct soc_enum mono_pcm_out_enum =
1544         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1545
1546 static const struct snd_kcontrol_new mono_pcm_out_mux =
1547         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1548
1549 static const char *aif2dac_src_text[] = {
1550         "AIF2", "AIF3",
1551 };
1552
1553 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1554 static const struct soc_enum aif2dacl_src_enum =
1555         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1556
1557 static const struct snd_kcontrol_new aif2dacl_src_mux =
1558         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1559
1560 static const struct soc_enum aif2dacr_src_enum =
1561         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1562
1563 static const struct snd_kcontrol_new aif2dacr_src_mux =
1564         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1565
1566 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1567 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1568         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1569 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1570         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1571
1572 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1573         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1574 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1575         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1577         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1579         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1581         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1582
1583 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1584                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1585                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1587                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1588                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1589 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1590                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1591 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1592                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1593
1594 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1595 };
1596
1597 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1598 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1599                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1600                     SND_SOC_DAPM_PRE_PMD),
1601 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1602                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1603                     SND_SOC_DAPM_PRE_PMD),
1604 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1605 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1607 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1608                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1609 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1610 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1611 };
1612
1613 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1614 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1615         dac_ev, SND_SOC_DAPM_PRE_PMU),
1616 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1617         dac_ev, SND_SOC_DAPM_PRE_PMU),
1618 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1619         dac_ev, SND_SOC_DAPM_PRE_PMU),
1620 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1621         dac_ev, SND_SOC_DAPM_PRE_PMU),
1622 };
1623
1624 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1625 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1626 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1627 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1628 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1629 };
1630
1631 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1632 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1633                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1635                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1636 };
1637
1638 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1639 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1640 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1641 };
1642
1643 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1644 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1645 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1646 SND_SOC_DAPM_INPUT("Clock"),
1647
1648 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1649                       SND_SOC_DAPM_PRE_PMU),
1650 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1651                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1652
1653 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1654                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1655                     SND_SOC_DAPM_PRE_PMD),
1656
1657 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1658 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1659 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1660
1661 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1662                      0, SND_SOC_NOPM, 9, 0),
1663 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1664                      0, SND_SOC_NOPM, 8, 0),
1665 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1666                       SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1667                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1668 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1669                       SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1670                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1671
1672 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1673                      0, SND_SOC_NOPM, 11, 0),
1674 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1675                      0, SND_SOC_NOPM, 10, 0),
1676 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1677                       SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1678                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1679 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1680                       SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1681                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1682
1683 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1684                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1685 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1686                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1687
1688 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1689                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1690 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1691                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1692
1693 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1694                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1695 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1696                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1697
1698 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1699 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1700
1701 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1702                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1703 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1704                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1705
1706 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1707                      SND_SOC_NOPM, 13, 0),
1708 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1709                      SND_SOC_NOPM, 12, 0),
1710 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1711                       SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1712                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1713 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1714                       SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1715                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1716
1717 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1720 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT",  NULL, 0, SND_SOC_NOPM, 0, 0),
1721
1722 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1723 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1724 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1725
1726 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1727 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1728
1729 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1730
1731 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1732 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1733 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1734 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1735
1736 /* Power is done with the muxes since the ADC power also controls the
1737  * downsampling chain, the chip will automatically manage the analogue
1738  * specific portions.
1739  */
1740 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1741 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1742
1743 SND_SOC_DAPM_POST("Debug log", post_ev),
1744 };
1745
1746 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1747 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1748 };
1749
1750 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1751 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1752 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1753 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1754 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1755 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1756 };
1757
1758 static const struct snd_soc_dapm_route intercon[] = {
1759         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1760         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1761
1762         { "DSP1CLK", NULL, "CLK_SYS" },
1763         { "DSP2CLK", NULL, "CLK_SYS" },
1764         { "DSPINTCLK", NULL, "CLK_SYS" },
1765
1766         { "AIF1ADC1L", NULL, "AIF1CLK" },
1767         { "AIF1ADC1L", NULL, "DSP1CLK" },
1768         { "AIF1ADC1R", NULL, "AIF1CLK" },
1769         { "AIF1ADC1R", NULL, "DSP1CLK" },
1770         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1771
1772         { "AIF1DAC1L", NULL, "AIF1CLK" },
1773         { "AIF1DAC1L", NULL, "DSP1CLK" },
1774         { "AIF1DAC1R", NULL, "AIF1CLK" },
1775         { "AIF1DAC1R", NULL, "DSP1CLK" },
1776         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1777
1778         { "AIF1ADC2L", NULL, "AIF1CLK" },
1779         { "AIF1ADC2L", NULL, "DSP1CLK" },
1780         { "AIF1ADC2R", NULL, "AIF1CLK" },
1781         { "AIF1ADC2R", NULL, "DSP1CLK" },
1782         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1783
1784         { "AIF1DAC2L", NULL, "AIF1CLK" },
1785         { "AIF1DAC2L", NULL, "DSP1CLK" },
1786         { "AIF1DAC2R", NULL, "AIF1CLK" },
1787         { "AIF1DAC2R", NULL, "DSP1CLK" },
1788         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1789
1790         { "AIF2ADCL", NULL, "AIF2CLK" },
1791         { "AIF2ADCL", NULL, "DSP2CLK" },
1792         { "AIF2ADCR", NULL, "AIF2CLK" },
1793         { "AIF2ADCR", NULL, "DSP2CLK" },
1794         { "AIF2ADCR", NULL, "DSPINTCLK" },
1795
1796         { "AIF2DACL", NULL, "AIF2CLK" },
1797         { "AIF2DACL", NULL, "DSP2CLK" },
1798         { "AIF2DACR", NULL, "AIF2CLK" },
1799         { "AIF2DACR", NULL, "DSP2CLK" },
1800         { "AIF2DACR", NULL, "DSPINTCLK" },
1801
1802         { "DMIC1L", NULL, "DMIC1DAT" },
1803         { "DMIC1L", NULL, "CLK_SYS" },
1804         { "DMIC1R", NULL, "DMIC1DAT" },
1805         { "DMIC1R", NULL, "CLK_SYS" },
1806         { "DMIC2L", NULL, "DMIC2DAT" },
1807         { "DMIC2L", NULL, "CLK_SYS" },
1808         { "DMIC2R", NULL, "DMIC2DAT" },
1809         { "DMIC2R", NULL, "CLK_SYS" },
1810
1811         { "ADCL", NULL, "AIF1CLK" },
1812         { "ADCL", NULL, "DSP1CLK" },
1813         { "ADCL", NULL, "DSPINTCLK" },
1814
1815         { "ADCR", NULL, "AIF1CLK" },
1816         { "ADCR", NULL, "DSP1CLK" },
1817         { "ADCR", NULL, "DSPINTCLK" },
1818
1819         { "ADCL Mux", "ADC", "ADCL" },
1820         { "ADCL Mux", "DMIC", "DMIC1L" },
1821         { "ADCR Mux", "ADC", "ADCR" },
1822         { "ADCR Mux", "DMIC", "DMIC1R" },
1823
1824         { "DAC1L", NULL, "AIF1CLK" },
1825         { "DAC1L", NULL, "DSP1CLK" },
1826         { "DAC1L", NULL, "DSPINTCLK" },
1827
1828         { "DAC1R", NULL, "AIF1CLK" },
1829         { "DAC1R", NULL, "DSP1CLK" },
1830         { "DAC1R", NULL, "DSPINTCLK" },
1831
1832         { "DAC2L", NULL, "AIF2CLK" },
1833         { "DAC2L", NULL, "DSP2CLK" },
1834         { "DAC2L", NULL, "DSPINTCLK" },
1835
1836         { "DAC2R", NULL, "AIF2DACR" },
1837         { "DAC2R", NULL, "AIF2CLK" },
1838         { "DAC2R", NULL, "DSP2CLK" },
1839         { "DAC2R", NULL, "DSPINTCLK" },
1840
1841         { "TOCLK", NULL, "CLK_SYS" },
1842
1843         { "AIF1DACDAT", NULL, "AIF1 Playback" },
1844         { "AIF2DACDAT", NULL, "AIF2 Playback" },
1845         { "AIF3DACDAT", NULL, "AIF3 Playback" },
1846
1847         { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1848         { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1849         { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1850
1851         /* AIF1 outputs */
1852         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1853         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1854         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1855
1856         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1857         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1858         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1859
1860         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1861         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1862         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1863
1864         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1865         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1866         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1867
1868         /* Pin level routing for AIF3 */
1869         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1870         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1871         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1872         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1873
1874         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1875         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1876         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1877         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1878         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1879         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1880         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1881
1882         /* DAC1 inputs */
1883         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1885         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1886         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888
1889         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1890         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1891         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1892         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1893         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1894
1895         /* DAC2/AIF2 outputs  */
1896         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1897         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1898         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902
1903         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1904         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1906         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1907         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
1910         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1911         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1912         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1913         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1914
1915         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1916
1917         /* AIF3 output */
1918         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1919         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1920         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1921         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1922         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1923         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1924         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1925         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1926
1927         /* Sidetone */
1928         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1929         { "Left Sidetone", "DMIC2", "DMIC2L" },
1930         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1931         { "Right Sidetone", "DMIC2", "DMIC2R" },
1932
1933         /* Output stages */
1934         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1935         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1936
1937         { "SPKL", "DAC1 Switch", "DAC1L" },
1938         { "SPKL", "DAC2 Switch", "DAC2L" },
1939
1940         { "SPKR", "DAC1 Switch", "DAC1R" },
1941         { "SPKR", "DAC2 Switch", "DAC2R" },
1942
1943         { "Left Headphone Mux", "DAC", "DAC1L" },
1944         { "Right Headphone Mux", "DAC", "DAC1R" },
1945 };
1946
1947 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1948         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1949         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1950         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1951         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1952         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1953         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1954         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1955         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1956 };
1957
1958 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1959         { "DAC1L", NULL, "DAC1L Mixer" },
1960         { "DAC1R", NULL, "DAC1R Mixer" },
1961         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1962         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1963 };
1964
1965 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1966         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1967         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1968         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1969         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1970         { "MICBIAS1", NULL, "CLK_SYS" },
1971         { "MICBIAS1", NULL, "MICBIAS Supply" },
1972         { "MICBIAS2", NULL, "CLK_SYS" },
1973         { "MICBIAS2", NULL, "MICBIAS Supply" },
1974 };
1975
1976 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1977         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1978         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1979         { "MICBIAS1", NULL, "VMID" },
1980         { "MICBIAS2", NULL, "VMID" },
1981 };
1982
1983 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1984         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1985         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1986
1987         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1988         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1989         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1990         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1991
1992         { "AIF3DACDAT", NULL, "AIF3" },
1993         { "AIF3ADCDAT", NULL, "AIF3" },
1994
1995         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1996         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1997
1998         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1999 };
2000
2001 /* The size in bits of the FLL divide multiplied by 10
2002  * to allow rounding later */
2003 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2004
2005 struct fll_div {
2006         u16 outdiv;
2007         u16 n;
2008         u16 k;
2009         u16 clk_ref_div;
2010         u16 fll_fratio;
2011 };
2012
2013 static int wm8994_get_fll_config(struct fll_div *fll,
2014                                  int freq_in, int freq_out)
2015 {
2016         u64 Kpart;
2017         unsigned int K, Ndiv, Nmod;
2018
2019         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2020
2021         /* Scale the input frequency down to <= 13.5MHz */
2022         fll->clk_ref_div = 0;
2023         while (freq_in > 13500000) {
2024                 fll->clk_ref_div++;
2025                 freq_in /= 2;
2026
2027                 if (fll->clk_ref_div > 3)
2028                         return -EINVAL;
2029         }
2030         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2031
2032         /* Scale the output to give 90MHz<=Fvco<=100MHz */
2033         fll->outdiv = 3;
2034         while (freq_out * (fll->outdiv + 1) < 90000000) {
2035                 fll->outdiv++;
2036                 if (fll->outdiv > 63)
2037                         return -EINVAL;
2038         }
2039         freq_out *= fll->outdiv + 1;
2040         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2041
2042         if (freq_in > 1000000) {
2043                 fll->fll_fratio = 0;
2044         } else if (freq_in > 256000) {
2045                 fll->fll_fratio = 1;
2046                 freq_in *= 2;
2047         } else if (freq_in > 128000) {
2048                 fll->fll_fratio = 2;
2049                 freq_in *= 4;
2050         } else if (freq_in > 64000) {
2051                 fll->fll_fratio = 3;
2052                 freq_in *= 8;
2053         } else {
2054                 fll->fll_fratio = 4;
2055                 freq_in *= 16;
2056         }
2057         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2058
2059         /* Now, calculate N.K */
2060         Ndiv = freq_out / freq_in;
2061
2062         fll->n = Ndiv;
2063         Nmod = freq_out % freq_in;
2064         pr_debug("Nmod=%d\n", Nmod);
2065
2066         /* Calculate fractional part - scale up so we can round. */
2067         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2068
2069         do_div(Kpart, freq_in);
2070
2071         K = Kpart & 0xFFFFFFFF;
2072
2073         if ((K % 10) >= 5)
2074                 K += 5;
2075
2076         /* Move down to proper range now rounding is done */
2077         fll->k = K / 10;
2078
2079         pr_debug("N=%x K=%x\n", fll->n, fll->k);
2080
2081         return 0;
2082 }
2083
2084 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2085                           unsigned int freq_in, unsigned int freq_out)
2086 {
2087         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2088         struct wm8994 *control = wm8994->wm8994;
2089         int reg_offset, ret;
2090         struct fll_div fll;
2091         u16 reg, clk1, aif_reg, aif_src;
2092         unsigned long timeout;
2093         bool was_enabled;
2094
2095         switch (id) {
2096         case WM8994_FLL1:
2097                 reg_offset = 0;
2098                 id = 0;
2099                 aif_src = 0x10;
2100                 break;
2101         case WM8994_FLL2:
2102                 reg_offset = 0x20;
2103                 id = 1;
2104                 aif_src = 0x18;
2105                 break;
2106         default:
2107                 return -EINVAL;
2108         }
2109
2110         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2111         was_enabled = reg & WM8994_FLL1_ENA;
2112
2113         switch (src) {
2114         case 0:
2115                 /* Allow no source specification when stopping */
2116                 if (freq_out)
2117                         return -EINVAL;
2118                 src = wm8994->fll[id].src;
2119                 break;
2120         case WM8994_FLL_SRC_MCLK1:
2121         case WM8994_FLL_SRC_MCLK2:
2122         case WM8994_FLL_SRC_LRCLK:
2123         case WM8994_FLL_SRC_BCLK:
2124                 break;
2125         case WM8994_FLL_SRC_INTERNAL:
2126                 freq_in = 12000000;
2127                 freq_out = 12000000;
2128                 break;
2129         default:
2130                 return -EINVAL;
2131         }
2132
2133         /* Are we changing anything? */
2134         if (wm8994->fll[id].src == src &&
2135             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2136                 return 0;
2137
2138         /* If we're stopping the FLL redo the old config - no
2139          * registers will actually be written but we avoid GCC flow
2140          * analysis bugs spewing warnings.
2141          */
2142         if (freq_out)
2143                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2144         else
2145                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2146                                             wm8994->fll[id].out);
2147         if (ret < 0)
2148                 return ret;
2149
2150         /* Make sure that we're not providing SYSCLK right now */
2151         clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2152         if (clk1 & WM8994_SYSCLK_SRC)
2153                 aif_reg = WM8994_AIF2_CLOCKING_1;
2154         else
2155                 aif_reg = WM8994_AIF1_CLOCKING_1;
2156         reg = snd_soc_read(codec, aif_reg);
2157
2158         if ((reg & WM8994_AIF1CLK_ENA) &&
2159             (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2160                 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2161                         id + 1);
2162                 return -EBUSY;
2163         }
2164
2165         /* We always need to disable the FLL while reconfiguring */
2166         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2167                             WM8994_FLL1_ENA, 0);
2168
2169         if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2170             freq_in == freq_out && freq_out) {
2171                 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2172                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2173                                     WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2174                 goto out;
2175         }
2176
2177         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2178                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2179         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2180                             WM8994_FLL1_OUTDIV_MASK |
2181                             WM8994_FLL1_FRATIO_MASK, reg);
2182
2183         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2184                             WM8994_FLL1_K_MASK, fll.k);
2185
2186         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2187                             WM8994_FLL1_N_MASK,
2188                             fll.n << WM8994_FLL1_N_SHIFT);
2189
2190         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2191                             WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2192                             WM8994_FLL1_REFCLK_DIV_MASK |
2193                             WM8994_FLL1_REFCLK_SRC_MASK,
2194                             ((src == WM8994_FLL_SRC_INTERNAL)
2195                              << WM8994_FLL1_FRC_NCO_SHIFT) |
2196                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2197                             (src - 1));
2198
2199         /* Clear any pending completion from a previous failure */
2200         try_wait_for_completion(&wm8994->fll_locked[id]);
2201
2202         /* Enable (with fractional mode if required) */
2203         if (freq_out) {
2204                 /* Enable VMID if we need it */
2205                 if (!was_enabled) {
2206                         active_reference(codec);
2207
2208                         switch (control->type) {
2209                         case WM8994:
2210                                 vmid_reference(codec);
2211                                 break;
2212                         case WM8958:
2213                                 if (wm8994->revision < 1)
2214                                         vmid_reference(codec);
2215                                 break;
2216                         default:
2217                                 break;
2218                         }
2219                 }
2220
2221                 reg = WM8994_FLL1_ENA;
2222
2223                 if (fll.k)
2224                         reg |= WM8994_FLL1_FRAC;
2225                 if (src == WM8994_FLL_SRC_INTERNAL)
2226                         reg |= WM8994_FLL1_OSC_ENA;
2227
2228                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2229                                     WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2230                                     WM8994_FLL1_FRAC, reg);
2231
2232                 if (wm8994->fll_locked_irq) {
2233                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2234                                                               msecs_to_jiffies(10));
2235                         if (timeout == 0)
2236                                 dev_warn(codec->dev,
2237                                          "Timed out waiting for FLL lock\n");
2238                 } else {
2239                         msleep(5);
2240                 }
2241         } else {
2242                 if (was_enabled) {
2243                         switch (control->type) {
2244                         case WM8994:
2245                                 vmid_dereference(codec);
2246                                 break;
2247                         case WM8958:
2248                                 if (wm8994->revision < 1)
2249                                         vmid_dereference(codec);
2250                                 break;
2251                         default:
2252                                 break;
2253                         }
2254
2255                         active_dereference(codec);
2256                 }
2257         }
2258
2259 out:
2260         wm8994->fll[id].in = freq_in;
2261         wm8994->fll[id].out = freq_out;
2262         wm8994->fll[id].src = src;
2263
2264         configure_clock(codec);
2265
2266         return 0;
2267 }
2268
2269 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2270 {
2271         struct completion *completion = data;
2272
2273         complete(completion);
2274
2275         return IRQ_HANDLED;
2276 }
2277
2278 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2279
2280 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2281                           unsigned int freq_in, unsigned int freq_out)
2282 {
2283         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2284 }
2285
2286 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2287                 int clk_id, unsigned int freq, int dir)
2288 {
2289         struct snd_soc_codec *codec = dai->codec;
2290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2291         int i;
2292
2293         switch (dai->id) {
2294         case 1:
2295         case 2:
2296                 break;
2297
2298         default:
2299                 /* AIF3 shares clocking with AIF1/2 */
2300                 return -EINVAL;
2301         }
2302
2303         switch (clk_id) {
2304         case WM8994_SYSCLK_MCLK1:
2305                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2306                 wm8994->mclk[0] = freq;
2307                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2308                         dai->id, freq);
2309                 break;
2310
2311         case WM8994_SYSCLK_MCLK2:
2312                 /* TODO: Set GPIO AF */
2313                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2314                 wm8994->mclk[1] = freq;
2315                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2316                         dai->id, freq);
2317                 break;
2318
2319         case WM8994_SYSCLK_FLL1:
2320                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2321                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2322                 break;
2323
2324         case WM8994_SYSCLK_FLL2:
2325                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2326                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2327                 break;
2328
2329         case WM8994_SYSCLK_OPCLK:
2330                 /* Special case - a division (times 10) is given and
2331                  * no effect on main clocking.
2332                  */
2333                 if (freq) {
2334                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2335                                 if (opclk_divs[i] == freq)
2336                                         break;
2337                         if (i == ARRAY_SIZE(opclk_divs))
2338                                 return -EINVAL;
2339                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2340                                             WM8994_OPCLK_DIV_MASK, i);
2341                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2342                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2343                 } else {
2344                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2345                                             WM8994_OPCLK_ENA, 0);
2346                 }
2347
2348         default:
2349                 return -EINVAL;
2350         }
2351
2352         configure_clock(codec);
2353
2354         return 0;
2355 }
2356
2357 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2358                                  enum snd_soc_bias_level level)
2359 {
2360         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2361         struct wm8994 *control = wm8994->wm8994;
2362
2363         wm_hubs_set_bias_level(codec, level);
2364
2365         switch (level) {
2366         case SND_SOC_BIAS_ON:
2367                 break;
2368
2369         case SND_SOC_BIAS_PREPARE:
2370                 /* MICBIAS into regulating mode */
2371                 switch (control->type) {
2372                 case WM8958:
2373                 case WM1811:
2374                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2375                                             WM8958_MICB1_MODE, 0);
2376                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2377                                             WM8958_MICB2_MODE, 0);
2378                         break;
2379                 default:
2380                         break;
2381                 }
2382
2383                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2384                         active_reference(codec);
2385                 break;
2386
2387         case SND_SOC_BIAS_STANDBY:
2388                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2389                         switch (control->type) {
2390                         case WM8958:
2391                                 if (wm8994->revision == 0) {
2392                                         /* Optimise performance for rev A */
2393                                         snd_soc_update_bits(codec,
2394                                                             WM8958_CHARGE_PUMP_2,
2395                                                             WM8958_CP_DISCH,
2396                                                             WM8958_CP_DISCH);
2397                                 }
2398                                 break;
2399
2400                         default:
2401                                 break;
2402                         }
2403
2404                         /* Discharge LINEOUT1 & 2 */
2405                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2406                                             WM8994_LINEOUT1_DISCH |
2407                                             WM8994_LINEOUT2_DISCH,
2408                                             WM8994_LINEOUT1_DISCH |
2409                                             WM8994_LINEOUT2_DISCH);
2410                 }
2411
2412                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2413                         active_dereference(codec);
2414
2415                 /* MICBIAS into bypass mode on newer devices */
2416                 switch (control->type) {
2417                 case WM8958:
2418                 case WM1811:
2419                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2420                                             WM8958_MICB1_MODE,
2421                                             WM8958_MICB1_MODE);
2422                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2423                                             WM8958_MICB2_MODE,
2424                                             WM8958_MICB2_MODE);
2425                         break;
2426                 default:
2427                         break;
2428                 }
2429                 break;
2430
2431         case SND_SOC_BIAS_OFF:
2432                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2433                         wm8994->cur_fw = NULL;
2434                 break;
2435         }
2436
2437         codec->dapm.bias_level = level;
2438
2439         return 0;
2440 }
2441
2442 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2443 {
2444         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2445
2446         switch (mode) {
2447         case WM8994_VMID_NORMAL:
2448                 if (wm8994->hubs.lineout1_se) {
2449                         snd_soc_dapm_disable_pin(&codec->dapm,
2450                                                  "LINEOUT1N Driver");
2451                         snd_soc_dapm_disable_pin(&codec->dapm,
2452                                                  "LINEOUT1P Driver");
2453                 }
2454                 if (wm8994->hubs.lineout2_se) {
2455                         snd_soc_dapm_disable_pin(&codec->dapm,
2456                                                  "LINEOUT2N Driver");
2457                         snd_soc_dapm_disable_pin(&codec->dapm,
2458                                                  "LINEOUT2P Driver");
2459                 }
2460
2461                 /* Do the sync with the old mode to allow it to clean up */
2462                 snd_soc_dapm_sync(&codec->dapm);
2463                 wm8994->vmid_mode = mode;
2464                 break;
2465
2466         case WM8994_VMID_FORCE:
2467                 if (wm8994->hubs.lineout1_se) {
2468                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2469                                                       "LINEOUT1N Driver");
2470                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2471                                                       "LINEOUT1P Driver");
2472                 }
2473                 if (wm8994->hubs.lineout2_se) {
2474                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2475                                                       "LINEOUT2N Driver");
2476                         snd_soc_dapm_force_enable_pin(&codec->dapm,
2477                                                       "LINEOUT2P Driver");
2478                 }
2479
2480                 wm8994->vmid_mode = mode;
2481                 snd_soc_dapm_sync(&codec->dapm);
2482                 break;
2483
2484         default:
2485                 return -EINVAL;
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2492 {
2493         struct snd_soc_codec *codec = dai->codec;
2494         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2495         struct wm8994 *control = wm8994->wm8994;
2496         int ms_reg;
2497         int aif1_reg;
2498         int ms = 0;
2499         int aif1 = 0;
2500
2501         switch (dai->id) {
2502         case 1:
2503                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2504                 aif1_reg = WM8994_AIF1_CONTROL_1;
2505                 break;
2506         case 2:
2507                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2508                 aif1_reg = WM8994_AIF2_CONTROL_1;
2509                 break;
2510         default:
2511                 return -EINVAL;
2512         }
2513
2514         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2515         case SND_SOC_DAIFMT_CBS_CFS:
2516                 break;
2517         case SND_SOC_DAIFMT_CBM_CFM:
2518                 ms = WM8994_AIF1_MSTR;
2519                 break;
2520         default:
2521                 return -EINVAL;
2522         }
2523
2524         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2525         case SND_SOC_DAIFMT_DSP_B:
2526                 aif1 |= WM8994_AIF1_LRCLK_INV;
2527         case SND_SOC_DAIFMT_DSP_A:
2528                 aif1 |= 0x18;
2529                 break;
2530         case SND_SOC_DAIFMT_I2S:
2531                 aif1 |= 0x10;
2532                 break;
2533         case SND_SOC_DAIFMT_RIGHT_J:
2534                 break;
2535         case SND_SOC_DAIFMT_LEFT_J:
2536                 aif1 |= 0x8;
2537                 break;
2538         default:
2539                 return -EINVAL;
2540         }
2541
2542         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2543         case SND_SOC_DAIFMT_DSP_A:
2544         case SND_SOC_DAIFMT_DSP_B:
2545                 /* frame inversion not valid for DSP modes */
2546                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2547                 case SND_SOC_DAIFMT_NB_NF:
2548                         break;
2549                 case SND_SOC_DAIFMT_IB_NF:
2550                         aif1 |= WM8994_AIF1_BCLK_INV;
2551                         break;
2552                 default:
2553                         return -EINVAL;
2554                 }
2555                 break;
2556
2557         case SND_SOC_DAIFMT_I2S:
2558         case SND_SOC_DAIFMT_RIGHT_J:
2559         case SND_SOC_DAIFMT_LEFT_J:
2560                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2561                 case SND_SOC_DAIFMT_NB_NF:
2562                         break;
2563                 case SND_SOC_DAIFMT_IB_IF:
2564                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2565                         break;
2566                 case SND_SOC_DAIFMT_IB_NF:
2567                         aif1 |= WM8994_AIF1_BCLK_INV;
2568                         break;
2569                 case SND_SOC_DAIFMT_NB_IF:
2570                         aif1 |= WM8994_AIF1_LRCLK_INV;
2571                         break;
2572                 default:
2573                         return -EINVAL;
2574                 }
2575                 break;
2576         default:
2577                 return -EINVAL;
2578         }
2579
2580         /* The AIF2 format configuration needs to be mirrored to AIF3
2581          * on WM8958 if it's in use so just do it all the time. */
2582         switch (control->type) {
2583         case WM1811:
2584         case WM8958:
2585                 if (dai->id == 2)
2586                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2587                                             WM8994_AIF1_LRCLK_INV |
2588                                             WM8958_AIF3_FMT_MASK, aif1);
2589                 break;
2590
2591         default:
2592                 break;
2593         }
2594
2595         snd_soc_update_bits(codec, aif1_reg,
2596                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2597                             WM8994_AIF1_FMT_MASK,
2598                             aif1);
2599         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2600                             ms);
2601
2602         return 0;
2603 }
2604
2605 static struct {
2606         int val, rate;
2607 } srs[] = {
2608         { 0,   8000 },
2609         { 1,  11025 },
2610         { 2,  12000 },
2611         { 3,  16000 },
2612         { 4,  22050 },
2613         { 5,  24000 },
2614         { 6,  32000 },
2615         { 7,  44100 },
2616         { 8,  48000 },
2617         { 9,  88200 },
2618         { 10, 96000 },
2619 };
2620
2621 static int fs_ratios[] = {
2622         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2623 };
2624
2625 static int bclk_divs[] = {
2626         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2627         640, 880, 960, 1280, 1760, 1920
2628 };
2629
2630 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2631                             struct snd_pcm_hw_params *params,
2632                             struct snd_soc_dai *dai)
2633 {
2634         struct snd_soc_codec *codec = dai->codec;
2635         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2636         int aif1_reg;
2637         int aif2_reg;
2638         int bclk_reg;
2639         int lrclk_reg;
2640         int rate_reg;
2641         int aif1 = 0;
2642         int aif2 = 0;
2643         int bclk = 0;
2644         int lrclk = 0;
2645         int rate_val = 0;
2646         int id = dai->id - 1;
2647
2648         int i, cur_val, best_val, bclk_rate, best;
2649
2650         switch (dai->id) {
2651         case 1:
2652                 aif1_reg = WM8994_AIF1_CONTROL_1;
2653                 aif2_reg = WM8994_AIF1_CONTROL_2;
2654                 bclk_reg = WM8994_AIF1_BCLK;
2655                 rate_reg = WM8994_AIF1_RATE;
2656                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2657                     wm8994->lrclk_shared[0]) {
2658                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2659                 } else {
2660                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2661                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2662                 }
2663                 break;
2664         case 2:
2665                 aif1_reg = WM8994_AIF2_CONTROL_1;
2666                 aif2_reg = WM8994_AIF2_CONTROL_2;
2667                 bclk_reg = WM8994_AIF2_BCLK;
2668                 rate_reg = WM8994_AIF2_RATE;
2669                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2670                     wm8994->lrclk_shared[1]) {
2671                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2672                 } else {
2673                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2674                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2675                 }
2676                 break;
2677         default:
2678                 return -EINVAL;
2679         }
2680
2681         bclk_rate = params_rate(params);
2682         switch (params_format(params)) {
2683         case SNDRV_PCM_FORMAT_S16_LE:
2684                 bclk_rate *= 16;
2685                 break;
2686         case SNDRV_PCM_FORMAT_S20_3LE:
2687                 bclk_rate *= 20;
2688                 aif1 |= 0x20;
2689                 break;
2690         case SNDRV_PCM_FORMAT_S24_LE:
2691                 bclk_rate *= 24;
2692                 aif1 |= 0x40;
2693                 break;
2694         case SNDRV_PCM_FORMAT_S32_LE:
2695                 bclk_rate *= 32;
2696                 aif1 |= 0x60;
2697                 break;
2698         default:
2699                 return -EINVAL;
2700         }
2701
2702         wm8994->channels[id] = params_channels(params);
2703         switch (params_channels(params)) {
2704         case 1:
2705         case 2:
2706                 bclk_rate *= 2;
2707                 break;
2708         default:
2709                 bclk_rate *= 4;
2710                 break;
2711         }
2712
2713         /* Try to find an appropriate sample rate; look for an exact match. */
2714         for (i = 0; i < ARRAY_SIZE(srs); i++)
2715                 if (srs[i].rate == params_rate(params))
2716                         break;
2717         if (i == ARRAY_SIZE(srs))
2718                 return -EINVAL;
2719         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2720
2721         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2722         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2723                 dai->id, wm8994->aifclk[id], bclk_rate);
2724
2725         if (params_channels(params) == 1 &&
2726             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2727                 aif2 |= WM8994_AIF1_MONO;
2728
2729         if (wm8994->aifclk[id] == 0) {
2730                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2731                 return -EINVAL;
2732         }
2733
2734         /* AIFCLK/fs ratio; look for a close match in either direction */
2735         best = 0;
2736         best_val = abs((fs_ratios[0] * params_rate(params))
2737                        - wm8994->aifclk[id]);
2738         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2739                 cur_val = abs((fs_ratios[i] * params_rate(params))
2740                               - wm8994->aifclk[id]);
2741                 if (cur_val >= best_val)
2742                         continue;
2743                 best = i;
2744                 best_val = cur_val;
2745         }
2746         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2747                 dai->id, fs_ratios[best]);
2748         rate_val |= best;
2749
2750         /* We may not get quite the right frequency if using
2751          * approximate clocks so look for the closest match that is
2752          * higher than the target (we need to ensure that there enough
2753          * BCLKs to clock out the samples).
2754          */
2755         best = 0;
2756         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2757                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2758                 if (cur_val < 0) /* BCLK table is sorted */
2759                         break;
2760                 best = i;
2761         }
2762         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2763         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2764                 bclk_divs[best], bclk_rate);
2765         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2766
2767         lrclk = bclk_rate / params_rate(params);
2768         if (!lrclk) {
2769                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2770                         bclk_rate);
2771                 return -EINVAL;
2772         }
2773         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2774                 lrclk, bclk_rate / lrclk);
2775
2776         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2777         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2778         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2779         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2780                             lrclk);
2781         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2782                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2783
2784         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2785                 switch (dai->id) {
2786                 case 1:
2787                         wm8994->dac_rates[0] = params_rate(params);
2788                         wm8994_set_retune_mobile(codec, 0);
2789                         wm8994_set_retune_mobile(codec, 1);
2790                         break;
2791                 case 2:
2792                         wm8994->dac_rates[1] = params_rate(params);
2793                         wm8994_set_retune_mobile(codec, 2);
2794                         break;
2795                 }
2796         }
2797
2798         return 0;
2799 }
2800
2801 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2802                                  struct snd_pcm_hw_params *params,
2803                                  struct snd_soc_dai *dai)
2804 {
2805         struct snd_soc_codec *codec = dai->codec;
2806         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2807         struct wm8994 *control = wm8994->wm8994;
2808         int aif1_reg;
2809         int aif1 = 0;
2810
2811         switch (dai->id) {
2812         case 3:
2813                 switch (control->type) {
2814                 case WM1811:
2815                 case WM8958:
2816                         aif1_reg = WM8958_AIF3_CONTROL_1;
2817                         break;
2818                 default:
2819                         return 0;
2820                 }
2821         default:
2822                 return 0;
2823         }
2824
2825         switch (params_format(params)) {
2826         case SNDRV_PCM_FORMAT_S16_LE:
2827                 break;
2828         case SNDRV_PCM_FORMAT_S20_3LE:
2829                 aif1 |= 0x20;
2830                 break;
2831         case SNDRV_PCM_FORMAT_S24_LE:
2832                 aif1 |= 0x40;
2833                 break;
2834         case SNDRV_PCM_FORMAT_S32_LE:
2835                 aif1 |= 0x60;
2836                 break;
2837         default:
2838                 return -EINVAL;
2839         }
2840
2841         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2842 }
2843
2844 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2845 {
2846         struct snd_soc_codec *codec = codec_dai->codec;
2847         int mute_reg;
2848         int reg;
2849
2850         switch (codec_dai->id) {
2851         case 1:
2852                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2853                 break;
2854         case 2:
2855                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2856                 break;
2857         default:
2858                 return -EINVAL;
2859         }
2860
2861         if (mute)
2862                 reg = WM8994_AIF1DAC1_MUTE;
2863         else
2864                 reg = 0;
2865
2866         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2867
2868         return 0;
2869 }
2870
2871 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2872 {
2873         struct snd_soc_codec *codec = codec_dai->codec;
2874         int reg, val, mask;
2875
2876         switch (codec_dai->id) {
2877         case 1:
2878                 reg = WM8994_AIF1_MASTER_SLAVE;
2879                 mask = WM8994_AIF1_TRI;
2880                 break;
2881         case 2:
2882                 reg = WM8994_AIF2_MASTER_SLAVE;
2883                 mask = WM8994_AIF2_TRI;
2884                 break;
2885         default:
2886                 return -EINVAL;
2887         }
2888
2889         if (tristate)
2890                 val = mask;
2891         else
2892                 val = 0;
2893
2894         return snd_soc_update_bits(codec, reg, mask, val);
2895 }
2896
2897 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2898 {
2899         struct snd_soc_codec *codec = dai->codec;
2900
2901         /* Disable the pulls on the AIF if we're using it to save power. */
2902         snd_soc_update_bits(codec, WM8994_GPIO_3,
2903                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2904         snd_soc_update_bits(codec, WM8994_GPIO_4,
2905                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2906         snd_soc_update_bits(codec, WM8994_GPIO_5,
2907                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2908
2909         return 0;
2910 }
2911
2912 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2913
2914 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2915                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2916
2917 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2918         .set_sysclk     = wm8994_set_dai_sysclk,
2919         .set_fmt        = wm8994_set_dai_fmt,
2920         .hw_params      = wm8994_hw_params,
2921         .digital_mute   = wm8994_aif_mute,
2922         .set_pll        = wm8994_set_fll,
2923         .set_tristate   = wm8994_set_tristate,
2924 };
2925
2926 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2927         .set_sysclk     = wm8994_set_dai_sysclk,
2928         .set_fmt        = wm8994_set_dai_fmt,
2929         .hw_params      = wm8994_hw_params,
2930         .digital_mute   = wm8994_aif_mute,
2931         .set_pll        = wm8994_set_fll,
2932         .set_tristate   = wm8994_set_tristate,
2933 };
2934
2935 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2936         .hw_params      = wm8994_aif3_hw_params,
2937 };
2938
2939 static struct snd_soc_dai_driver wm8994_dai[] = {
2940         {
2941                 .name = "wm8994-aif1",
2942                 .id = 1,
2943                 .playback = {
2944                         .stream_name = "AIF1 Playback",
2945                         .channels_min = 1,
2946                         .channels_max = 2,
2947                         .rates = WM8994_RATES,
2948                         .formats = WM8994_FORMATS,
2949                         .sig_bits = 24,
2950                 },
2951                 .capture = {
2952                         .stream_name = "AIF1 Capture",
2953                         .channels_min = 1,
2954                         .channels_max = 2,
2955                         .rates = WM8994_RATES,
2956                         .formats = WM8994_FORMATS,
2957                         .sig_bits = 24,
2958                  },
2959                 .ops = &wm8994_aif1_dai_ops,
2960         },
2961         {
2962                 .name = "wm8994-aif2",
2963                 .id = 2,
2964                 .playback = {
2965                         .stream_name = "AIF2 Playback",
2966                         .channels_min = 1,
2967                         .channels_max = 2,
2968                         .rates = WM8994_RATES,
2969                         .formats = WM8994_FORMATS,
2970                         .sig_bits = 24,
2971                 },
2972                 .capture = {
2973                         .stream_name = "AIF2 Capture",
2974                         .channels_min = 1,
2975                         .channels_max = 2,
2976                         .rates = WM8994_RATES,
2977                         .formats = WM8994_FORMATS,
2978                         .sig_bits = 24,
2979                 },
2980                 .probe = wm8994_aif2_probe,
2981                 .ops = &wm8994_aif2_dai_ops,
2982         },
2983         {
2984                 .name = "wm8994-aif3",
2985                 .id = 3,
2986                 .playback = {
2987                         .stream_name = "AIF3 Playback",
2988                         .channels_min = 1,
2989                         .channels_max = 2,
2990                         .rates = WM8994_RATES,
2991                         .formats = WM8994_FORMATS,
2992                         .sig_bits = 24,
2993                 },
2994                 .capture = {
2995                         .stream_name = "AIF3 Capture",
2996                         .channels_min = 1,
2997                         .channels_max = 2,
2998                         .rates = WM8994_RATES,
2999                         .formats = WM8994_FORMATS,
3000                         .sig_bits = 24,
3001                  },
3002                 .ops = &wm8994_aif3_dai_ops,
3003         }
3004 };
3005
3006 #ifdef CONFIG_PM
3007 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3008 {
3009         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3010         int i, ret;
3011
3012         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3013                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3014                        sizeof(struct wm8994_fll_config));
3015                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3016                 if (ret < 0)
3017                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3018                                  i + 1, ret);
3019         }
3020
3021         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3022
3023         return 0;
3024 }
3025
3026 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3027 {
3028         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3029         struct wm8994 *control = wm8994->wm8994;
3030         int i, ret;
3031         unsigned int val, mask;
3032
3033         if (wm8994->revision < 4) {
3034                 /* force a HW read */
3035                 ret = regmap_read(control->regmap,
3036                                   WM8994_POWER_MANAGEMENT_5, &val);
3037
3038                 /* modify the cache only */
3039                 codec->cache_only = 1;
3040                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3041                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3042                 val &= mask;
3043                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3044                                     mask, val);
3045                 codec->cache_only = 0;
3046         }
3047
3048         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3049                 if (!wm8994->fll_suspend[i].out)
3050                         continue;
3051
3052                 ret = _wm8994_set_fll(codec, i + 1,
3053                                      wm8994->fll_suspend[i].src,
3054                                      wm8994->fll_suspend[i].in,
3055                                      wm8994->fll_suspend[i].out);
3056                 if (ret < 0)
3057                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3058                                  i + 1, ret);
3059         }
3060
3061         return 0;
3062 }
3063 #else
3064 #define wm8994_codec_suspend NULL
3065 #define wm8994_codec_resume NULL
3066 #endif
3067
3068 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3069 {
3070         struct snd_soc_codec *codec = wm8994->hubs.codec;
3071         struct wm8994_pdata *pdata = wm8994->pdata;
3072         struct snd_kcontrol_new controls[] = {
3073                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3074                              wm8994->retune_mobile_enum,
3075                              wm8994_get_retune_mobile_enum,
3076                              wm8994_put_retune_mobile_enum),
3077                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3078                              wm8994->retune_mobile_enum,
3079                              wm8994_get_retune_mobile_enum,
3080                              wm8994_put_retune_mobile_enum),
3081                 SOC_ENUM_EXT("AIF2 EQ Mode",
3082                              wm8994->retune_mobile_enum,
3083                              wm8994_get_retune_mobile_enum,
3084                              wm8994_put_retune_mobile_enum),
3085         };
3086         int ret, i, j;
3087         const char **t;
3088
3089         /* We need an array of texts for the enum API but the number
3090          * of texts is likely to be less than the number of
3091          * configurations due to the sample rate dependency of the
3092          * configurations. */
3093         wm8994->num_retune_mobile_texts = 0;
3094         wm8994->retune_mobile_texts = NULL;
3095         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3096                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3097                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
3098                                    wm8994->retune_mobile_texts[j]) == 0)
3099                                 break;
3100                 }
3101
3102                 if (j != wm8994->num_retune_mobile_texts)
3103                         continue;
3104
3105                 /* Expand the array... */
3106                 t = krealloc(wm8994->retune_mobile_texts,
3107                              sizeof(char *) *
3108                              (wm8994->num_retune_mobile_texts + 1),
3109                              GFP_KERNEL);
3110                 if (t == NULL)
3111                         continue;
3112
3113                 /* ...store the new entry... */
3114                 t[wm8994->num_retune_mobile_texts] =
3115                         pdata->retune_mobile_cfgs[i].name;
3116
3117                 /* ...and remember the new version. */
3118                 wm8994->num_retune_mobile_texts++;
3119                 wm8994->retune_mobile_texts = t;
3120         }
3121
3122         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3123                 wm8994->num_retune_mobile_texts);
3124
3125         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3126         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3127
3128         ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3129                                    ARRAY_SIZE(controls));
3130         if (ret != 0)
3131                 dev_err(wm8994->hubs.codec->dev,
3132                         "Failed to add ReTune Mobile controls: %d\n", ret);
3133 }
3134
3135 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3136 {
3137         struct snd_soc_codec *codec = wm8994->hubs.codec;
3138         struct wm8994_pdata *pdata = wm8994->pdata;
3139         int ret, i;
3140
3141         if (!pdata)
3142                 return;
3143
3144         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3145                                       pdata->lineout2_diff,
3146                                       pdata->lineout1fb,
3147                                       pdata->lineout2fb,
3148                                       pdata->jd_scthr,
3149                                       pdata->jd_thr,
3150                                       pdata->micb1_delay,
3151                                       pdata->micb2_delay,
3152                                       pdata->micbias1_lvl,
3153                                       pdata->micbias2_lvl);
3154
3155         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3156
3157         if (pdata->num_drc_cfgs) {
3158                 struct snd_kcontrol_new controls[] = {
3159                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3160                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3161                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3162                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3163                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3164                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
3165                 };
3166
3167                 /* We need an array of texts for the enum API */
3168                 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3169                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3170                 if (!wm8994->drc_texts) {
3171                         dev_err(wm8994->hubs.codec->dev,
3172                                 "Failed to allocate %d DRC config texts\n",
3173                                 pdata->num_drc_cfgs);
3174                         return;
3175                 }
3176
3177                 for (i = 0; i < pdata->num_drc_cfgs; i++)
3178                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3179
3180                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3181                 wm8994->drc_enum.texts = wm8994->drc_texts;
3182
3183                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3184                                            ARRAY_SIZE(controls));
3185                 for (i = 0; i < WM8994_NUM_DRC; i++)
3186                         wm8994_set_drc(codec, i);
3187         } else {
3188                 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3189                                                  wm8994_drc_controls,
3190                                                  ARRAY_SIZE(wm8994_drc_controls));
3191         }
3192
3193         if (ret != 0)
3194                 dev_err(wm8994->hubs.codec->dev,
3195                         "Failed to add DRC mode controls: %d\n", ret);
3196
3197
3198         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3199                 pdata->num_retune_mobile_cfgs);
3200
3201         if (pdata->num_retune_mobile_cfgs)
3202                 wm8994_handle_retune_mobile_pdata(wm8994);
3203         else
3204                 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3205                                      ARRAY_SIZE(wm8994_eq_controls));
3206
3207         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3208                 if (pdata->micbias[i]) {
3209                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
3210                                 pdata->micbias[i] & 0xffff);
3211                 }
3212         }
3213 }
3214
3215 /**
3216  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3217  *
3218  * @codec:   WM8994 codec
3219  * @jack:    jack to report detection events on
3220  * @micbias: microphone bias to detect on
3221  *
3222  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
3223  * being used to bring out signals to the processor then only platform
3224  * data configuration is needed for WM8994 and processor GPIOs should
3225  * be configured using snd_soc_jack_add_gpios() instead.
3226  *
3227  * Configuration of detection levels is available via the micbias1_lvl
3228  * and micbias2_lvl platform data members.
3229  */
3230 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3231                       int micbias)
3232 {
3233         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3234         struct wm8994_micdet *micdet;
3235         struct wm8994 *control = wm8994->wm8994;
3236         int reg, ret;
3237
3238         if (control->type != WM8994) {
3239                 dev_warn(codec->dev, "Not a WM8994\n");
3240                 return -EINVAL;
3241         }
3242
3243         switch (micbias) {
3244         case 1:
3245                 micdet = &wm8994->micdet[0];
3246                 if (jack)
3247                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3248                                                             "MICBIAS1");
3249                 else
3250                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3251                                                        "MICBIAS1");
3252                 break;
3253         case 2:
3254                 micdet = &wm8994->micdet[1];
3255                 if (jack)
3256                         ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3257                                                             "MICBIAS1");
3258                 else
3259                         ret = snd_soc_dapm_disable_pin(&codec->dapm,
3260                                                        "MICBIAS1");
3261                 break;
3262         default:
3263                 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3264                 return -EINVAL;
3265         }
3266
3267         if (ret != 0)
3268                 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3269                          micbias, ret);
3270
3271         dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3272                 micbias, jack);
3273
3274         /* Store the configuration */
3275         micdet->jack = jack;
3276         micdet->detecting = true;
3277
3278         /* If either of the jacks is set up then enable detection */
3279         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3280                 reg = WM8994_MICD_ENA;
3281         else
3282                 reg = 0;
3283
3284         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3285
3286         /* enable MICDET and MICSHRT deboune */
3287         snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3288                             WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3289                             WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3290                             WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3291
3292         snd_soc_dapm_sync(&codec->dapm);
3293
3294         return 0;
3295 }
3296 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3297
3298 static void wm8994_mic_work(struct work_struct *work)
3299 {
3300         struct wm8994_priv *priv = container_of(work,
3301                                                 struct wm8994_priv,
3302                                                 mic_work.work);
3303         struct regmap *regmap = priv->wm8994->regmap;
3304         struct device *dev = priv->wm8994->dev;
3305         unsigned int reg;
3306         int ret;
3307         int report;
3308
3309         pm_runtime_get_sync(dev);
3310
3311         ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3312         if (ret < 0) {
3313                 dev_err(dev, "Failed to read microphone status: %d\n",
3314                         ret);
3315                 pm_runtime_put(dev);
3316                 return;
3317         }
3318
3319         dev_dbg(dev, "Microphone status: %x\n", reg);
3320
3321         report = 0;
3322         if (reg & WM8994_MIC1_DET_STS) {
3323                 if (priv->micdet[0].detecting)
3324                         report = SND_JACK_HEADSET;
3325         }
3326         if (reg & WM8994_MIC1_SHRT_STS) {
3327                 if (priv->micdet[0].detecting)
3328                         report = SND_JACK_HEADPHONE;
3329                 else
3330                         report |= SND_JACK_BTN_0;
3331         }
3332         if (report)
3333                 priv->micdet[0].detecting = false;
3334         else
3335                 priv->micdet[0].detecting = true;
3336
3337         snd_soc_jack_report(priv->micdet[0].jack, report,
3338                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3339
3340         report = 0;
3341         if (reg & WM8994_MIC2_DET_STS) {
3342                 if (priv->micdet[1].detecting)
3343                         report = SND_JACK_HEADSET;
3344         }
3345         if (reg & WM8994_MIC2_SHRT_STS) {
3346                 if (priv->micdet[1].detecting)
3347                         report = SND_JACK_HEADPHONE;
3348                 else
3349                         report |= SND_JACK_BTN_0;
3350         }
3351         if (report)
3352                 priv->micdet[1].detecting = false;
3353         else
3354                 priv->micdet[1].detecting = true;
3355
3356         snd_soc_jack_report(priv->micdet[1].jack, report,
3357                             SND_JACK_HEADSET | SND_JACK_BTN_0);
3358
3359         pm_runtime_put(dev);
3360 }
3361
3362 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3363 {
3364         struct wm8994_priv *priv = data;
3365         struct snd_soc_codec *codec = priv->hubs.codec;
3366
3367 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3368         trace_snd_soc_jack_irq(dev_name(codec->dev));
3369 #endif
3370
3371         pm_wakeup_event(codec->dev, 300);
3372
3373         schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3374
3375         return IRQ_HANDLED;
3376 }
3377
3378 /* Default microphone detection handler for WM8958 - the user can
3379  * override this if they wish.
3380  */
3381 static void wm8958_default_micdet(u16 status, void *data)
3382 {
3383         struct snd_soc_codec *codec = data;
3384         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3385         int report;
3386
3387         dev_dbg(codec->dev, "MICDET %x\n", status);
3388
3389         /* Either nothing present or just starting detection */
3390         if (!(status & WM8958_MICD_STS)) {
3391                 if (!wm8994->jackdet) {
3392                         /* If nothing present then clear our statuses */
3393                         dev_dbg(codec->dev, "Detected open circuit\n");
3394                         wm8994->jack_mic = false;
3395                         wm8994->mic_detecting = true;
3396
3397                         wm8958_micd_set_rate(codec);
3398
3399                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3400                                             wm8994->btn_mask |
3401                                             SND_JACK_HEADSET);
3402                 }
3403                 return;
3404         }
3405
3406         /* If the measurement is showing a high impedence we've got a
3407          * microphone.
3408          */
3409         if (wm8994->mic_detecting && (status & 0x600)) {
3410                 dev_dbg(codec->dev, "Detected microphone\n");
3411
3412                 wm8994->mic_detecting = false;
3413                 wm8994->jack_mic = true;
3414
3415                 wm8958_micd_set_rate(codec);
3416
3417                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3418                                     SND_JACK_HEADSET);
3419         }
3420
3421
3422         if (wm8994->mic_detecting && status & 0xfc) {
3423                 dev_dbg(codec->dev, "Detected headphone\n");
3424                 wm8994->mic_detecting = false;
3425
3426                 wm8958_micd_set_rate(codec);
3427
3428                 /* If we have jackdet that will detect removal */
3429                 if (wm8994->jackdet) {
3430                         mutex_lock(&wm8994->accdet_lock);
3431
3432                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3433                                             WM8958_MICD_ENA, 0);
3434
3435                         wm1811_jackdet_set_mode(codec,
3436                                                 WM1811_JACKDET_MODE_JACK);
3437
3438                         mutex_unlock(&wm8994->accdet_lock);
3439
3440                         if (wm8994->pdata->jd_ext_cap)
3441                                 snd_soc_dapm_disable_pin(&codec->dapm,
3442                                                          "MICBIAS2");
3443                 }
3444
3445                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3446                                     SND_JACK_HEADSET);
3447         }
3448
3449         /* Report short circuit as a button */
3450         if (wm8994->jack_mic) {
3451                 report = 0;
3452                 if (status & 0x4)
3453                         report |= SND_JACK_BTN_0;
3454
3455                 if (status & 0x8)
3456                         report |= SND_JACK_BTN_1;
3457
3458                 if (status & 0x10)
3459                         report |= SND_JACK_BTN_2;
3460
3461                 if (status & 0x20)
3462                         report |= SND_JACK_BTN_3;
3463
3464                 if (status & 0x40)
3465                         report |= SND_JACK_BTN_4;
3466
3467                 if (status & 0x80)
3468                         report |= SND_JACK_BTN_5;
3469
3470                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3471                                     wm8994->btn_mask);
3472         }
3473 }
3474
3475 /* Deferred mic detection to allow for extra settling time */
3476 static void wm1811_mic_work(struct work_struct *work)
3477 {
3478         struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3479                                                   mic_work.work);
3480         struct snd_soc_codec *codec = wm8994->hubs.codec;
3481
3482         pm_runtime_get_sync(codec->dev);
3483
3484         /* If required for an external cap force MICBIAS on */
3485         if (wm8994->pdata->jd_ext_cap) {
3486                 snd_soc_dapm_force_enable_pin(&codec->dapm,
3487                                               "MICBIAS2");
3488                 snd_soc_dapm_sync(&codec->dapm);
3489         }
3490
3491         mutex_lock(&wm8994->accdet_lock);
3492
3493         dev_dbg(codec->dev, "Starting mic detection\n");
3494
3495         /*
3496          * Start off measument of microphone impedence to find out
3497          * what's actually there.
3498          */
3499         wm8994->mic_detecting = true;
3500         wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3501
3502         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3503                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3504
3505         mutex_unlock(&wm8994->accdet_lock);
3506
3507         pm_runtime_put(codec->dev);
3508 }
3509
3510 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3511 {
3512         struct wm8994_priv *wm8994 = data;
3513         struct snd_soc_codec *codec = wm8994->hubs.codec;
3514         int reg, delay;
3515         bool present;
3516
3517         pm_runtime_get_sync(codec->dev);
3518
3519         mutex_lock(&wm8994->accdet_lock);
3520
3521         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3522         if (reg < 0) {
3523                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3524                 mutex_unlock(&wm8994->accdet_lock);
3525                 pm_runtime_put(codec->dev);
3526                 return IRQ_NONE;
3527         }
3528
3529         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3530
3531         present = reg & WM1811_JACKDET_LVL;
3532
3533         if (present) {
3534                 dev_dbg(codec->dev, "Jack detected\n");
3535
3536                 wm8958_micd_set_rate(codec);
3537
3538                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3539                                     WM8958_MICB2_DISCH, 0);
3540
3541                 /* Disable debounce while inserted */
3542                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3543                                     WM1811_JACKDET_DB, 0);
3544
3545                 delay = wm8994->pdata->micdet_delay;
3546                 schedule_delayed_work(&wm8994->mic_work,
3547                                       msecs_to_jiffies(delay));
3548         } else {
3549                 dev_dbg(codec->dev, "Jack not detected\n");
3550
3551                 cancel_delayed_work_sync(&wm8994->mic_work);
3552
3553                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3554                                     WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3555
3556                 /* Enable debounce while removed */
3557                 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3558                                     WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3559
3560                 wm8994->mic_detecting = false;
3561                 wm8994->jack_mic = false;
3562                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3563                                     WM8958_MICD_ENA, 0);
3564                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3565         }
3566
3567         mutex_unlock(&wm8994->accdet_lock);
3568
3569         /* Turn off MICBIAS if it was on for an external cap */
3570         if (wm8994->pdata->jd_ext_cap && !present)
3571                 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3572
3573         if (present)
3574                 snd_soc_jack_report(wm8994->micdet[0].jack,
3575                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3576         else
3577                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3578                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3579                                     wm8994->btn_mask);
3580
3581         /* Since we only report deltas force an update, ensures we
3582          * avoid bootstrapping issues with the core. */
3583         snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3584
3585         pm_runtime_put(codec->dev);
3586         return IRQ_HANDLED;
3587 }
3588
3589 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3590 {
3591         struct wm8994_priv *wm8994 = container_of(work,
3592                                                 struct wm8994_priv,
3593                                                 jackdet_bootstrap.work);
3594         wm1811_jackdet_irq(0, wm8994);
3595 }
3596
3597 /**
3598  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3599  *
3600  * @codec:   WM8958 codec
3601  * @jack:    jack to report detection events on
3602  *
3603  * Enable microphone detection functionality for the WM8958.  By
3604  * default simple detection which supports the detection of up to 6
3605  * buttons plus video and microphone functionality is supported.
3606  *
3607  * The WM8958 has an advanced jack detection facility which is able to
3608  * support complex accessory detection, especially when used in
3609  * conjunction with external circuitry.  In order to provide maximum
3610  * flexiblity a callback is provided which allows a completely custom
3611  * detection algorithm.
3612  */
3613 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3614                       wm8958_micdet_cb cb, void *cb_data)
3615 {
3616         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3617         struct wm8994 *control = wm8994->wm8994;
3618         u16 micd_lvl_sel;
3619
3620         switch (control->type) {
3621         case WM1811:
3622         case WM8958:
3623                 break;
3624         default:
3625                 return -EINVAL;
3626         }
3627
3628         if (jack) {
3629                 if (!cb) {
3630                         dev_dbg(codec->dev, "Using default micdet callback\n");
3631                         cb = wm8958_default_micdet;
3632                         cb_data = codec;
3633                 }
3634
3635                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3636                 snd_soc_dapm_sync(&codec->dapm);
3637
3638                 wm8994->micdet[0].jack = jack;
3639                 wm8994->jack_cb = cb;
3640                 wm8994->jack_cb_data = cb_data;
3641
3642                 wm8994->mic_detecting = true;
3643                 wm8994->jack_mic = false;
3644
3645                 wm8958_micd_set_rate(codec);
3646
3647                 /* Detect microphones and short circuits by default */
3648                 if (wm8994->pdata->micd_lvl_sel)
3649                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3650                 else
3651                         micd_lvl_sel = 0x41;
3652
3653                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3654                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3655                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3656
3657                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3658                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3659
3660                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3661
3662                 /*
3663                  * If we can use jack detection start off with that,
3664                  * otherwise jump straight to microphone detection.
3665                  */
3666                 if (wm8994->jackdet) {
3667                         /* Disable debounce for the initial detect */
3668                         snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3669                                             WM1811_JACKDET_DB, 0);
3670
3671                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
3672                                             WM8958_MICB2_DISCH,
3673                                             WM8958_MICB2_DISCH);
3674                         snd_soc_update_bits(codec, WM8994_LDO_1,
3675                                             WM8994_LDO1_DISCH, 0);
3676                         wm1811_jackdet_set_mode(codec,
3677                                                 WM1811_JACKDET_MODE_JACK);
3678                 } else {
3679                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3680                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3681                 }
3682
3683         } else {
3684                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3685                                     WM8958_MICD_ENA, 0);
3686                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3687                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3688                 snd_soc_dapm_sync(&codec->dapm);
3689         }
3690
3691         return 0;
3692 }
3693 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3694
3695 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3696 {
3697         struct wm8994_priv *wm8994 = data;
3698         struct snd_soc_codec *codec = wm8994->hubs.codec;
3699         int reg, count;
3700
3701         /*
3702          * Jack detection may have detected a removal simulataneously
3703          * with an update of the MICDET status; if so it will have
3704          * stopped detection and we can ignore this interrupt.
3705          */
3706         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3707                 return IRQ_HANDLED;
3708
3709         pm_runtime_get_sync(codec->dev);
3710
3711         /* We may occasionally read a detection without an impedence
3712          * range being provided - if that happens loop again.
3713          */
3714         count = 10;
3715         do {
3716                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3717                 if (reg < 0) {
3718                         dev_err(codec->dev,
3719                                 "Failed to read mic detect status: %d\n",
3720                                 reg);
3721                         pm_runtime_put(codec->dev);
3722                         return IRQ_NONE;
3723                 }
3724
3725                 if (!(reg & WM8958_MICD_VALID)) {
3726                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3727                         goto out;
3728                 }
3729
3730                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3731                         break;
3732
3733                 msleep(1);
3734         } while (count--);
3735
3736         if (count == 0)
3737                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3738
3739 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3740         trace_snd_soc_jack_irq(dev_name(codec->dev));
3741 #endif
3742
3743         if (wm8994->jack_cb)
3744                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3745         else
3746                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3747
3748 out:
3749         pm_runtime_put(codec->dev);
3750         return IRQ_HANDLED;
3751 }
3752
3753 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3754 {
3755         struct snd_soc_codec *codec = data;
3756
3757         dev_err(codec->dev, "FIFO error\n");
3758
3759         return IRQ_HANDLED;
3760 }
3761
3762 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3763 {
3764         struct snd_soc_codec *codec = data;
3765
3766         dev_err(codec->dev, "Thermal warning\n");
3767
3768         return IRQ_HANDLED;
3769 }
3770
3771 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3772 {
3773         struct snd_soc_codec *codec = data;
3774
3775         dev_crit(codec->dev, "Thermal shutdown\n");
3776
3777         return IRQ_HANDLED;
3778 }
3779
3780 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3781 {
3782         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3783         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3784         struct snd_soc_dapm_context *dapm = &codec->dapm;
3785         unsigned int reg;
3786         int ret, i;
3787
3788         wm8994->hubs.codec = codec;
3789         codec->control_data = control->regmap;
3790
3791         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3792
3793         mutex_init(&wm8994->accdet_lock);
3794         INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3795                           wm1811_jackdet_bootstrap);
3796
3797         switch (control->type) {
3798         case WM8994:
3799                 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3800                 break;
3801         case WM1811:
3802                 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3803                 break;
3804         default:
3805                 break;
3806         }
3807
3808         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3809                 init_completion(&wm8994->fll_locked[i]);
3810
3811         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3812                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3813
3814         pm_runtime_enable(codec->dev);
3815         pm_runtime_idle(codec->dev);
3816
3817         /* By default use idle_bias_off, will override for WM8994 */
3818         codec->dapm.idle_bias_off = 1;
3819
3820         /* Set revision-specific configuration */
3821         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3822         switch (control->type) {
3823         case WM8994:
3824                 /* Single ended line outputs should have VMID on. */
3825                 if (!wm8994->pdata->lineout1_diff ||
3826                     !wm8994->pdata->lineout2_diff)
3827                         codec->dapm.idle_bias_off = 0;
3828
3829                 switch (wm8994->revision) {
3830                 case 2:
3831                 case 3:
3832                         wm8994->hubs.dcs_codes_l = -5;
3833                         wm8994->hubs.dcs_codes_r = -5;
3834                         wm8994->hubs.hp_startup_mode = 1;
3835                         wm8994->hubs.dcs_readback_mode = 1;
3836                         wm8994->hubs.series_startup = 1;
3837                         break;
3838                 default:
3839                         wm8994->hubs.dcs_readback_mode = 2;
3840                         break;
3841                 }
3842                 break;
3843
3844         case WM8958:
3845                 wm8994->hubs.dcs_readback_mode = 1;
3846                 wm8994->hubs.hp_startup_mode = 1;
3847
3848                 switch (wm8994->revision) {
3849                 case 0:
3850                         break;
3851                 default:
3852                         wm8994->fll_byp = true;
3853                         break;
3854                 }
3855                 break;
3856
3857         case WM1811:
3858                 wm8994->hubs.dcs_readback_mode = 2;
3859                 wm8994->hubs.no_series_update = 1;
3860                 wm8994->hubs.hp_startup_mode = 1;
3861                 wm8994->hubs.no_cache_dac_hp_direct = true;
3862                 wm8994->fll_byp = true;
3863
3864                 switch (control->cust_id) {
3865                 case 0:
3866                 case 2:
3867                         wm8994->hubs.dcs_codes_l = -9;
3868                         wm8994->hubs.dcs_codes_r = -7;
3869                         break;
3870                 case 1:
3871                 case 3:
3872                         wm8994->hubs.dcs_codes_l = -8;
3873                         wm8994->hubs.dcs_codes_r = -7;
3874                         break;
3875                 default:
3876                         break;
3877                 }
3878
3879                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3880                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3881                 break;
3882
3883         default:
3884                 break;
3885         }
3886
3887         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3888                            wm8994_fifo_error, "FIFO error", codec);
3889         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3890                            wm8994_temp_warn, "Thermal warning", codec);
3891         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3892                            wm8994_temp_shut, "Thermal shutdown", codec);
3893
3894         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3895                                  wm_hubs_dcs_done, "DC servo done",
3896                                  &wm8994->hubs);
3897         if (ret == 0)
3898                 wm8994->hubs.dcs_done_irq = true;
3899
3900         switch (control->type) {
3901         case WM8994:
3902                 if (wm8994->micdet_irq) {
3903                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3904                                                    wm8994_mic_irq,
3905                                                    IRQF_TRIGGER_RISING,
3906                                                    "Mic1 detect",
3907                                                    wm8994);
3908                         if (ret != 0)
3909                                 dev_warn(codec->dev,
3910                                          "Failed to request Mic1 detect IRQ: %d\n",
3911                                          ret);
3912                 }
3913
3914                 ret = wm8994_request_irq(wm8994->wm8994,
3915                                          WM8994_IRQ_MIC1_SHRT,
3916                                          wm8994_mic_irq, "Mic 1 short",
3917                                          wm8994);
3918                 if (ret != 0)
3919                         dev_warn(codec->dev,
3920                                  "Failed to request Mic1 short IRQ: %d\n",
3921                                  ret);
3922
3923                 ret = wm8994_request_irq(wm8994->wm8994,
3924                                          WM8994_IRQ_MIC2_DET,
3925                                          wm8994_mic_irq, "Mic 2 detect",
3926                                          wm8994);
3927                 if (ret != 0)
3928                         dev_warn(codec->dev,
3929                                  "Failed to request Mic2 detect IRQ: %d\n",
3930                                  ret);
3931
3932                 ret = wm8994_request_irq(wm8994->wm8994,
3933                                          WM8994_IRQ_MIC2_SHRT,
3934                                          wm8994_mic_irq, "Mic 2 short",
3935                                          wm8994);
3936                 if (ret != 0)
3937                         dev_warn(codec->dev,
3938                                  "Failed to request Mic2 short IRQ: %d\n",
3939                                  ret);
3940                 break;
3941
3942         case WM8958:
3943         case WM1811:
3944                 if (wm8994->micdet_irq) {
3945                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3946                                                    wm8958_mic_irq,
3947                                                    IRQF_TRIGGER_RISING,
3948                                                    "Mic detect",
3949                                                    wm8994);
3950                         if (ret != 0)
3951                                 dev_warn(codec->dev,
3952                                          "Failed to request Mic detect IRQ: %d\n",
3953                                          ret);
3954                 } else {
3955                         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3956                                            wm8958_mic_irq, "Mic detect",
3957                                            wm8994);
3958                 }
3959         }
3960
3961         switch (control->type) {
3962         case WM1811:
3963                 if (control->cust_id > 1 || wm8994->revision > 1) {
3964                         ret = wm8994_request_irq(wm8994->wm8994,
3965                                                  WM8994_IRQ_GPIO(6),
3966                                                  wm1811_jackdet_irq, "JACKDET",
3967                                                  wm8994);
3968                         if (ret == 0)
3969                                 wm8994->jackdet = true;
3970                 }
3971                 break;
3972         default:
3973                 break;
3974         }
3975
3976         wm8994->fll_locked_irq = true;
3977         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3978                 ret = wm8994_request_irq(wm8994->wm8994,
3979                                          WM8994_IRQ_FLL1_LOCK + i,
3980                                          wm8994_fll_locked_irq, "FLL lock",
3981                                          &wm8994->fll_locked[i]);
3982                 if (ret != 0)
3983                         wm8994->fll_locked_irq = false;
3984         }
3985
3986         /* Make sure we can read from the GPIOs if they're inputs */
3987         pm_runtime_get_sync(codec->dev);
3988
3989         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3990          * configured on init - if a system wants to do this dynamically
3991          * at runtime we can deal with that then.
3992          */
3993         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3994         if (ret < 0) {
3995                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3996                 goto err_irq;
3997         }
3998         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3999                 wm8994->lrclk_shared[0] = 1;
4000                 wm8994_dai[0].symmetric_rates = 1;
4001         } else {
4002                 wm8994->lrclk_shared[0] = 0;
4003         }
4004
4005         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
4006         if (ret < 0) {
4007                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4008                 goto err_irq;
4009         }
4010         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4011                 wm8994->lrclk_shared[1] = 1;
4012                 wm8994_dai[1].symmetric_rates = 1;
4013         } else {
4014                 wm8994->lrclk_shared[1] = 0;
4015         }
4016
4017         pm_runtime_put(codec->dev);
4018
4019         /* Latch volume update bits */
4020         for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4021                 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4022                                     wm8994_vu_bits[i].mask,
4023                                     wm8994_vu_bits[i].mask);
4024
4025         /* Set the low bit of the 3D stereo depth so TLV matches */
4026         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4027                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4028                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4029         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4030                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4031                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4032         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4033                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4034                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4035
4036         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4037          * use this; it only affects behaviour on idle TDM clock
4038          * cycles. */
4039         switch (control->type) {
4040         case WM8994:
4041         case WM8958:
4042                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4043                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4044                 break;
4045         default:
4046                 break;
4047         }
4048
4049         /* Put MICBIAS into bypass mode by default on newer devices */
4050         switch (control->type) {
4051         case WM8958:
4052         case WM1811:
4053                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4054                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4055                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4056                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4057                 break;
4058         default:
4059                 break;
4060         }
4061
4062         wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4063         wm_hubs_update_class_w(codec);
4064
4065         wm8994_handle_pdata(wm8994);
4066
4067         wm_hubs_add_analogue_controls(codec);
4068         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4069                              ARRAY_SIZE(wm8994_snd_controls));
4070         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4071                                   ARRAY_SIZE(wm8994_dapm_widgets));
4072
4073         switch (control->type) {
4074         case WM8994:
4075                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4076                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
4077                 if (wm8994->revision < 4) {
4078                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4079                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4080                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4081                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4082                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4083                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4084                 } else {
4085                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4086                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4087                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4088                                                   ARRAY_SIZE(wm8994_adc_widgets));
4089                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4090                                                   ARRAY_SIZE(wm8994_dac_widgets));
4091                 }
4092                 break;
4093         case WM8958:
4094                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4095                                      ARRAY_SIZE(wm8958_snd_controls));
4096                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4097                                           ARRAY_SIZE(wm8958_dapm_widgets));
4098                 if (wm8994->revision < 1) {
4099                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4100                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4101                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4102                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
4103                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4104                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
4105                 } else {
4106                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4107                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
4108                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4109                                                   ARRAY_SIZE(wm8994_adc_widgets));
4110                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4111                                                   ARRAY_SIZE(wm8994_dac_widgets));
4112                 }
4113                 break;
4114
4115         case WM1811:
4116                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4117                                      ARRAY_SIZE(wm8958_snd_controls));
4118                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4119                                           ARRAY_SIZE(wm8958_dapm_widgets));
4120                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4121                                           ARRAY_SIZE(wm8994_lateclk_widgets));
4122                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4123                                           ARRAY_SIZE(wm8994_adc_widgets));
4124                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4125                                           ARRAY_SIZE(wm8994_dac_widgets));
4126                 break;
4127         }
4128
4129         wm_hubs_add_analogue_routes(codec, 0, 0);
4130         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4131
4132         switch (control->type) {
4133         case WM8994:
4134                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4135                                         ARRAY_SIZE(wm8994_intercon));
4136
4137                 if (wm8994->revision < 4) {
4138                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4139                                                 ARRAY_SIZE(wm8994_revd_intercon));
4140                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4141                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4142                 } else {
4143                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4144                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4145                 }
4146                 break;
4147         case WM8958:
4148                 if (wm8994->revision < 1) {
4149                         snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4150                                                 ARRAY_SIZE(wm8994_intercon));
4151                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4152                                                 ARRAY_SIZE(wm8994_revd_intercon));
4153                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4154                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4155                 } else {
4156                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4157                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
4158                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4159                                                 ARRAY_SIZE(wm8958_intercon));
4160                 }
4161
4162                 wm8958_dsp2_init(codec);
4163                 break;
4164         case WM1811:
4165                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4166                                         ARRAY_SIZE(wm8994_lateclk_intercon));
4167                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4168                                         ARRAY_SIZE(wm8958_intercon));
4169                 break;
4170         }
4171
4172         return 0;
4173
4174 err_irq:
4175         if (wm8994->jackdet)
4176                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4177         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4178         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4179         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4180         if (wm8994->micdet_irq)
4181                 free_irq(wm8994->micdet_irq, wm8994);
4182         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4183                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4184                                 &wm8994->fll_locked[i]);
4185         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4186                         &wm8994->hubs);
4187         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4188         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4189         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4190
4191         return ret;
4192 }
4193
4194 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4195 {
4196         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4197         struct wm8994 *control = wm8994->wm8994;
4198         int i;
4199
4200         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4201
4202         pm_runtime_disable(codec->dev);
4203
4204         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4205                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4206                                 &wm8994->fll_locked[i]);
4207
4208         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4209                         &wm8994->hubs);
4210         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4211         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4212         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4213
4214         if (wm8994->jackdet)
4215                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4216
4217         switch (control->type) {
4218         case WM8994:
4219                 if (wm8994->micdet_irq)
4220                         free_irq(wm8994->micdet_irq, wm8994);
4221                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4222                                 wm8994);
4223                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4224                                 wm8994);
4225                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4226                                 wm8994);
4227                 break;
4228
4229         case WM1811:
4230         case WM8958:
4231                 if (wm8994->micdet_irq)
4232                         free_irq(wm8994->micdet_irq, wm8994);
4233                 break;
4234         }
4235         release_firmware(wm8994->mbc);
4236         release_firmware(wm8994->mbc_vss);
4237         release_firmware(wm8994->enh_eq);
4238         kfree(wm8994->retune_mobile_texts);
4239         return 0;
4240 }
4241
4242 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4243         .probe =        wm8994_codec_probe,
4244         .remove =       wm8994_codec_remove,
4245         .suspend =      wm8994_codec_suspend,
4246         .resume =       wm8994_codec_resume,
4247         .set_bias_level = wm8994_set_bias_level,
4248 };
4249
4250 static int __devinit wm8994_probe(struct platform_device *pdev)
4251 {
4252         struct wm8994_priv *wm8994;
4253
4254         wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4255                               GFP_KERNEL);
4256         if (wm8994 == NULL)
4257                 return -ENOMEM;
4258         platform_set_drvdata(pdev, wm8994);
4259
4260         wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4261         wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4262
4263         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4264                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
4265 }
4266
4267 static int __devexit wm8994_remove(struct platform_device *pdev)
4268 {
4269         snd_soc_unregister_codec(&pdev->dev);
4270         return 0;
4271 }
4272
4273 #ifdef CONFIG_PM_SLEEP
4274 static int wm8994_suspend(struct device *dev)
4275 {
4276         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4277
4278         /* Drop down to power saving mode when system is suspended */
4279         if (wm8994->jackdet && !wm8994->active_refcount)
4280                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4281                                    WM1811_JACKDET_MODE_MASK,
4282                                    wm8994->jackdet_mode);
4283
4284         return 0;
4285 }
4286
4287 static int wm8994_resume(struct device *dev)
4288 {
4289         struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4290
4291         if (wm8994->jackdet && wm8994->jack_cb)
4292                 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4293                                    WM1811_JACKDET_MODE_MASK,
4294                                    WM1811_JACKDET_MODE_AUDIO);
4295
4296         return 0;
4297 }
4298 #endif
4299
4300 static const struct dev_pm_ops wm8994_pm_ops = {
4301         SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4302 };
4303
4304 static struct platform_driver wm8994_codec_driver = {
4305         .driver = {
4306                 .name = "wm8994-codec",
4307                 .owner = THIS_MODULE,
4308                 .pm = &wm8994_pm_ops,
4309         },
4310         .probe = wm8994_probe,
4311         .remove = __devexit_p(wm8994_remove),
4312 };
4313
4314 module_platform_driver(wm8994_codec_driver);
4315
4316 MODULE_DESCRIPTION("ASoC WM8994 driver");
4317 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4318 MODULE_LICENSE("GPL");
4319 MODULE_ALIAS("platform:wm8994-codec");