sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = wm8994->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110                 return 1;
 111         default:
 112                 return 0;
 113         }
 114 }
 115
 116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 117         unsigned int value)
 118 {
 119         int ret;
 120
 121         BUG_ON(reg > WM8994_MAX_REGISTER);
 122
 123         if (!wm8994_volatile(codec, reg)) {
 124                 ret = snd_soc_cache_write(codec, reg, value);
 125                 if (ret != 0)
 126                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 127                                 reg, ret);
 128         }
 129
 130         return wm8994_reg_write(codec->control_data, reg, value);
 131 }
 132
 133 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 134                                 unsigned int reg)
 135 {
 136         unsigned int val;
 137         int ret;
 138
 139         BUG_ON(reg > WM8994_MAX_REGISTER);
 140
 141         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 142             reg < codec->driver->reg_cache_size) {
 143                 ret = snd_soc_cache_read(codec, reg, &val);
 144                 if (ret >= 0)
 145                         return val;
 146                 else
 147                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 148                                 reg, ret);
 149         }
 150
 151         return wm8994_reg_read(codec->control_data, reg);
 152 }
 153
 154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 155 {
 156         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 157         int rate;
 158         int reg1 = 0;
 159         int offset;
 160
 161         if (aif)
 162                 offset = 4;
 163         else
 164                 offset = 0;
 165
 166         switch (wm8994->sysclk[aif]) {
 167         case WM8994_SYSCLK_MCLK1:
 168                 rate = wm8994->mclk[0];
 169                 break;
 170
 171         case WM8994_SYSCLK_MCLK2:
 172                 reg1 |= 0x8;
 173                 rate = wm8994->mclk[1];
 174                 break;
 175
 176         case WM8994_SYSCLK_FLL1:
 177                 reg1 |= 0x10;
 178                 rate = wm8994->fll[0].out;
 179                 break;
 180
 181         case WM8994_SYSCLK_FLL2:
 182                 reg1 |= 0x18;
 183                 rate = wm8994->fll[1].out;
 184                 break;
 185
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         if (rate >= 13500000) {
 191                 rate /= 2;
 192                 reg1 |= WM8994_AIF1CLK_DIV;
 193
 194                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 195                         aif + 1, rate);
 196         }
 197
 198         if (rate && rate < 3000000)
 199                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 200                          aif + 1, rate);
 201
 202         wm8994->aifclk[aif] = rate;
 203
 204         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 205                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 206                             reg1);
 207
 208         return 0;
 209 }
 210
 211 static int configure_clock(struct snd_soc_codec *codec)
 212 {
 213         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 214         int old, new;
 215
 216         /* Bring up the AIF clocks first */
 217         configure_aif_clock(codec, 0);
 218         configure_aif_clock(codec, 1);
 219
 220         /* Then switch CLK_SYS over to the higher of them; a change
 221          * can only happen as a result of a clocking change which can
 222          * only be made outside of DAPM so we can safely redo the
 223          * clocking.
 224          */
 225
 226         /* If they're equal it doesn't matter which is used */
 227         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 228                 return 0;
 229
 230         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 231                 new = WM8994_SYSCLK_SRC;
 232         else
 233                 new = 0;
 234
 235         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 236
 237         /* If there's no change then we're done. */
 238         if (old == new)
 239                 return 0;
 240
 241         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 242
 243         snd_soc_dapm_sync(&codec->dapm);
 244
 245         return 0;
 246 }
 247
 248 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 249                          struct snd_soc_dapm_widget *sink)
 250 {
 251         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 252         const char *clk;
 253
 254         /* Check what we're currently using for CLK_SYS */
 255         if (reg & WM8994_SYSCLK_SRC)
 256                 clk = "AIF2CLK";
 257         else
 258                 clk = "AIF1CLK";
 259
 260         return strcmp(source->name, clk) == 0;
 261 }
 262
 263 static const char *sidetone_hpf_text[] = {
 264         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 265 };
 266
 267 static const struct soc_enum sidetone_hpf =
 268         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 269
 270 static const char *adc_hpf_text[] = {
 271         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 272 };
 273
 274 static const struct soc_enum aif1adc1_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif1adc2_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const struct soc_enum aif2adc_hpf =
 281         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 282
 283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 288
 289 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 290 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 291         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 292         .put = wm8994_put_drc_sw, \
 293         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 294
 295 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 296                              struct snd_ctl_elem_value *ucontrol)
 297 {
 298         struct soc_mixer_control *mc =
 299                 (struct soc_mixer_control *)kcontrol->private_value;
 300         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 301         int mask, ret;
 302
 303         /* Can't enable both ADC and DAC paths simultaneously */
 304         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 305                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 306                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 307         else
 308                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 309
 310         ret = snd_soc_read(codec, mc->reg);
 311         if (ret < 0)
 312                 return ret;
 313         if (ret & mask)
 314                 return -EINVAL;
 315
 316         return snd_soc_put_volsw(kcontrol, ucontrol);
 317 }
 318
 319 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 320 {
 321         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 322         struct wm8994_pdata *pdata = wm8994->pdata;
 323         int base = wm8994_drc_base[drc];
 324         int cfg = wm8994->drc_cfg[drc];
 325         int save, i;
 326
 327         /* Save any enables; the configuration should clear them. */
 328         save = snd_soc_read(codec, base);
 329         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 330                 WM8994_AIF1ADC1R_DRC_ENA;
 331
 332         for (i = 0; i < WM8994_DRC_REGS; i++)
 333                 snd_soc_update_bits(codec, base + i, 0xffff,
 334                                     pdata->drc_cfgs[cfg].regs[i]);
 335
 336         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 337                              WM8994_AIF1ADC1L_DRC_ENA |
 338                              WM8994_AIF1ADC1R_DRC_ENA, save);
 339 }
 340
 341 /* Icky as hell but saves code duplication */
 342 static int wm8994_get_drc(const char *name)
 343 {
 344         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 345                 return 0;
 346         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 347                 return 1;
 348         if (strcmp(name, "AIF2DRC Mode") == 0)
 349                 return 2;
 350         return -EINVAL;
 351 }
 352
 353 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 354                                struct snd_ctl_elem_value *ucontrol)
 355 {
 356         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 357         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 358         struct wm8994_pdata *pdata = wm8994->pdata;
 359         int drc = wm8994_get_drc(kcontrol->id.name);
 360         int value = ucontrol->value.integer.value[0];
 361
 362         if (drc < 0)
 363                 return drc;
 364
 365         if (value >= pdata->num_drc_cfgs)
 366                 return -EINVAL;
 367
 368         wm8994->drc_cfg[drc] = value;
 369
 370         wm8994_set_drc(codec, drc);
 371
 372         return 0;
 373 }
 374
 375 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 376                                struct snd_ctl_elem_value *ucontrol)
 377 {
 378         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 379         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 380         int drc = wm8994_get_drc(kcontrol->id.name);
 381
 382         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 383
 384         return 0;
 385 }
 386
 387 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 388 {
 389         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 390         struct wm8994_pdata *pdata = wm8994->pdata;
 391         int base = wm8994_retune_mobile_base[block];
 392         int iface, best, best_val, save, i, cfg;
 393
 394         if (!pdata || !wm8994->num_retune_mobile_texts)
 395                 return;
 396
 397         switch (block) {
 398         case 0:
 399         case 1:
 400                 iface = 0;
 401                 break;
 402         case 2:
 403                 iface = 1;
 404                 break;
 405         default:
 406                 return;
 407         }
 408
 409         /* Find the version of the currently selected configuration
 410          * with the nearest sample rate. */
 411         cfg = wm8994->retune_mobile_cfg[block];
 412         best = 0;
 413         best_val = INT_MAX;
 414         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 415                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 416                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 417                     abs(pdata->retune_mobile_cfgs[i].rate
 418                         - wm8994->dac_rates[iface]) < best_val) {
 419                         best = i;
 420                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 421                                        - wm8994->dac_rates[iface]);
 422                 }
 423         }
 424
 425         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 426                 block,
 427                 pdata->retune_mobile_cfgs[best].name,
 428                 pdata->retune_mobile_cfgs[best].rate,
 429                 wm8994->dac_rates[iface]);
 430
 431         /* The EQ will be disabled while reconfiguring it, remember the
 432          * current configuration.
 433          */
 434         save = snd_soc_read(codec, base);
 435         save &= WM8994_AIF1DAC1_EQ_ENA;
 436
 437         for (i = 0; i < WM8994_EQ_REGS; i++)
 438                 snd_soc_update_bits(codec, base + i, 0xffff,
 439                                 pdata->retune_mobile_cfgs[best].regs[i]);
 440
 441         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 442 }
 443
 444 /* Icky as hell but saves code duplication */
 445 static int wm8994_get_retune_mobile_block(const char *name)
 446 {
 447         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 448                 return 0;
 449         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 450                 return 1;
 451         if (strcmp(name, "AIF2 EQ Mode") == 0)
 452                 return 2;
 453         return -EINVAL;
 454 }
 455
 456 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 457                                          struct snd_ctl_elem_value *ucontrol)
 458 {
 459         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 460         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 461         struct wm8994_pdata *pdata = wm8994->pdata;
 462         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 463         int value = ucontrol->value.integer.value[0];
 464
 465         if (block < 0)
 466                 return block;
 467
 468         if (value >= pdata->num_retune_mobile_cfgs)
 469                 return -EINVAL;
 470
 471         wm8994->retune_mobile_cfg[block] = value;
 472
 473         wm8994_set_retune_mobile(codec, block);
 474
 475         return 0;
 476 }
 477
 478 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 479                                          struct snd_ctl_elem_value *ucontrol)
 480 {
 481         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 482         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 483         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 484
 485         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 486
 487         return 0;
 488 }
 489
 490 static const char *aif_chan_src_text[] = {
 491         "Left", "Right"
 492 };
 493
 494 static const struct soc_enum aif1adcl_src =
 495         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 496
 497 static const struct soc_enum aif1adcr_src =
 498         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 499
 500 static const struct soc_enum aif2adcl_src =
 501         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 502
 503 static const struct soc_enum aif2adcr_src =
 504         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 505
 506 static const struct soc_enum aif1dacl_src =
 507         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 508
 509 static const struct soc_enum aif1dacr_src =
 510         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 511
 512 static const struct soc_enum aif2dacl_src =
 513         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 514
 515 static const struct soc_enum aif2dacr_src =
 516         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 517
 518 static const char *osr_text[] = {
 519         "Low Power", "High Performance",
 520 };
 521
 522 static const struct soc_enum dac_osr =
 523         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 524
 525 static const struct soc_enum adc_osr =
 526         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 527
 528 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 529 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 530                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 531                  1, 119, 0, digital_tlv),
 532 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 533                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 534                  1, 119, 0, digital_tlv),
 535 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 536                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 537                  1, 119, 0, digital_tlv),
 538
 539 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 540 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 541 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 542 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 543
 544 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 545 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 546 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 547 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 548
 549 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 550                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 552                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 553 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 554                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 555
 556 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 557 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 558
 559 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 560 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 561 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 568 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 569 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 570
 571 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 572 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 573 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 574
 575 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 580                5, 12, 0, st_tlv),
 581 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 582                0, 12, 0, st_tlv),
 583 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 584 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 585
 586 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 587 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 588
 589 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 590 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 591
 592 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 593 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 594
 595 SOC_ENUM("ADC OSR", adc_osr),
 596 SOC_ENUM("DAC OSR", dac_osr),
 597
 598 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 599                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 600 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 601              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 602
 603 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 604                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 605 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 606              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 607
 608 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 609                6, 1, 1, wm_hubs_spkmix_tlv),
 610 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 611                2, 1, 1, wm_hubs_spkmix_tlv),
 612
 613 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 614                6, 1, 1, wm_hubs_spkmix_tlv),
 615 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 616                2, 1, 1, wm_hubs_spkmix_tlv),
 617
 618 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 625            8, 1, 0),
 626 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 627                10, 15, 0, wm8994_3d_tlv),
 628 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 629            8, 1, 0),
 630 };
 631
 632 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 638                eq_tlv),
 639 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 640                eq_tlv),
 641 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 642                eq_tlv),
 643
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 649                eq_tlv),
 650 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 651                eq_tlv),
 652 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 653                eq_tlv),
 654
 655 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 660                eq_tlv),
 661 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 662                eq_tlv),
 663 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 664                eq_tlv),
 665 };
 666
 667 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 668 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 669 };
 670
 671 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 672                          struct snd_kcontrol *kcontrol, int event)
 673 {
 674         struct snd_soc_codec *codec = w->codec;
 675
 676         switch (event) {
 677         case SND_SOC_DAPM_PRE_PMU:
 678                 return configure_clock(codec);
 679
 680         case SND_SOC_DAPM_POST_PMD:
 681                 configure_clock(codec);
 682                 break;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 689 {
 690         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 691         int enable = 1;
 692         int source = 0;  /* GCC flow analysis can't track enable */
 693         int reg, reg_r;
 694
 695         /* Only support direct DAC->headphone paths */
 696         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 697         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 698                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 699                 enable = 0;
 700         }
 701
 702         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 703         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 704                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 705                 enable = 0;
 706         }
 707
 708         /* We also need the same setting for L/R and only one path */
 709         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 710         switch (reg) {
 711         case WM8994_AIF2DACL_TO_DAC1L:
 712                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 713                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 714                 break;
 715         case WM8994_AIF1DAC2L_TO_DAC1L:
 716                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 717                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 718                 break;
 719         case WM8994_AIF1DAC1L_TO_DAC1L:
 720                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 721                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 722                 break;
 723         default:
 724                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 725                 enable = 0;
 726                 break;
 727         }
 728
 729         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 730         if (reg_r != reg) {
 731                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 732                 enable = 0;
 733         }
 734
 735         if (enable) {
 736                 dev_dbg(codec->dev, "Class W enabled\n");
 737                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 738                                     WM8994_CP_DYN_PWR |
 739                                     WM8994_CP_DYN_SRC_SEL_MASK,
 740                                     source | WM8994_CP_DYN_PWR);
 741                 wm8994->hubs.class_w = true;
 742
 743         } else {
 744                 dev_dbg(codec->dev, "Class W disabled\n");
 745                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 746                                     WM8994_CP_DYN_PWR, 0);
 747                 wm8994->hubs.class_w = false;
 748         }
 749 }
 750
 751 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 752                           struct snd_kcontrol *kcontrol, int event)
 753 {
 754         struct snd_soc_codec *codec = w->codec;
 755         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 if (wm8994->aif1clk_enable) {
 760                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 761                                             WM8994_AIF1CLK_ENA_MASK,
 762                                             WM8994_AIF1CLK_ENA);
 763                         wm8994->aif1clk_enable = 0;
 764                 }
 765                 if (wm8994->aif2clk_enable) {
 766                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 767                                             WM8994_AIF2CLK_ENA_MASK,
 768                                             WM8994_AIF2CLK_ENA);
 769                         wm8994->aif2clk_enable = 0;
 770                 }
 771                 break;
 772         }
 773
 774         /* We may also have postponed startup of DSP, handle that. */
 775         wm8958_aif_ev(w, kcontrol, event);
 776
 777         return 0;
 778 }
 779
 780 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 781                            struct snd_kcontrol *kcontrol, int event)
 782 {
 783         struct snd_soc_codec *codec = w->codec;
 784         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 785
 786         switch (event) {
 787         case SND_SOC_DAPM_POST_PMD:
 788                 if (wm8994->aif1clk_disable) {
 789                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 790                                             WM8994_AIF1CLK_ENA_MASK, 0);
 791                         wm8994->aif1clk_disable = 0;
 792                 }
 793                 if (wm8994->aif2clk_disable) {
 794                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 795                                             WM8994_AIF2CLK_ENA_MASK, 0);
 796                         wm8994->aif2clk_disable = 0;
 797                 }
 798                 break;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 805                       struct snd_kcontrol *kcontrol, int event)
 806 {
 807         struct snd_soc_codec *codec = w->codec;
 808         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 809
 810         switch (event) {
 811         case SND_SOC_DAPM_PRE_PMU:
 812                 wm8994->aif1clk_enable = 1;
 813                 break;
 814         case SND_SOC_DAPM_POST_PMD:
 815                 wm8994->aif1clk_disable = 1;
 816                 break;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 823                       struct snd_kcontrol *kcontrol, int event)
 824 {
 825         struct snd_soc_codec *codec = w->codec;
 826         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 827
 828         switch (event) {
 829         case SND_SOC_DAPM_PRE_PMU:
 830                 wm8994->aif2clk_enable = 1;
 831                 break;
 832         case SND_SOC_DAPM_POST_PMD:
 833                 wm8994->aif2clk_disable = 1;
 834                 break;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 841                       struct snd_kcontrol *kcontrol, int event)
 842 {
 843         late_enable_ev(w, kcontrol, event);
 844         return 0;
 845 }
 846
 847 static int micbias_ev(struct snd_soc_dapm_widget *w,
 848                       struct snd_kcontrol *kcontrol, int event)
 849 {
 850         late_enable_ev(w, kcontrol, event);
 851         return 0;
 852 }
 853
 854 static int dac_ev(struct snd_soc_dapm_widget *w,
 855                   struct snd_kcontrol *kcontrol, int event)
 856 {
 857         struct snd_soc_codec *codec = w->codec;
 858         unsigned int mask = 1 << w->shift;
 859
 860         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 861                             mask, mask);
 862         return 0;
 863 }
 864
 865 static const char *hp_mux_text[] = {
 866         "Mixer",
 867         "DAC",
 868 };
 869
 870 #define WM8994_HP_ENUM(xname, xenum) \
 871 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 872         .info = snd_soc_info_enum_double, \
 873         .get = snd_soc_dapm_get_enum_double, \
 874         .put = wm8994_put_hp_enum, \
 875         .private_value = (unsigned long)&xenum }
 876
 877 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 878                               struct snd_ctl_elem_value *ucontrol)
 879 {
 880         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 881         struct snd_soc_dapm_widget *w = wlist->widgets[0];
 882         struct snd_soc_codec *codec = w->codec;
 883         int ret;
 884
 885         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 886
 887         wm8994_update_class_w(codec);
 888
 889         return ret;
 890 }
 891
 892 static const struct soc_enum hpl_enum =
 893         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 894
 895 static const struct snd_kcontrol_new hpl_mux =
 896         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 897
 898 static const struct soc_enum hpr_enum =
 899         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 900
 901 static const struct snd_kcontrol_new hpr_mux =
 902         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 903
 904 static const char *adc_mux_text[] = {
 905         "ADC",
 906         "DMIC",
 907 };
 908
 909 static const struct soc_enum adc_enum =
 910         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 911
 912 static const struct snd_kcontrol_new adcl_mux =
 913         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 914
 915 static const struct snd_kcontrol_new adcr_mux =
 916         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 917
 918 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 919 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 920 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 921 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 922 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 923 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 924 };
 925
 926 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 927 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 928 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 929 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 930 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 931 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 932 };
 933
 934 /* Debugging; dump chip status after DAPM transitions */
 935 static int post_ev(struct snd_soc_dapm_widget *w,
 936             struct snd_kcontrol *kcontrol, int event)
 937 {
 938         struct snd_soc_codec *codec = w->codec;
 939         dev_dbg(codec->dev, "SRC status: %x\n",
 940                 snd_soc_read(codec,
 941                              WM8994_RATE_STATUS));
 942         return 0;
 943 }
 944
 945 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 946 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 947                 1, 1, 0),
 948 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 949                 0, 1, 0),
 950 };
 951
 952 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 953 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 954                 1, 1, 0),
 955 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 956                 0, 1, 0),
 957 };
 958
 959 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 960 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 961                 1, 1, 0),
 962 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 963                 0, 1, 0),
 964 };
 965
 966 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
 967 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 968                 1, 1, 0),
 969 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 970                 0, 1, 0),
 971 };
 972
 973 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
 974 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 975                 5, 1, 0),
 976 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 977                 4, 1, 0),
 978 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 979                 2, 1, 0),
 980 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 981                 1, 1, 0),
 982 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 983                 0, 1, 0),
 984 };
 985
 986 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
 987 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 988                 5, 1, 0),
 989 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 990                 4, 1, 0),
 991 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 992                 2, 1, 0),
 993 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 994                 1, 1, 0),
 995 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 996                 0, 1, 0),
 997 };
 998
 999 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1000 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1001         .info = snd_soc_info_volsw, \
1002         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1003         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1004
1005 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1006                               struct snd_ctl_elem_value *ucontrol)
1007 {
1008         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1009         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1010         struct snd_soc_codec *codec = w->codec;
1011         int ret;
1012
1013         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1014
1015         wm8994_update_class_w(codec);
1016
1017         return ret;
1018 }
1019
1020 static const struct snd_kcontrol_new dac1l_mix[] = {
1021 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022                       5, 1, 0),
1023 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024                       4, 1, 0),
1025 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026                       2, 1, 0),
1027 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1028                       1, 1, 0),
1029 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1030                       0, 1, 0),
1031 };
1032
1033 static const struct snd_kcontrol_new dac1r_mix[] = {
1034 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035                       5, 1, 0),
1036 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037                       4, 1, 0),
1038 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039                       2, 1, 0),
1040 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1041                       1, 1, 0),
1042 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1043                       0, 1, 0),
1044 };
1045
1046 static const char *sidetone_text[] = {
1047         "ADC/DMIC1", "DMIC2",
1048 };
1049
1050 static const struct soc_enum sidetone1_enum =
1051         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1052
1053 static const struct snd_kcontrol_new sidetone1_mux =
1054         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1055
1056 static const struct soc_enum sidetone2_enum =
1057         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1058
1059 static const struct snd_kcontrol_new sidetone2_mux =
1060         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1061
1062 static const char *aif1dac_text[] = {
1063         "AIF1DACDAT", "AIF3DACDAT",
1064 };
1065
1066 static const struct soc_enum aif1dac_enum =
1067         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1068
1069 static const struct snd_kcontrol_new aif1dac_mux =
1070         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1071
1072 static const char *aif2dac_text[] = {
1073         "AIF2DACDAT", "AIF3DACDAT",
1074 };
1075
1076 static const struct soc_enum aif2dac_enum =
1077         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1078
1079 static const struct snd_kcontrol_new aif2dac_mux =
1080         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1081
1082 static const char *aif2adc_text[] = {
1083         "AIF2ADCDAT", "AIF3DACDAT",
1084 };
1085
1086 static const struct soc_enum aif2adc_enum =
1087         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1088
1089 static const struct snd_kcontrol_new aif2adc_mux =
1090         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1091
1092 static const char *aif3adc_text[] = {
1093         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1094 };
1095
1096 static const struct soc_enum wm8994_aif3adc_enum =
1097         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1098
1099 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1100         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1101
1102 static const struct soc_enum wm8958_aif3adc_enum =
1103         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1104
1105 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1106         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1107
1108 static const char *mono_pcm_out_text[] = {
1109         "None", "AIF2ADCL", "AIF2ADCR",
1110 };
1111
1112 static const struct soc_enum mono_pcm_out_enum =
1113         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1114
1115 static const struct snd_kcontrol_new mono_pcm_out_mux =
1116         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1117
1118 static const char *aif2dac_src_text[] = {
1119         "AIF2", "AIF3",
1120 };
1121
1122 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1123 static const struct soc_enum aif2dacl_src_enum =
1124         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1125
1126 static const struct snd_kcontrol_new aif2dacl_src_mux =
1127         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1128
1129 static const struct soc_enum aif2dacr_src_enum =
1130         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1131
1132 static const struct snd_kcontrol_new aif2dacr_src_mux =
1133         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1134
1135 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1136 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1137         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1139         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1140
1141 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1146         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1148         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1149
1150 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1151 };
1152
1153 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1154 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1155 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1156 };
1157
1158 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1159 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1160         dac_ev, SND_SOC_DAPM_PRE_PMU),
1161 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1162         dac_ev, SND_SOC_DAPM_PRE_PMU),
1163 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1164         dac_ev, SND_SOC_DAPM_PRE_PMU),
1165 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1166         dac_ev, SND_SOC_DAPM_PRE_PMU),
1167 };
1168
1169 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1170 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1171 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1172 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1173 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1174 };
1175
1176 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1177 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1178                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1179 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1180                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1181 };
1182
1183 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1184 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1185 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1186 };
1187
1188 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1189 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1190 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1191 SND_SOC_DAPM_INPUT("Clock"),
1192
1193 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1194 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1195                       SND_SOC_DAPM_PRE_PMU),
1196
1197 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1198                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1199
1200 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1201 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1202 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1203
1204 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1205                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1206 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1207                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1208 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1209                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1210                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1211 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1212                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1213                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1214
1215 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1216                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1217 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1218                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1219 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1220                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1221                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1222 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1223                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1224                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1225
1226 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1227                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1228 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1229                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1230
1231 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1232                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1233 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1234                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1235
1236 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1237                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1238 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1239                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1240
1241 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1242 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1243
1244 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1245                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1246 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1247                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1248
1249 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1250                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1251 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1252                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1253 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1254                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1255                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1256 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1257                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1258                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1259
1260 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1261 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1262 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1263 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1264
1265 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1266 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1267 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1268
1269 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1270 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1271
1272 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1273
1274 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1275 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1276 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1277 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1278
1279 /* Power is done with the muxes since the ADC power also controls the
1280  * downsampling chain, the chip will automatically manage the analogue
1281  * specific portions.
1282  */
1283 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1284 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1285
1286 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1287 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1288
1289 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1290                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1291 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1292                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1293
1294 SND_SOC_DAPM_POST("Debug log", post_ev),
1295 };
1296
1297 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1298 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1299 };
1300
1301 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1302 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1303 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1304 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1305 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1306 };
1307
1308 static const struct snd_soc_dapm_route intercon[] = {
1309         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1310         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1311
1312         { "DSP1CLK", NULL, "CLK_SYS" },
1313         { "DSP2CLK", NULL, "CLK_SYS" },
1314         { "DSPINTCLK", NULL, "CLK_SYS" },
1315
1316         { "AIF1ADC1L", NULL, "AIF1CLK" },
1317         { "AIF1ADC1L", NULL, "DSP1CLK" },
1318         { "AIF1ADC1R", NULL, "AIF1CLK" },
1319         { "AIF1ADC1R", NULL, "DSP1CLK" },
1320         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1321
1322         { "AIF1DAC1L", NULL, "AIF1CLK" },
1323         { "AIF1DAC1L", NULL, "DSP1CLK" },
1324         { "AIF1DAC1R", NULL, "AIF1CLK" },
1325         { "AIF1DAC1R", NULL, "DSP1CLK" },
1326         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1327
1328         { "AIF1ADC2L", NULL, "AIF1CLK" },
1329         { "AIF1ADC2L", NULL, "DSP1CLK" },
1330         { "AIF1ADC2R", NULL, "AIF1CLK" },
1331         { "AIF1ADC2R", NULL, "DSP1CLK" },
1332         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1333
1334         { "AIF1DAC2L", NULL, "AIF1CLK" },
1335         { "AIF1DAC2L", NULL, "DSP1CLK" },
1336         { "AIF1DAC2R", NULL, "AIF1CLK" },
1337         { "AIF1DAC2R", NULL, "DSP1CLK" },
1338         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1339
1340         { "AIF2ADCL", NULL, "AIF2CLK" },
1341         { "AIF2ADCL", NULL, "DSP2CLK" },
1342         { "AIF2ADCR", NULL, "AIF2CLK" },
1343         { "AIF2ADCR", NULL, "DSP2CLK" },
1344         { "AIF2ADCR", NULL, "DSPINTCLK" },
1345
1346         { "AIF2DACL", NULL, "AIF2CLK" },
1347         { "AIF2DACL", NULL, "DSP2CLK" },
1348         { "AIF2DACR", NULL, "AIF2CLK" },
1349         { "AIF2DACR", NULL, "DSP2CLK" },
1350         { "AIF2DACR", NULL, "DSPINTCLK" },
1351
1352         { "DMIC1L", NULL, "DMIC1DAT" },
1353         { "DMIC1L", NULL, "CLK_SYS" },
1354         { "DMIC1R", NULL, "DMIC1DAT" },
1355         { "DMIC1R", NULL, "CLK_SYS" },
1356         { "DMIC2L", NULL, "DMIC2DAT" },
1357         { "DMIC2L", NULL, "CLK_SYS" },
1358         { "DMIC2R", NULL, "DMIC2DAT" },
1359         { "DMIC2R", NULL, "CLK_SYS" },
1360
1361         { "ADCL", NULL, "AIF1CLK" },
1362         { "ADCL", NULL, "DSP1CLK" },
1363         { "ADCL", NULL, "DSPINTCLK" },
1364
1365         { "ADCR", NULL, "AIF1CLK" },
1366         { "ADCR", NULL, "DSP1CLK" },
1367         { "ADCR", NULL, "DSPINTCLK" },
1368
1369         { "ADCL Mux", "ADC", "ADCL" },
1370         { "ADCL Mux", "DMIC", "DMIC1L" },
1371         { "ADCR Mux", "ADC", "ADCR" },
1372         { "ADCR Mux", "DMIC", "DMIC1R" },
1373
1374         { "DAC1L", NULL, "AIF1CLK" },
1375         { "DAC1L", NULL, "DSP1CLK" },
1376         { "DAC1L", NULL, "DSPINTCLK" },
1377
1378         { "DAC1R", NULL, "AIF1CLK" },
1379         { "DAC1R", NULL, "DSP1CLK" },
1380         { "DAC1R", NULL, "DSPINTCLK" },
1381
1382         { "DAC2L", NULL, "AIF2CLK" },
1383         { "DAC2L", NULL, "DSP2CLK" },
1384         { "DAC2L", NULL, "DSPINTCLK" },
1385
1386         { "DAC2R", NULL, "AIF2DACR" },
1387         { "DAC2R", NULL, "AIF2CLK" },
1388         { "DAC2R", NULL, "DSP2CLK" },
1389         { "DAC2R", NULL, "DSPINTCLK" },
1390
1391         { "TOCLK", NULL, "CLK_SYS" },
1392
1393         /* AIF1 outputs */
1394         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1395         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1396         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1397
1398         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1399         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1400         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1401
1402         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1403         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1404         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1405
1406         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1407         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1408         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1409
1410         /* Pin level routing for AIF3 */
1411         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1412         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1413         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1414         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1415
1416         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1417         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1418         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1419         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1420         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1421         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1422         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1423
1424         /* DAC1 inputs */
1425         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1426         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1427         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1428         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1429         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1430
1431         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1432         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1433         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1434         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1435         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1436
1437         /* DAC2/AIF2 outputs  */
1438         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1439         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1440         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1441         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1442         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1443         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1444
1445         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1446         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1447         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1448         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1449         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1450         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1451
1452         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1453         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1454         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1455         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1456
1457         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1458
1459         /* AIF3 output */
1460         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1461         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1462         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1463         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1464         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1465         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1466         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1467         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1468
1469         /* Sidetone */
1470         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1471         { "Left Sidetone", "DMIC2", "DMIC2L" },
1472         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1473         { "Right Sidetone", "DMIC2", "DMIC2R" },
1474
1475         /* Output stages */
1476         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1477         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1478
1479         { "SPKL", "DAC1 Switch", "DAC1L" },
1480         { "SPKL", "DAC2 Switch", "DAC2L" },
1481
1482         { "SPKR", "DAC1 Switch", "DAC1R" },
1483         { "SPKR", "DAC2 Switch", "DAC2R" },
1484
1485         { "Left Headphone Mux", "DAC", "DAC1L" },
1486         { "Right Headphone Mux", "DAC", "DAC1R" },
1487 };
1488
1489 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1490         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1491         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1492         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1493         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1494         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1495         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1496         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1497         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1498 };
1499
1500 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1501         { "DAC1L", NULL, "DAC1L Mixer" },
1502         { "DAC1R", NULL, "DAC1R Mixer" },
1503         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1504         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1505 };
1506
1507 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1508         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1509         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1510         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1511         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1512         { "MICBIAS", NULL, "CLK_SYS" },
1513         { "MICBIAS", NULL, "MICBIAS Supply" },
1514 };
1515
1516 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1517         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1518         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1519 };
1520
1521 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1522         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1523         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1524
1525         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1526         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1527         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1528         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1529
1530         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1531         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1532
1533         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1534 };
1535
1536 /* The size in bits of the FLL divide multiplied by 10
1537  * to allow rounding later */
1538 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1539
1540 struct fll_div {
1541         u16 outdiv;
1542         u16 n;
1543         u16 k;
1544         u16 clk_ref_div;
1545         u16 fll_fratio;
1546 };
1547
1548 static int wm8994_get_fll_config(struct fll_div *fll,
1549                                  int freq_in, int freq_out)
1550 {
1551         u64 Kpart;
1552         unsigned int K, Ndiv, Nmod;
1553
1554         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1555
1556         /* Scale the input frequency down to <= 13.5MHz */
1557         fll->clk_ref_div = 0;
1558         while (freq_in > 13500000) {
1559                 fll->clk_ref_div++;
1560                 freq_in /= 2;
1561
1562                 if (fll->clk_ref_div > 3)
1563                         return -EINVAL;
1564         }
1565         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1566
1567         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1568         fll->outdiv = 3;
1569         while (freq_out * (fll->outdiv + 1) < 90000000) {
1570                 fll->outdiv++;
1571                 if (fll->outdiv > 63)
1572                         return -EINVAL;
1573         }
1574         freq_out *= fll->outdiv + 1;
1575         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1576
1577         if (freq_in > 1000000) {
1578                 fll->fll_fratio = 0;
1579         } else if (freq_in > 256000) {
1580                 fll->fll_fratio = 1;
1581                 freq_in *= 2;
1582         } else if (freq_in > 128000) {
1583                 fll->fll_fratio = 2;
1584                 freq_in *= 4;
1585         } else if (freq_in > 64000) {
1586                 fll->fll_fratio = 3;
1587                 freq_in *= 8;
1588         } else {
1589                 fll->fll_fratio = 4;
1590                 freq_in *= 16;
1591         }
1592         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1593
1594         /* Now, calculate N.K */
1595         Ndiv = freq_out / freq_in;
1596
1597         fll->n = Ndiv;
1598         Nmod = freq_out % freq_in;
1599         pr_debug("Nmod=%d\n", Nmod);
1600
1601         /* Calculate fractional part - scale up so we can round. */
1602         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1603
1604         do_div(Kpart, freq_in);
1605
1606         K = Kpart & 0xFFFFFFFF;
1607
1608         if ((K % 10) >= 5)
1609                 K += 5;
1610
1611         /* Move down to proper range now rounding is done */
1612         fll->k = K / 10;
1613
1614         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1615
1616         return 0;
1617 }
1618
1619 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1620                           unsigned int freq_in, unsigned int freq_out)
1621 {
1622         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1623         int reg_offset, ret;
1624         struct fll_div fll;
1625         u16 reg, aif1, aif2;
1626
1627         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1628                 & WM8994_AIF1CLK_ENA;
1629
1630         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1631                 & WM8994_AIF2CLK_ENA;
1632
1633         switch (id) {
1634         case WM8994_FLL1:
1635                 reg_offset = 0;
1636                 id = 0;
1637                 break;
1638         case WM8994_FLL2:
1639                 reg_offset = 0x20;
1640                 id = 1;
1641                 break;
1642         default:
1643                 return -EINVAL;
1644         }
1645
1646         switch (src) {
1647         case 0:
1648                 /* Allow no source specification when stopping */
1649                 if (freq_out)
1650                         return -EINVAL;
1651                 src = wm8994->fll[id].src;
1652                 break;
1653         case WM8994_FLL_SRC_MCLK1:
1654         case WM8994_FLL_SRC_MCLK2:
1655         case WM8994_FLL_SRC_LRCLK:
1656         case WM8994_FLL_SRC_BCLK:
1657                 break;
1658         default:
1659                 return -EINVAL;
1660         }
1661
1662         /* Are we changing anything? */
1663         if (wm8994->fll[id].src == src &&
1664             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1665                 return 0;
1666
1667         /* If we're stopping the FLL redo the old config - no
1668          * registers will actually be written but we avoid GCC flow
1669          * analysis bugs spewing warnings.
1670          */
1671         if (freq_out)
1672                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1673         else
1674                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1675                                             wm8994->fll[id].out);
1676         if (ret < 0)
1677                 return ret;
1678
1679         /* Gate the AIF clocks while we reclock */
1680         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1681                             WM8994_AIF1CLK_ENA, 0);
1682         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1683                             WM8994_AIF2CLK_ENA, 0);
1684
1685         /* We always need to disable the FLL while reconfiguring */
1686         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1687                             WM8994_FLL1_ENA, 0);
1688
1689         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1690                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1691         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1692                             WM8994_FLL1_OUTDIV_MASK |
1693                             WM8994_FLL1_FRATIO_MASK, reg);
1694
1695         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1696
1697         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1698                             WM8994_FLL1_N_MASK,
1699                                     fll.n << WM8994_FLL1_N_SHIFT);
1700
1701         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1702                             WM8994_FLL1_REFCLK_DIV_MASK |
1703                             WM8994_FLL1_REFCLK_SRC_MASK,
1704                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1705                             (src - 1));
1706
1707         /* Enable (with fractional mode if required) */
1708         if (freq_out) {
1709                 if (fll.k)
1710                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1711                 else
1712                         reg = WM8994_FLL1_ENA;
1713                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1714                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1715                                     reg);
1716         }
1717
1718         wm8994->fll[id].in = freq_in;
1719         wm8994->fll[id].out = freq_out;
1720         wm8994->fll[id].src = src;
1721
1722         /* Enable any gated AIF clocks */
1723         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1724                             WM8994_AIF1CLK_ENA, aif1);
1725         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1726                             WM8994_AIF2CLK_ENA, aif2);
1727
1728         configure_clock(codec);
1729
1730         return 0;
1731 }
1732
1733
1734 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1735
1736 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1737                           unsigned int freq_in, unsigned int freq_out)
1738 {
1739         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1740 }
1741
1742 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1743                 int clk_id, unsigned int freq, int dir)
1744 {
1745         struct snd_soc_codec *codec = dai->codec;
1746         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1747         int i;
1748
1749         switch (dai->id) {
1750         case 1:
1751         case 2:
1752                 break;
1753
1754         default:
1755                 /* AIF3 shares clocking with AIF1/2 */
1756                 return -EINVAL;
1757         }
1758
1759         switch (clk_id) {
1760         case WM8994_SYSCLK_MCLK1:
1761                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1762                 wm8994->mclk[0] = freq;
1763                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1764                         dai->id, freq);
1765                 break;
1766
1767         case WM8994_SYSCLK_MCLK2:
1768                 /* TODO: Set GPIO AF */
1769                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1770                 wm8994->mclk[1] = freq;
1771                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1772                         dai->id, freq);
1773                 break;
1774
1775         case WM8994_SYSCLK_FLL1:
1776                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1777                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1778                 break;
1779
1780         case WM8994_SYSCLK_FLL2:
1781                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1782                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1783                 break;
1784
1785         case WM8994_SYSCLK_OPCLK:
1786                 /* Special case - a division (times 10) is given and
1787                  * no effect on main clocking.
1788                  */
1789                 if (freq) {
1790                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1791                                 if (opclk_divs[i] == freq)
1792                                         break;
1793                         if (i == ARRAY_SIZE(opclk_divs))
1794                                 return -EINVAL;
1795                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1796                                             WM8994_OPCLK_DIV_MASK, i);
1797                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1798                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1799                 } else {
1800                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1801                                             WM8994_OPCLK_ENA, 0);
1802                 }
1803
1804         default:
1805                 return -EINVAL;
1806         }
1807
1808         configure_clock(codec);
1809
1810         return 0;
1811 }
1812
1813 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1814                                  enum snd_soc_bias_level level)
1815 {
1816         struct wm8994 *control = codec->control_data;
1817         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1818
1819         switch (level) {
1820         case SND_SOC_BIAS_ON:
1821                 break;
1822
1823         case SND_SOC_BIAS_PREPARE:
1824                 /* VMID=2x40k */
1825                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1826                                     WM8994_VMID_SEL_MASK, 0x2);
1827                 break;
1828
1829         case SND_SOC_BIAS_STANDBY:
1830                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1831                         pm_runtime_get_sync(codec->dev);
1832
1833                         switch (control->type) {
1834                         case WM8994:
1835                                 if (wm8994->revision < 4) {
1836                                         /* Tweak DC servo and DSP
1837                                          * configuration for improved
1838                                          * performance. */
1839                                         snd_soc_write(codec, 0x102, 0x3);
1840                                         snd_soc_write(codec, 0x56, 0x3);
1841                                         snd_soc_write(codec, 0x817, 0);
1842                                         snd_soc_write(codec, 0x102, 0);
1843                                 }
1844                                 break;
1845
1846                         case WM8958:
1847                                 if (wm8994->revision == 0) {
1848                                         /* Optimise performance for rev A */
1849                                         snd_soc_write(codec, 0x102, 0x3);
1850                                         snd_soc_write(codec, 0xcb, 0x81);
1851                                         snd_soc_write(codec, 0x817, 0);
1852                                         snd_soc_write(codec, 0x102, 0);
1853
1854                                         snd_soc_update_bits(codec,
1855                                                             WM8958_CHARGE_PUMP_2,
1856                                                             WM8958_CP_DISCH,
1857                                                             WM8958_CP_DISCH);
1858                                 }
1859                                 break;
1860                         }
1861
1862                         /* Discharge LINEOUT1 & 2 */
1863                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1864                                             WM8994_LINEOUT1_DISCH |
1865                                             WM8994_LINEOUT2_DISCH,
1866                                             WM8994_LINEOUT1_DISCH |
1867                                             WM8994_LINEOUT2_DISCH);
1868
1869                         /* Startup bias, VMID ramp & buffer */
1870                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1871                                             WM8994_STARTUP_BIAS_ENA |
1872                                             WM8994_VMID_BUF_ENA |
1873                                             WM8994_VMID_RAMP_MASK,
1874                                             WM8994_STARTUP_BIAS_ENA |
1875                                             WM8994_VMID_BUF_ENA |
1876                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1877
1878                         /* Main bias enable, VMID=2x40k */
1879                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1880                                             WM8994_BIAS_ENA |
1881                                             WM8994_VMID_SEL_MASK,
1882                                             WM8994_BIAS_ENA | 0x2);
1883
1884                         msleep(20);
1885                 }
1886
1887                 /* VMID=2x500k */
1888                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1889                                     WM8994_VMID_SEL_MASK, 0x4);
1890
1891                 break;
1892
1893         case SND_SOC_BIAS_OFF:
1894                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1895                         /* Switch over to startup biases */
1896                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1897                                             WM8994_BIAS_SRC |
1898                                             WM8994_STARTUP_BIAS_ENA |
1899                                             WM8994_VMID_BUF_ENA |
1900                                             WM8994_VMID_RAMP_MASK,
1901                                             WM8994_BIAS_SRC |
1902                                             WM8994_STARTUP_BIAS_ENA |
1903                                             WM8994_VMID_BUF_ENA |
1904                                             (1 << WM8994_VMID_RAMP_SHIFT));
1905
1906                         /* Disable main biases */
1907                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1908                                             WM8994_BIAS_ENA |
1909                                             WM8994_VMID_SEL_MASK, 0);
1910
1911                         /* Discharge line */
1912                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1913                                             WM8994_LINEOUT1_DISCH |
1914                                             WM8994_LINEOUT2_DISCH,
1915                                             WM8994_LINEOUT1_DISCH |
1916                                             WM8994_LINEOUT2_DISCH);
1917
1918                         msleep(5);
1919
1920                         /* Switch off startup biases */
1921                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1922                                             WM8994_BIAS_SRC |
1923                                             WM8994_STARTUP_BIAS_ENA |
1924                                             WM8994_VMID_BUF_ENA |
1925                                             WM8994_VMID_RAMP_MASK, 0);
1926
1927                         wm8994->cur_fw = NULL;
1928
1929                         pm_runtime_put(codec->dev);
1930                 }
1931                 break;
1932         }
1933         codec->dapm.bias_level = level;
1934         return 0;
1935 }
1936
1937 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1938 {
1939         struct snd_soc_codec *codec = dai->codec;
1940         struct wm8994 *control = codec->control_data;
1941         int ms_reg;
1942         int aif1_reg;
1943         int ms = 0;
1944         int aif1 = 0;
1945
1946         switch (dai->id) {
1947         case 1:
1948                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1949                 aif1_reg = WM8994_AIF1_CONTROL_1;
1950                 break;
1951         case 2:
1952                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1953                 aif1_reg = WM8994_AIF2_CONTROL_1;
1954                 break;
1955         default:
1956                 return -EINVAL;
1957         }
1958
1959         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1960         case SND_SOC_DAIFMT_CBS_CFS:
1961                 break;
1962         case SND_SOC_DAIFMT_CBM_CFM:
1963                 ms = WM8994_AIF1_MSTR;
1964                 break;
1965         default:
1966                 return -EINVAL;
1967         }
1968
1969         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1970         case SND_SOC_DAIFMT_DSP_B:
1971                 aif1 |= WM8994_AIF1_LRCLK_INV;
1972         case SND_SOC_DAIFMT_DSP_A:
1973                 aif1 |= 0x18;
1974                 break;
1975         case SND_SOC_DAIFMT_I2S:
1976                 aif1 |= 0x10;
1977                 break;
1978         case SND_SOC_DAIFMT_RIGHT_J:
1979                 break;
1980         case SND_SOC_DAIFMT_LEFT_J:
1981                 aif1 |= 0x8;
1982                 break;
1983         default:
1984                 return -EINVAL;
1985         }
1986
1987         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1988         case SND_SOC_DAIFMT_DSP_A:
1989         case SND_SOC_DAIFMT_DSP_B:
1990                 /* frame inversion not valid for DSP modes */
1991                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1992                 case SND_SOC_DAIFMT_NB_NF:
1993                         break;
1994                 case SND_SOC_DAIFMT_IB_NF:
1995                         aif1 |= WM8994_AIF1_BCLK_INV;
1996                         break;
1997                 default:
1998                         return -EINVAL;
1999                 }
2000                 break;
2001
2002         case SND_SOC_DAIFMT_I2S:
2003         case SND_SOC_DAIFMT_RIGHT_J:
2004         case SND_SOC_DAIFMT_LEFT_J:
2005                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2006                 case SND_SOC_DAIFMT_NB_NF:
2007                         break;
2008                 case SND_SOC_DAIFMT_IB_IF:
2009                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2010                         break;
2011                 case SND_SOC_DAIFMT_IB_NF:
2012                         aif1 |= WM8994_AIF1_BCLK_INV;
2013                         break;
2014                 case SND_SOC_DAIFMT_NB_IF:
2015                         aif1 |= WM8994_AIF1_LRCLK_INV;
2016                         break;
2017                 default:
2018                         return -EINVAL;
2019                 }
2020                 break;
2021         default:
2022                 return -EINVAL;
2023         }
2024
2025         /* The AIF2 format configuration needs to be mirrored to AIF3
2026          * on WM8958 if it's in use so just do it all the time. */
2027         if (control->type == WM8958 && dai->id == 2)
2028                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2029                                     WM8994_AIF1_LRCLK_INV |
2030                                     WM8958_AIF3_FMT_MASK, aif1);
2031
2032         snd_soc_update_bits(codec, aif1_reg,
2033                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2034                             WM8994_AIF1_FMT_MASK,
2035                             aif1);
2036         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2037                             ms);
2038
2039         return 0;
2040 }
2041
2042 static struct {
2043         int val, rate;
2044 } srs[] = {
2045         { 0,   8000 },
2046         { 1,  11025 },
2047         { 2,  12000 },
2048         { 3,  16000 },
2049         { 4,  22050 },
2050         { 5,  24000 },
2051         { 6,  32000 },
2052         { 7,  44100 },
2053         { 8,  48000 },
2054         { 9,  88200 },
2055         { 10, 96000 },
2056 };
2057
2058 static int fs_ratios[] = {
2059         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2060 };
2061
2062 static int bclk_divs[] = {
2063         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2064         640, 880, 960, 1280, 1760, 1920
2065 };
2066
2067 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2068                             struct snd_pcm_hw_params *params,
2069                             struct snd_soc_dai *dai)
2070 {
2071         struct snd_soc_codec *codec = dai->codec;
2072         struct wm8994 *control = codec->control_data;
2073         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2074         int aif1_reg;
2075         int aif2_reg;
2076         int bclk_reg;
2077         int lrclk_reg;
2078         int rate_reg;
2079         int aif1 = 0;
2080         int aif2 = 0;
2081         int bclk = 0;
2082         int lrclk = 0;
2083         int rate_val = 0;
2084         int id = dai->id - 1;
2085
2086         int i, cur_val, best_val, bclk_rate, best;
2087
2088         switch (dai->id) {
2089         case 1:
2090                 aif1_reg = WM8994_AIF1_CONTROL_1;
2091                 aif2_reg = WM8994_AIF1_CONTROL_2;
2092                 bclk_reg = WM8994_AIF1_BCLK;
2093                 rate_reg = WM8994_AIF1_RATE;
2094                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2095                     wm8994->lrclk_shared[0]) {
2096                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2097                 } else {
2098                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2099                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2100                 }
2101                 break;
2102         case 2:
2103                 aif1_reg = WM8994_AIF2_CONTROL_1;
2104                 aif2_reg = WM8994_AIF2_CONTROL_2;
2105                 bclk_reg = WM8994_AIF2_BCLK;
2106                 rate_reg = WM8994_AIF2_RATE;
2107                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2108                     wm8994->lrclk_shared[1]) {
2109                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2110                 } else {
2111                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2112                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2113                 }
2114                 break;
2115         case 3:
2116                 switch (control->type) {
2117                 case WM8958:
2118                         aif1_reg = WM8958_AIF3_CONTROL_1;
2119                         break;
2120                 default:
2121                         return 0;
2122                 }
2123         default:
2124                 return -EINVAL;
2125         }
2126
2127         bclk_rate = params_rate(params) * 2;
2128         switch (params_format(params)) {
2129         case SNDRV_PCM_FORMAT_S16_LE:
2130                 bclk_rate *= 16;
2131                 break;
2132         case SNDRV_PCM_FORMAT_S20_3LE:
2133                 bclk_rate *= 20;
2134                 aif1 |= 0x20;
2135                 break;
2136         case SNDRV_PCM_FORMAT_S24_LE:
2137                 bclk_rate *= 24;
2138                 aif1 |= 0x40;
2139                 break;
2140         case SNDRV_PCM_FORMAT_S32_LE:
2141                 bclk_rate *= 32;
2142                 aif1 |= 0x60;
2143                 break;
2144         default:
2145                 return -EINVAL;
2146         }
2147
2148         /* Try to find an appropriate sample rate; look for an exact match. */
2149         for (i = 0; i < ARRAY_SIZE(srs); i++)
2150                 if (srs[i].rate == params_rate(params))
2151                         break;
2152         if (i == ARRAY_SIZE(srs))
2153                 return -EINVAL;
2154         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2155
2156         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2157         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2158                 dai->id, wm8994->aifclk[id], bclk_rate);
2159
2160         if (params_channels(params) == 1 &&
2161             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2162                 aif2 |= WM8994_AIF1_MONO;
2163
2164         if (wm8994->aifclk[id] == 0) {
2165                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2166                 return -EINVAL;
2167         }
2168
2169         /* AIFCLK/fs ratio; look for a close match in either direction */
2170         best = 0;
2171         best_val = abs((fs_ratios[0] * params_rate(params))
2172                        - wm8994->aifclk[id]);
2173         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2174                 cur_val = abs((fs_ratios[i] * params_rate(params))
2175                               - wm8994->aifclk[id]);
2176                 if (cur_val >= best_val)
2177                         continue;
2178                 best = i;
2179                 best_val = cur_val;
2180         }
2181         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2182                 dai->id, fs_ratios[best]);
2183         rate_val |= best;
2184
2185         /* We may not get quite the right frequency if using
2186          * approximate clocks so look for the closest match that is
2187          * higher than the target (we need to ensure that there enough
2188          * BCLKs to clock out the samples).
2189          */
2190         best = 0;
2191         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2192                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2193                 if (cur_val < 0) /* BCLK table is sorted */
2194                         break;
2195                 best = i;
2196         }
2197         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2198         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2199                 bclk_divs[best], bclk_rate);
2200         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2201
2202         lrclk = bclk_rate / params_rate(params);
2203         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2204                 lrclk, bclk_rate / lrclk);
2205
2206         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2207         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2208         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2209         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2210                             lrclk);
2211         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2212                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2213
2214         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2215                 switch (dai->id) {
2216                 case 1:
2217                         wm8994->dac_rates[0] = params_rate(params);
2218                         wm8994_set_retune_mobile(codec, 0);
2219                         wm8994_set_retune_mobile(codec, 1);
2220                         break;
2221                 case 2:
2222                         wm8994->dac_rates[1] = params_rate(params);
2223                         wm8994_set_retune_mobile(codec, 2);
2224                         break;
2225                 }
2226         }
2227
2228         return 0;
2229 }
2230
2231 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2232                                  struct snd_pcm_hw_params *params,
2233                                  struct snd_soc_dai *dai)
2234 {
2235         struct snd_soc_codec *codec = dai->codec;
2236         struct wm8994 *control = codec->control_data;
2237         int aif1_reg;
2238         int aif1 = 0;
2239
2240         switch (dai->id) {
2241         case 3:
2242                 switch (control->type) {
2243                 case WM8958:
2244                         aif1_reg = WM8958_AIF3_CONTROL_1;
2245                         break;
2246                 default:
2247                         return 0;
2248                 }
2249         default:
2250                 return 0;
2251         }
2252
2253         switch (params_format(params)) {
2254         case SNDRV_PCM_FORMAT_S16_LE:
2255                 break;
2256         case SNDRV_PCM_FORMAT_S20_3LE:
2257                 aif1 |= 0x20;
2258                 break;
2259         case SNDRV_PCM_FORMAT_S24_LE:
2260                 aif1 |= 0x40;
2261                 break;
2262         case SNDRV_PCM_FORMAT_S32_LE:
2263                 aif1 |= 0x60;
2264                 break;
2265         default:
2266                 return -EINVAL;
2267         }
2268
2269         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2270 }
2271
2272 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2273 {
2274         struct snd_soc_codec *codec = codec_dai->codec;
2275         int mute_reg;
2276         int reg;
2277
2278         switch (codec_dai->id) {
2279         case 1:
2280                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2281                 break;
2282         case 2:
2283                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2284                 break;
2285         default:
2286                 return -EINVAL;
2287         }
2288
2289         if (mute)
2290                 reg = WM8994_AIF1DAC1_MUTE;
2291         else
2292                 reg = 0;
2293
2294         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2295
2296         return 0;
2297 }
2298
2299 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2300 {
2301         struct snd_soc_codec *codec = codec_dai->codec;
2302         int reg, val, mask;
2303
2304         switch (codec_dai->id) {
2305         case 1:
2306                 reg = WM8994_AIF1_MASTER_SLAVE;
2307                 mask = WM8994_AIF1_TRI;
2308                 break;
2309         case 2:
2310                 reg = WM8994_AIF2_MASTER_SLAVE;
2311                 mask = WM8994_AIF2_TRI;
2312                 break;
2313         case 3:
2314                 reg = WM8994_POWER_MANAGEMENT_6;
2315                 mask = WM8994_AIF3_TRI;
2316                 break;
2317         default:
2318                 return -EINVAL;
2319         }
2320
2321         if (tristate)
2322                 val = mask;
2323         else
2324                 val = 0;
2325
2326         return snd_soc_update_bits(codec, reg, mask, val);
2327 }
2328
2329 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2330
2331 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2332                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2333
2334 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2335         .set_sysclk     = wm8994_set_dai_sysclk,
2336         .set_fmt        = wm8994_set_dai_fmt,
2337         .hw_params      = wm8994_hw_params,
2338         .digital_mute   = wm8994_aif_mute,
2339         .set_pll        = wm8994_set_fll,
2340         .set_tristate   = wm8994_set_tristate,
2341 };
2342
2343 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2344         .set_sysclk     = wm8994_set_dai_sysclk,
2345         .set_fmt        = wm8994_set_dai_fmt,
2346         .hw_params      = wm8994_hw_params,
2347         .digital_mute   = wm8994_aif_mute,
2348         .set_pll        = wm8994_set_fll,
2349         .set_tristate   = wm8994_set_tristate,
2350 };
2351
2352 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2353         .hw_params      = wm8994_aif3_hw_params,
2354         .set_tristate   = wm8994_set_tristate,
2355 };
2356
2357 static struct snd_soc_dai_driver wm8994_dai[] = {
2358         {
2359                 .name = "wm8994-aif1",
2360                 .id = 1,
2361                 .playback = {
2362                         .stream_name = "AIF1 Playback",
2363                         .channels_min = 1,
2364                         .channels_max = 2,
2365                         .rates = WM8994_RATES,
2366                         .formats = WM8994_FORMATS,
2367                 },
2368                 .capture = {
2369                         .stream_name = "AIF1 Capture",
2370                         .channels_min = 1,
2371                         .channels_max = 2,
2372                         .rates = WM8994_RATES,
2373                         .formats = WM8994_FORMATS,
2374                  },
2375                 .ops = &wm8994_aif1_dai_ops,
2376         },
2377         {
2378                 .name = "wm8994-aif2",
2379                 .id = 2,
2380                 .playback = {
2381                         .stream_name = "AIF2 Playback",
2382                         .channels_min = 1,
2383                         .channels_max = 2,
2384                         .rates = WM8994_RATES,
2385                         .formats = WM8994_FORMATS,
2386                 },
2387                 .capture = {
2388                         .stream_name = "AIF2 Capture",
2389                         .channels_min = 1,
2390                         .channels_max = 2,
2391                         .rates = WM8994_RATES,
2392                         .formats = WM8994_FORMATS,
2393                 },
2394                 .ops = &wm8994_aif2_dai_ops,
2395         },
2396         {
2397                 .name = "wm8994-aif3",
2398                 .id = 3,
2399                 .playback = {
2400                         .stream_name = "AIF3 Playback",
2401                         .channels_min = 1,
2402                         .channels_max = 2,
2403                         .rates = WM8994_RATES,
2404                         .formats = WM8994_FORMATS,
2405                 },
2406                 .capture = {
2407                         .stream_name = "AIF3 Capture",
2408                         .channels_min = 1,
2409                         .channels_max = 2,
2410                         .rates = WM8994_RATES,
2411                         .formats = WM8994_FORMATS,
2412                 },
2413                 .ops = &wm8994_aif3_dai_ops,
2414         }
2415 };
2416
2417 #ifdef CONFIG_PM
2418 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2419 {
2420         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2421         struct wm8994 *control = codec->control_data;
2422         int i, ret;
2423
2424         switch (control->type) {
2425         case WM8994:
2426                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2427                 break;
2428         case WM8958:
2429                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2430                                     WM8958_MICD_ENA, 0);
2431                 break;
2432         }
2433
2434         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2435                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2436                        sizeof(struct wm8994_fll_config));
2437                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2438                 if (ret < 0)
2439                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2440                                  i + 1, ret);
2441         }
2442
2443         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2444
2445         return 0;
2446 }
2447
2448 static int wm8994_resume(struct snd_soc_codec *codec)
2449 {
2450         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2451         struct wm8994 *control = codec->control_data;
2452         int i, ret;
2453         unsigned int val, mask;
2454
2455         if (wm8994->revision < 4) {
2456                 /* force a HW read */
2457                 val = wm8994_reg_read(codec->control_data,
2458                                       WM8994_POWER_MANAGEMENT_5);
2459
2460                 /* modify the cache only */
2461                 codec->cache_only = 1;
2462                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2463                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2464                 val &= mask;
2465                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2466                                     mask, val);
2467                 codec->cache_only = 0;
2468         }
2469
2470         /* Restore the registers */
2471         ret = snd_soc_cache_sync(codec);
2472         if (ret != 0)
2473                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2474
2475         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2476
2477         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2478                 if (!wm8994->fll_suspend[i].out)
2479                         continue;
2480
2481                 ret = _wm8994_set_fll(codec, i + 1,
2482                                      wm8994->fll_suspend[i].src,
2483                                      wm8994->fll_suspend[i].in,
2484                                      wm8994->fll_suspend[i].out);
2485                 if (ret < 0)
2486                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2487                                  i + 1, ret);
2488         }
2489
2490         switch (control->type) {
2491         case WM8994:
2492                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2493                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2494                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2495                 break;
2496         case WM8958:
2497                 if (wm8994->jack_cb)
2498                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2499                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2500                 break;
2501         }
2502
2503         return 0;
2504 }
2505 #else
2506 #define wm8994_suspend NULL
2507 #define wm8994_resume NULL
2508 #endif
2509
2510 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2511 {
2512         struct snd_soc_codec *codec = wm8994->codec;
2513         struct wm8994_pdata *pdata = wm8994->pdata;
2514         struct snd_kcontrol_new controls[] = {
2515                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2516                              wm8994->retune_mobile_enum,
2517                              wm8994_get_retune_mobile_enum,
2518                              wm8994_put_retune_mobile_enum),
2519                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2520                              wm8994->retune_mobile_enum,
2521                              wm8994_get_retune_mobile_enum,
2522                              wm8994_put_retune_mobile_enum),
2523                 SOC_ENUM_EXT("AIF2 EQ Mode",
2524                              wm8994->retune_mobile_enum,
2525                              wm8994_get_retune_mobile_enum,
2526                              wm8994_put_retune_mobile_enum),
2527         };
2528         int ret, i, j;
2529         const char **t;
2530
2531         /* We need an array of texts for the enum API but the number
2532          * of texts is likely to be less than the number of
2533          * configurations due to the sample rate dependency of the
2534          * configurations. */
2535         wm8994->num_retune_mobile_texts = 0;
2536         wm8994->retune_mobile_texts = NULL;
2537         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2538                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2539                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2540                                    wm8994->retune_mobile_texts[j]) == 0)
2541                                 break;
2542                 }
2543
2544                 if (j != wm8994->num_retune_mobile_texts)
2545                         continue;
2546
2547                 /* Expand the array... */
2548                 t = krealloc(wm8994->retune_mobile_texts,
2549                              sizeof(char *) *
2550                              (wm8994->num_retune_mobile_texts + 1),
2551                              GFP_KERNEL);
2552                 if (t == NULL)
2553                         continue;
2554
2555                 /* ...store the new entry... */
2556                 t[wm8994->num_retune_mobile_texts] =
2557                         pdata->retune_mobile_cfgs[i].name;
2558
2559                 /* ...and remember the new version. */
2560                 wm8994->num_retune_mobile_texts++;
2561                 wm8994->retune_mobile_texts = t;
2562         }
2563
2564         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2565                 wm8994->num_retune_mobile_texts);
2566
2567         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2568         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2569
2570         ret = snd_soc_add_controls(wm8994->codec, controls,
2571                                    ARRAY_SIZE(controls));
2572         if (ret != 0)
2573                 dev_err(wm8994->codec->dev,
2574                         "Failed to add ReTune Mobile controls: %d\n", ret);
2575 }
2576
2577 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2578 {
2579         struct snd_soc_codec *codec = wm8994->codec;
2580         struct wm8994_pdata *pdata = wm8994->pdata;
2581         int ret, i;
2582
2583         if (!pdata)
2584                 return;
2585
2586         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2587                                       pdata->lineout2_diff,
2588                                       pdata->lineout1fb,
2589                                       pdata->lineout2fb,
2590                                       pdata->jd_scthr,
2591                                       pdata->jd_thr,
2592                                       pdata->micbias1_lvl,
2593                                       pdata->micbias2_lvl);
2594
2595         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2596
2597         if (pdata->num_drc_cfgs) {
2598                 struct snd_kcontrol_new controls[] = {
2599                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2600                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2601                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2602                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2603                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2604                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2605                 };
2606
2607                 /* We need an array of texts for the enum API */
2608                 wm8994->drc_texts = kmalloc(sizeof(char *)
2609                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2610                 if (!wm8994->drc_texts) {
2611                         dev_err(wm8994->codec->dev,
2612                                 "Failed to allocate %d DRC config texts\n",
2613                                 pdata->num_drc_cfgs);
2614                         return;
2615                 }
2616
2617                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2618                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2619
2620                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2621                 wm8994->drc_enum.texts = wm8994->drc_texts;
2622
2623                 ret = snd_soc_add_controls(wm8994->codec, controls,
2624                                            ARRAY_SIZE(controls));
2625                 if (ret != 0)
2626                         dev_err(wm8994->codec->dev,
2627                                 "Failed to add DRC mode controls: %d\n", ret);
2628
2629                 for (i = 0; i < WM8994_NUM_DRC; i++)
2630                         wm8994_set_drc(codec, i);
2631         }
2632
2633         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2634                 pdata->num_retune_mobile_cfgs);
2635
2636         if (pdata->num_retune_mobile_cfgs)
2637                 wm8994_handle_retune_mobile_pdata(wm8994);
2638         else
2639                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2640                                      ARRAY_SIZE(wm8994_eq_controls));
2641
2642         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2643                 if (pdata->micbias[i]) {
2644                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2645                                 pdata->micbias[i] & 0xffff);
2646                 }
2647         }
2648 }
2649
2650 /**
2651  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2652  *
2653  * @codec:   WM8994 codec
2654  * @jack:    jack to report detection events on
2655  * @micbias: microphone bias to detect on
2656  * @det:     value to report for presence detection
2657  * @shrt:    value to report for short detection
2658  *
2659  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2660  * being used to bring out signals to the processor then only platform
2661  * data configuration is needed for WM8994 and processor GPIOs should
2662  * be configured using snd_soc_jack_add_gpios() instead.
2663  *
2664  * Configuration of detection levels is available via the micbias1_lvl
2665  * and micbias2_lvl platform data members.
2666  */
2667 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2668                       int micbias, int det, int shrt)
2669 {
2670         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2671         struct wm8994_micdet *micdet;
2672         struct wm8994 *control = codec->control_data;
2673         int reg;
2674
2675         if (control->type != WM8994)
2676                 return -EINVAL;
2677
2678         switch (micbias) {
2679         case 1:
2680                 micdet = &wm8994->micdet[0];
2681                 break;
2682         case 2:
2683                 micdet = &wm8994->micdet[1];
2684                 break;
2685         default:
2686                 return -EINVAL;
2687         }
2688
2689         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2690                 micbias, det, shrt);
2691
2692         /* Store the configuration */
2693         micdet->jack = jack;
2694         micdet->det = det;
2695         micdet->shrt = shrt;
2696
2697         /* If either of the jacks is set up then enable detection */
2698         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2699                 reg = WM8994_MICD_ENA;
2700         else
2701                 reg = 0;
2702
2703         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2704
2705         return 0;
2706 }
2707 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2708
2709 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2710 {
2711         struct wm8994_priv *priv = data;
2712         struct snd_soc_codec *codec = priv->codec;
2713         int reg;
2714         int report;
2715
2716 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2717         trace_snd_soc_jack_irq(dev_name(codec->dev));
2718 #endif
2719
2720         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2721         if (reg < 0) {
2722                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2723                         reg);
2724                 return IRQ_HANDLED;
2725         }
2726
2727         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2728
2729         report = 0;
2730         if (reg & WM8994_MIC1_DET_STS)
2731                 report |= priv->micdet[0].det;
2732         if (reg & WM8994_MIC1_SHRT_STS)
2733                 report |= priv->micdet[0].shrt;
2734         snd_soc_jack_report(priv->micdet[0].jack, report,
2735                             priv->micdet[0].det | priv->micdet[0].shrt);
2736
2737         report = 0;
2738         if (reg & WM8994_MIC2_DET_STS)
2739                 report |= priv->micdet[1].det;
2740         if (reg & WM8994_MIC2_SHRT_STS)
2741                 report |= priv->micdet[1].shrt;
2742         snd_soc_jack_report(priv->micdet[1].jack, report,
2743                             priv->micdet[1].det | priv->micdet[1].shrt);
2744
2745         return IRQ_HANDLED;
2746 }
2747
2748 /* Default microphone detection handler for WM8958 - the user can
2749  * override this if they wish.
2750  */
2751 static void wm8958_default_micdet(u16 status, void *data)
2752 {
2753         struct snd_soc_codec *codec = data;
2754         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2755         int report = 0;
2756
2757         /* If nothing present then clear our statuses */
2758         if (!(status & WM8958_MICD_STS))
2759                 goto done;
2760
2761         report = SND_JACK_MICROPHONE;
2762
2763         /* Everything else is buttons; just assign slots */
2764         if (status & 0x1c0)
2765                 report |= SND_JACK_BTN_0;
2766
2767 done:
2768         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2769                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2770 }
2771
2772 /**
2773  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2774  *
2775  * @codec:   WM8958 codec
2776  * @jack:    jack to report detection events on
2777  *
2778  * Enable microphone detection functionality for the WM8958.  By
2779  * default simple detection which supports the detection of up to 6
2780  * buttons plus video and microphone functionality is supported.
2781  *
2782  * The WM8958 has an advanced jack detection facility which is able to
2783  * support complex accessory detection, especially when used in
2784  * conjunction with external circuitry.  In order to provide maximum
2785  * flexiblity a callback is provided which allows a completely custom
2786  * detection algorithm.
2787  */
2788 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2789                       wm8958_micdet_cb cb, void *cb_data)
2790 {
2791         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2792         struct wm8994 *control = codec->control_data;
2793
2794         if (control->type != WM8958)
2795                 return -EINVAL;
2796
2797         if (jack) {
2798                 if (!cb) {
2799                         dev_dbg(codec->dev, "Using default micdet callback\n");
2800                         cb = wm8958_default_micdet;
2801                         cb_data = codec;
2802                 }
2803
2804                 wm8994->micdet[0].jack = jack;
2805                 wm8994->jack_cb = cb;
2806                 wm8994->jack_cb_data = cb_data;
2807
2808                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2809                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2810         } else {
2811                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2812                                     WM8958_MICD_ENA, 0);
2813         }
2814
2815         return 0;
2816 }
2817 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2818
2819 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2820 {
2821         struct wm8994_priv *wm8994 = data;
2822         struct snd_soc_codec *codec = wm8994->codec;
2823         int reg;
2824
2825         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2826         if (reg < 0) {
2827                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2828                         reg);
2829                 return IRQ_NONE;
2830         }
2831
2832         if (!(reg & WM8958_MICD_VALID)) {
2833                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2834                 goto out;
2835         }
2836
2837 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2838         trace_snd_soc_jack_irq(dev_name(codec->dev));
2839 #endif
2840
2841         if (wm8994->jack_cb)
2842                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2843         else
2844                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2845
2846 out:
2847         return IRQ_HANDLED;
2848 }
2849
2850 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2851 {
2852         struct wm8994 *control;
2853         struct wm8994_priv *wm8994;
2854         struct snd_soc_dapm_context *dapm = &codec->dapm;
2855         int ret, i;
2856
2857         codec->control_data = dev_get_drvdata(codec->dev->parent);
2858         control = codec->control_data;
2859
2860         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2861         if (wm8994 == NULL)
2862                 return -ENOMEM;
2863         snd_soc_codec_set_drvdata(codec, wm8994);
2864
2865         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2866         wm8994->codec = codec;
2867
2868         if (wm8994->pdata && wm8994->pdata->micdet_irq)
2869                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2870         else if (wm8994->pdata && wm8994->pdata->irq_base)
2871                 wm8994->micdet_irq = wm8994->pdata->irq_base +
2872                                      WM8994_IRQ_MIC1_DET;
2873
2874         pm_runtime_enable(codec->dev);
2875         pm_runtime_resume(codec->dev);
2876
2877         /* Read our current status back from the chip - we don't want to
2878          * reset as this may interfere with the GPIO or LDO operation. */
2879         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2880                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2881                         continue;
2882
2883                 ret = wm8994_reg_read(codec->control_data, i);
2884                 if (ret <= 0)
2885                         continue;
2886
2887                 ret = snd_soc_cache_write(codec, i, ret);
2888                 if (ret != 0) {
2889                         dev_err(codec->dev,
2890                                 "Failed to initialise cache for 0x%x: %d\n",
2891                                 i, ret);
2892                         goto err;
2893                 }
2894         }
2895
2896         /* Set revision-specific configuration */
2897         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2898         switch (control->type) {
2899         case WM8994:
2900                 switch (wm8994->revision) {
2901                 case 2:
2902                 case 3:
2903                         wm8994->hubs.dcs_codes = -5;
2904                         wm8994->hubs.hp_startup_mode = 1;
2905                         wm8994->hubs.dcs_readback_mode = 1;
2906                         break;
2907                 default:
2908                         wm8994->hubs.dcs_readback_mode = 1;
2909                         break;
2910                 }
2911
2912         case WM8958:
2913                 wm8994->hubs.dcs_readback_mode = 1;
2914                 break;
2915
2916         default:
2917                 break;
2918         }
2919
2920         switch (control->type) {
2921         case WM8994:
2922                 if (wm8994->micdet_irq) {
2923                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2924                                                    wm8994_mic_irq,
2925                                                    IRQF_TRIGGER_RISING,
2926                                                    "Mic1 detect",
2927                                                    wm8994);
2928                         if (ret != 0)
2929                                 dev_warn(codec->dev,
2930                                          "Failed to request Mic1 detect IRQ: %d\n",
2931                                          ret);
2932                 }
2933
2934                 ret = wm8994_request_irq(codec->control_data,
2935                                          WM8994_IRQ_MIC1_SHRT,
2936                                          wm8994_mic_irq, "Mic 1 short",
2937                                          wm8994);
2938                 if (ret != 0)
2939                         dev_warn(codec->dev,
2940                                  "Failed to request Mic1 short IRQ: %d\n",
2941                                  ret);
2942
2943                 ret = wm8994_request_irq(codec->control_data,
2944                                          WM8994_IRQ_MIC2_DET,
2945                                          wm8994_mic_irq, "Mic 2 detect",
2946                                          wm8994);
2947                 if (ret != 0)
2948                         dev_warn(codec->dev,
2949                                  "Failed to request Mic2 detect IRQ: %d\n",
2950                                  ret);
2951
2952                 ret = wm8994_request_irq(codec->control_data,
2953                                          WM8994_IRQ_MIC2_SHRT,
2954                                          wm8994_mic_irq, "Mic 2 short",
2955                                          wm8994);
2956                 if (ret != 0)
2957                         dev_warn(codec->dev,
2958                                  "Failed to request Mic2 short IRQ: %d\n",
2959                                  ret);
2960                 break;
2961
2962         case WM8958:
2963                 if (wm8994->micdet_irq) {
2964                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2965                                                    wm8958_mic_irq,
2966                                                    IRQF_TRIGGER_RISING,
2967                                                    "Mic detect",
2968                                                    wm8994);
2969                         if (ret != 0)
2970                                 dev_warn(codec->dev,
2971                                          "Failed to request Mic detect IRQ: %d\n",
2972                                          ret);
2973                 }
2974         }
2975
2976         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
2977          * configured on init - if a system wants to do this dynamically
2978          * at runtime we can deal with that then.
2979          */
2980         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2981         if (ret < 0) {
2982                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
2983                 goto err_irq;
2984         }
2985         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2986                 wm8994->lrclk_shared[0] = 1;
2987                 wm8994_dai[0].symmetric_rates = 1;
2988         } else {
2989                 wm8994->lrclk_shared[0] = 0;
2990         }
2991
2992         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2993         if (ret < 0) {
2994                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
2995                 goto err_irq;
2996         }
2997         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2998                 wm8994->lrclk_shared[1] = 1;
2999                 wm8994_dai[1].symmetric_rates = 1;
3000         } else {
3001                 wm8994->lrclk_shared[1] = 0;
3002         }
3003
3004         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3005
3006         /* Latch volume updates (right only; we always do left then right). */
3007         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3008                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3009         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3010                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3011         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3012                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3013         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3014                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3015         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3016                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3017         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3018                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3019         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3020                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3021         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3022                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3023         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3024                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3025         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3026                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3027         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3028                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3029         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3030                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3031         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3032                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3033         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3034                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3035         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3036                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3037         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3038                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3039
3040         /* Set the low bit of the 3D stereo depth so TLV matches */
3041         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3042                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3043                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3044         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3045                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3046                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3047         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3048                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3049                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3050
3051         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3052          * behaviour on idle TDM clock cycles. */
3053         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3054                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3055
3056         wm8994_update_class_w(codec);
3057
3058         wm8994_handle_pdata(wm8994);
3059
3060         wm_hubs_add_analogue_controls(codec);
3061         snd_soc_add_controls(codec, wm8994_snd_controls,
3062                              ARRAY_SIZE(wm8994_snd_controls));
3063         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3064                                   ARRAY_SIZE(wm8994_dapm_widgets));
3065
3066         switch (control->type) {
3067         case WM8994:
3068                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3069                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3070                 if (wm8994->revision < 4) {
3071                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3072                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3073                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3074                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3075                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3076                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3077                 } else {
3078                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3079                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3080                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3081                                                   ARRAY_SIZE(wm8994_adc_widgets));
3082                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3083                                                   ARRAY_SIZE(wm8994_dac_widgets));
3084                 }
3085                 break;
3086         case WM8958:
3087                 snd_soc_add_controls(codec, wm8958_snd_controls,
3088                                      ARRAY_SIZE(wm8958_snd_controls));
3089                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3090                                           ARRAY_SIZE(wm8958_dapm_widgets));
3091                 if (wm8994->revision < 1) {
3092                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3093                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3094                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3095                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3096                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3097                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3098                 } else {
3099                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3100                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3101                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3102                                                   ARRAY_SIZE(wm8994_adc_widgets));
3103                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3104                                                   ARRAY_SIZE(wm8994_dac_widgets));
3105                 }
3106                 break;
3107         }
3108
3109
3110         wm_hubs_add_analogue_routes(codec, 0, 0);
3111         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3112
3113         switch (control->type) {
3114         case WM8994:
3115                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3116                                         ARRAY_SIZE(wm8994_intercon));
3117
3118                 if (wm8994->revision < 4) {
3119                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3120                                                 ARRAY_SIZE(wm8994_revd_intercon));
3121                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3122                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3123                 } else {
3124                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3125                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3126                 }
3127                 break;
3128         case WM8958:
3129                 if (wm8994->revision < 1) {
3130                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3131                                                 ARRAY_SIZE(wm8994_revd_intercon));
3132                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3133                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3134                 } else {
3135                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3136                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3137                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3138                                                 ARRAY_SIZE(wm8958_intercon));
3139                 }
3140
3141                 wm8958_dsp2_init(codec);
3142                 break;
3143         }
3144
3145         return 0;
3146
3147 err_irq:
3148         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3149         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3150         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3151         if (wm8994->micdet_irq)
3152                 free_irq(wm8994->micdet_irq, wm8994);
3153 err:
3154         kfree(wm8994);
3155         return ret;
3156 }
3157
3158 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3159 {
3160         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3161         struct wm8994 *control = codec->control_data;
3162
3163         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3164
3165         pm_runtime_disable(codec->dev);
3166
3167         switch (control->type) {
3168         case WM8994:
3169                 if (wm8994->micdet_irq)
3170                         free_irq(wm8994->micdet_irq, wm8994);
3171                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3172                                 wm8994);
3173                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3174                                 wm8994);
3175                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3176                                 wm8994);
3177                 break;
3178
3179         case WM8958:
3180                 if (wm8994->micdet_irq)
3181                         free_irq(wm8994->micdet_irq, wm8994);
3182                 break;
3183         }
3184         if (wm8994->mbc)
3185                 release_firmware(wm8994->mbc);
3186         if (wm8994->mbc_vss)
3187                 release_firmware(wm8994->mbc_vss);
3188         if (wm8994->enh_eq)
3189                 release_firmware(wm8994->enh_eq);
3190         kfree(wm8994->retune_mobile_texts);
3191         kfree(wm8994->drc_texts);
3192         kfree(wm8994);
3193
3194         return 0;
3195 }
3196
3197 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3198         .probe =        wm8994_codec_probe,
3199         .remove =       wm8994_codec_remove,
3200         .suspend =      wm8994_suspend,
3201         .resume =       wm8994_resume,
3202         .read =         wm8994_read,
3203         .write =        wm8994_write,
3204         .readable_register = wm8994_readable,
3205         .volatile_register = wm8994_volatile,
3206         .set_bias_level = wm8994_set_bias_level,
3207
3208         .reg_cache_size = WM8994_CACHE_SIZE,
3209         .reg_cache_default = wm8994_reg_defaults,
3210         .reg_word_size = 2,
3211         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3212 };
3213
3214 static int __devinit wm8994_probe(struct platform_device *pdev)
3215 {
3216         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3217                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3218 }
3219
3220 static int __devexit wm8994_remove(struct platform_device *pdev)
3221 {
3222         snd_soc_unregister_codec(&pdev->dev);
3223         return 0;
3224 }
3225
3226 static struct platform_driver wm8994_codec_driver = {
3227         .driver = {
3228                    .name = "wm8994-codec",
3229                    .owner = THIS_MODULE,
3230                    },
3231         .probe = wm8994_probe,
3232         .remove = __devexit_p(wm8994_remove),
3233 };
3234
3235 static __init int wm8994_init(void)
3236 {
3237         return platform_driver_register(&wm8994_codec_driver);
3238 }
3239 module_init(wm8994_init);
3240
3241 static __exit void wm8994_exit(void)
3242 {
3243         platform_driver_unregister(&wm8994_codec_driver);
3244 }
3245 module_exit(wm8994_exit);
3246
3247
3248 MODULE_DESCRIPTION("ASoC WM8994 driver");
3249 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3250 MODULE_LICENSE("GPL");
3251 MODULE_ALIAS("platform:wm8994-codec");