sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static int wm8994_drc_base[] = {
  50         WM8994_AIF1_DRC1_1,
  51         WM8994_AIF1_DRC2_1,
  52         WM8994_AIF2_DRC_1,
  53 };
  54
  55 static int wm8994_retune_mobile_base[] = {
  56         WM8994_AIF1_DAC1_EQ_GAINS_1,
  57         WM8994_AIF1_DAC2_EQ_GAINS_1,
  58         WM8994_AIF2_EQ_GAINS_1,
  59 };
  60
  61 static void wm8958_default_micdet(u16 status, void *data);
  62
  63 static const struct wm8958_micd_rate micdet_rates[] = {
  64         { 32768,       true,  1, 4 },
  65         { 32768,       false, 1, 1 },
  66         { 44100 * 256, true,  7, 10 },
  67         { 44100 * 256, false, 7, 10 },
  68 };
  69
  70 static const struct wm8958_micd_rate jackdet_rates[] = {
  71         { 32768,       true,  0, 1 },
  72         { 32768,       false, 0, 1 },
  73         { 44100 * 256, true,  7, 10 },
  74         { 44100 * 256, false, 7, 10 },
  75 };
  76
  77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
  78 {
  79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  80         int best, i, sysclk, val;
  81         bool idle;
  82         const struct wm8958_micd_rate *rates;
  83         int num_rates;
  84
  85         if (wm8994->jack_cb != wm8958_default_micdet)
  86                 return;
  87
  88         idle = !wm8994->jack_mic;
  89
  90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
  91         if (sysclk & WM8994_SYSCLK_SRC)
  92                 sysclk = wm8994->aifclk[1];
  93         else
  94                 sysclk = wm8994->aifclk[0];
  95
  96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
  97                 rates = wm8994->pdata->micd_rates;
  98                 num_rates = wm8994->pdata->num_micd_rates;
  99         } else if (wm8994->jackdet) {
 100                 rates = jackdet_rates;
 101                 num_rates = ARRAY_SIZE(jackdet_rates);
 102         } else {
 103                 rates = micdet_rates;
 104                 num_rates = ARRAY_SIZE(micdet_rates);
 105         }
 106
 107         best = 0;
 108         for (i = 0; i < num_rates; i++) {
 109                 if (rates[i].idle != idle)
 110                         continue;
 111                 if (abs(rates[i].sysclk - sysclk) <
 112                     abs(rates[best].sysclk - sysclk))
 113                         best = i;
 114                 else if (rates[best].idle != idle)
 115                         best = i;
 116         }
 117
 118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 120
 121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 122                             WM8958_MICD_BIAS_STARTTIME_MASK |
 123                             WM8958_MICD_RATE_MASK, val);
 124 }
 125
 126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 127 {
 128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 129         int rate;
 130         int reg1 = 0;
 131         int offset;
 132
 133         if (aif)
 134                 offset = 4;
 135         else
 136                 offset = 0;
 137
 138         switch (wm8994->sysclk[aif]) {
 139         case WM8994_SYSCLK_MCLK1:
 140                 rate = wm8994->mclk[0];
 141                 break;
 142
 143         case WM8994_SYSCLK_MCLK2:
 144                 reg1 |= 0x8;
 145                 rate = wm8994->mclk[1];
 146                 break;
 147
 148         case WM8994_SYSCLK_FLL1:
 149                 reg1 |= 0x10;
 150                 rate = wm8994->fll[0].out;
 151                 break;
 152
 153         case WM8994_SYSCLK_FLL2:
 154                 reg1 |= 0x18;
 155                 rate = wm8994->fll[1].out;
 156                 break;
 157
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         if (rate >= 13500000) {
 163                 rate /= 2;
 164                 reg1 |= WM8994_AIF1CLK_DIV;
 165
 166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 167                         aif + 1, rate);
 168         }
 169
 170         wm8994->aifclk[aif] = rate;
 171
 172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 174                             reg1);
 175
 176         return 0;
 177 }
 178
 179 static int configure_clock(struct snd_soc_codec *codec)
 180 {
 181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 182         int change, new;
 183
 184         /* Bring up the AIF clocks first */
 185         configure_aif_clock(codec, 0);
 186         configure_aif_clock(codec, 1);
 187
 188         /* Then switch CLK_SYS over to the higher of them; a change
 189          * can only happen as a result of a clocking change which can
 190          * only be made outside of DAPM so we can safely redo the
 191          * clocking.
 192          */
 193
 194         /* If they're equal it doesn't matter which is used */
 195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 196                 wm8958_micd_set_rate(codec);
 197                 return 0;
 198         }
 199
 200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 201                 new = WM8994_SYSCLK_SRC;
 202         else
 203                 new = 0;
 204
 205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 206                                      WM8994_SYSCLK_SRC, new);
 207         if (change)
 208                 snd_soc_dapm_sync(&codec->dapm);
 209
 210         wm8958_micd_set_rate(codec);
 211
 212         return 0;
 213 }
 214
 215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 216                          struct snd_soc_dapm_widget *sink)
 217 {
 218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 219         const char *clk;
 220
 221         /* Check what we're currently using for CLK_SYS */
 222         if (reg & WM8994_SYSCLK_SRC)
 223                 clk = "AIF2CLK";
 224         else
 225                 clk = "AIF1CLK";
 226
 227         return strcmp(source->name, clk) == 0;
 228 }
 229
 230 static const char *sidetone_hpf_text[] = {
 231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 232 };
 233
 234 static const struct soc_enum sidetone_hpf =
 235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 236
 237 static const char *adc_hpf_text[] = {
 238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 239 };
 240
 241 static const struct soc_enum aif1adc1_hpf =
 242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 243
 244 static const struct soc_enum aif1adc2_hpf =
 245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 246
 247 static const struct soc_enum aif2adc_hpf =
 248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 249
 250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 257
 258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 261         .put = wm8994_put_drc_sw, \
 262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 263
 264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 265                              struct snd_ctl_elem_value *ucontrol)
 266 {
 267         struct soc_mixer_control *mc =
 268                 (struct soc_mixer_control *)kcontrol->private_value;
 269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 270         int mask, ret;
 271
 272         /* Can't enable both ADC and DAC paths simultaneously */
 273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 276         else
 277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 278
 279         ret = snd_soc_read(codec, mc->reg);
 280         if (ret < 0)
 281                 return ret;
 282         if (ret & mask)
 283                 return -EINVAL;
 284
 285         return snd_soc_put_volsw(kcontrol, ucontrol);
 286 }
 287
 288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 289 {
 290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 291         struct wm8994_pdata *pdata = wm8994->pdata;
 292         int base = wm8994_drc_base[drc];
 293         int cfg = wm8994->drc_cfg[drc];
 294         int save, i;
 295
 296         /* Save any enables; the configuration should clear them. */
 297         save = snd_soc_read(codec, base);
 298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 299                 WM8994_AIF1ADC1R_DRC_ENA;
 300
 301         for (i = 0; i < WM8994_DRC_REGS; i++)
 302                 snd_soc_update_bits(codec, base + i, 0xffff,
 303                                     pdata->drc_cfgs[cfg].regs[i]);
 304
 305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 306                              WM8994_AIF1ADC1L_DRC_ENA |
 307                              WM8994_AIF1ADC1R_DRC_ENA, save);
 308 }
 309
 310 /* Icky as hell but saves code duplication */
 311 static int wm8994_get_drc(const char *name)
 312 {
 313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 314                 return 0;
 315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 316                 return 1;
 317         if (strcmp(name, "AIF2DRC Mode") == 0)
 318                 return 2;
 319         return -EINVAL;
 320 }
 321
 322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 323                                struct snd_ctl_elem_value *ucontrol)
 324 {
 325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 327         struct wm8994_pdata *pdata = wm8994->pdata;
 328         int drc = wm8994_get_drc(kcontrol->id.name);
 329         int value = ucontrol->value.integer.value[0];
 330
 331         if (drc < 0)
 332                 return drc;
 333
 334         if (value >= pdata->num_drc_cfgs)
 335                 return -EINVAL;
 336
 337         wm8994->drc_cfg[drc] = value;
 338
 339         wm8994_set_drc(codec, drc);
 340
 341         return 0;
 342 }
 343
 344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 345                                struct snd_ctl_elem_value *ucontrol)
 346 {
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 349         int drc = wm8994_get_drc(kcontrol->id.name);
 350
 351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 352
 353         return 0;
 354 }
 355
 356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 357 {
 358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 359         struct wm8994_pdata *pdata = wm8994->pdata;
 360         int base = wm8994_retune_mobile_base[block];
 361         int iface, best, best_val, save, i, cfg;
 362
 363         if (!pdata || !wm8994->num_retune_mobile_texts)
 364                 return;
 365
 366         switch (block) {
 367         case 0:
 368         case 1:
 369                 iface = 0;
 370                 break;
 371         case 2:
 372                 iface = 1;
 373                 break;
 374         default:
 375                 return;
 376         }
 377
 378         /* Find the version of the currently selected configuration
 379          * with the nearest sample rate. */
 380         cfg = wm8994->retune_mobile_cfg[block];
 381         best = 0;
 382         best_val = INT_MAX;
 383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 386                     abs(pdata->retune_mobile_cfgs[i].rate
 387                         - wm8994->dac_rates[iface]) < best_val) {
 388                         best = i;
 389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 390                                        - wm8994->dac_rates[iface]);
 391                 }
 392         }
 393
 394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 395                 block,
 396                 pdata->retune_mobile_cfgs[best].name,
 397                 pdata->retune_mobile_cfgs[best].rate,
 398                 wm8994->dac_rates[iface]);
 399
 400         /* The EQ will be disabled while reconfiguring it, remember the
 401          * current configuration.
 402          */
 403         save = snd_soc_read(codec, base);
 404         save &= WM8994_AIF1DAC1_EQ_ENA;
 405
 406         for (i = 0; i < WM8994_EQ_REGS; i++)
 407                 snd_soc_update_bits(codec, base + i, 0xffff,
 408                                 pdata->retune_mobile_cfgs[best].regs[i]);
 409
 410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 411 }
 412
 413 /* Icky as hell but saves code duplication */
 414 static int wm8994_get_retune_mobile_block(const char *name)
 415 {
 416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 417                 return 0;
 418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 419                 return 1;
 420         if (strcmp(name, "AIF2 EQ Mode") == 0)
 421                 return 2;
 422         return -EINVAL;
 423 }
 424
 425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 426                                          struct snd_ctl_elem_value *ucontrol)
 427 {
 428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 430         struct wm8994_pdata *pdata = wm8994->pdata;
 431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 432         int value = ucontrol->value.integer.value[0];
 433
 434         if (block < 0)
 435                 return block;
 436
 437         if (value >= pdata->num_retune_mobile_cfgs)
 438                 return -EINVAL;
 439
 440         wm8994->retune_mobile_cfg[block] = value;
 441
 442         wm8994_set_retune_mobile(codec, block);
 443
 444         return 0;
 445 }
 446
 447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 448                                          struct snd_ctl_elem_value *ucontrol)
 449 {
 450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 453
 454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 455
 456         return 0;
 457 }
 458
 459 static const char *aif_chan_src_text[] = {
 460         "Left", "Right"
 461 };
 462
 463 static const struct soc_enum aif1adcl_src =
 464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 465
 466 static const struct soc_enum aif1adcr_src =
 467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 468
 469 static const struct soc_enum aif2adcl_src =
 470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 471
 472 static const struct soc_enum aif2adcr_src =
 473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 474
 475 static const struct soc_enum aif1dacl_src =
 476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 477
 478 static const struct soc_enum aif1dacr_src =
 479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 480
 481 static const struct soc_enum aif2dacl_src =
 482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 483
 484 static const struct soc_enum aif2dacr_src =
 485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 486
 487 static const char *osr_text[] = {
 488         "Low Power", "High Performance",
 489 };
 490
 491 static const struct soc_enum dac_osr =
 492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 493
 494 static const struct soc_enum adc_osr =
 495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 496
 497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 500                  1, 119, 0, digital_tlv),
 501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 503                  1, 119, 0, digital_tlv),
 504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 506                  1, 119, 0, digital_tlv),
 507
 508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 512
 513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 517
 518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 524
 525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 527
 528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 531
 532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 535
 536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 539
 540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 543
 544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 545                5, 12, 0, st_tlv),
 546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 547                0, 12, 0, st_tlv),
 548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 549                5, 12, 0, st_tlv),
 550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 551                0, 12, 0, st_tlv),
 552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 554
 555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 557
 558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 560
 561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 563
 564 SOC_ENUM("ADC OSR", adc_osr),
 565 SOC_ENUM("DAC OSR", dac_osr),
 566
 567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 571
 572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 576
 577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 578                6, 1, 1, wm_hubs_spkmix_tlv),
 579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 580                2, 1, 1, wm_hubs_spkmix_tlv),
 581
 582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 583                6, 1, 1, wm_hubs_spkmix_tlv),
 584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 585                2, 1, 1, wm_hubs_spkmix_tlv),
 586
 587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 588                10, 15, 0, wm8994_3d_tlv),
 589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 590            8, 1, 0),
 591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 592                10, 15, 0, wm8994_3d_tlv),
 593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 594            8, 1, 0),
 595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 596                10, 15, 0, wm8994_3d_tlv),
 597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 598            8, 1, 0),
 599 };
 600
 601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 603                eq_tlv),
 604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 605                eq_tlv),
 606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 607                eq_tlv),
 608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 609                eq_tlv),
 610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 611                eq_tlv),
 612
 613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 614                eq_tlv),
 615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 616                eq_tlv),
 617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 618                eq_tlv),
 619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 620                eq_tlv),
 621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 622                eq_tlv),
 623
 624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 625                eq_tlv),
 626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 627                eq_tlv),
 628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 629                eq_tlv),
 630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 631                eq_tlv),
 632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 633                eq_tlv),
 634 };
 635
 636 static const char *wm8958_ng_text[] = {
 637         "30ms", "125ms", "250ms", "500ms",
 638 };
 639
 640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 643
 644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 647
 648 static const struct soc_enum wm8958_aif2dac_ng_hold =
 649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 651
 652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 654
 655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 660                7, 1, ng_tlv),
 661
 662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 667                7, 1, ng_tlv),
 668
 669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 674                7, 1, ng_tlv),
 675 };
 676
 677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 679                mixin_boost_tlv),
 680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 681                mixin_boost_tlv),
 682 };
 683
 684 /* We run all mode setting through a function to enforce audio mode */
 685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 686 {
 687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 688
 689         if (wm8994->active_refcount)
 690                 mode = WM1811_JACKDET_MODE_AUDIO;
 691
 692         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 693                             WM1811_JACKDET_MODE_MASK, mode);
 694
 695         if (mode == WM1811_JACKDET_MODE_MIC)
 696                 msleep(2);
 697 }
 698
 699 static void active_reference(struct snd_soc_codec *codec)
 700 {
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702
 703         mutex_lock(&wm8994->accdet_lock);
 704
 705         wm8994->active_refcount++;
 706
 707         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 708                 wm8994->active_refcount);
 709
 710         if (wm8994->active_refcount == 1) {
 711                 /* If we're using jack detection go into audio mode */
 712                 if (wm8994->jackdet && wm8994->jack_cb) {
 713                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 714                                             WM1811_JACKDET_MODE_MASK,
 715                                             WM1811_JACKDET_MODE_AUDIO);
 716                         msleep(2);
 717                 }
 718         }
 719
 720         mutex_unlock(&wm8994->accdet_lock);
 721 }
 722
 723 static void active_dereference(struct snd_soc_codec *codec)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726         u16 mode;
 727
 728         mutex_lock(&wm8994->accdet_lock);
 729
 730         wm8994->active_refcount--;
 731
 732         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 733                 wm8994->active_refcount);
 734
 735         if (wm8994->active_refcount == 0) {
 736                 /* Go into appropriate detection only mode */
 737                 if (wm8994->jackdet && wm8994->jack_cb) {
 738                         if (wm8994->jack_mic || wm8994->mic_detecting)
 739                                 mode = WM1811_JACKDET_MODE_MIC;
 740                         else
 741                                 mode = WM1811_JACKDET_MODE_JACK;
 742
 743                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 744                                             WM1811_JACKDET_MODE_MASK,
 745                                             mode);
 746                 }
 747         }
 748
 749         mutex_unlock(&wm8994->accdet_lock);
 750 }
 751
 752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 753                          struct snd_kcontrol *kcontrol, int event)
 754 {
 755         struct snd_soc_codec *codec = w->codec;
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 return configure_clock(codec);
 760
 761         case SND_SOC_DAPM_POST_PMD:
 762                 configure_clock(codec);
 763                 break;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void vmid_reference(struct snd_soc_codec *codec)
 770 {
 771         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 772
 773         pm_runtime_get_sync(codec->dev);
 774
 775         wm8994->vmid_refcount++;
 776
 777         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 778                 wm8994->vmid_refcount);
 779
 780         if (wm8994->vmid_refcount == 1) {
 781                 /* Startup bias, VMID ramp & buffer */
 782                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 783                                     WM8994_STARTUP_BIAS_ENA |
 784                                     WM8994_VMID_BUF_ENA |
 785                                     WM8994_VMID_RAMP_MASK,
 786                                     WM8994_STARTUP_BIAS_ENA |
 787                                     WM8994_VMID_BUF_ENA |
 788                                     (0x3 << WM8994_VMID_RAMP_SHIFT));
 789
 790                 /* Main bias enable, VMID=2x40k */
 791                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 792                                     WM8994_BIAS_ENA |
 793                                     WM8994_VMID_SEL_MASK,
 794                                     WM8994_BIAS_ENA | 0x2);
 795
 796                 msleep(20);
 797         }
 798 }
 799
 800 static void vmid_dereference(struct snd_soc_codec *codec)
 801 {
 802         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 803
 804         wm8994->vmid_refcount--;
 805
 806         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 807                 wm8994->vmid_refcount);
 808
 809         if (wm8994->vmid_refcount == 0) {
 810                 /* Switch over to startup biases */
 811                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 812                                     WM8994_BIAS_SRC |
 813                                     WM8994_STARTUP_BIAS_ENA |
 814                                     WM8994_VMID_BUF_ENA |
 815                                     WM8994_VMID_RAMP_MASK,
 816                                     WM8994_BIAS_SRC |
 817                                     WM8994_STARTUP_BIAS_ENA |
 818                                     WM8994_VMID_BUF_ENA |
 819                                     (1 << WM8994_VMID_RAMP_SHIFT));
 820
 821                 /* Disable main biases */
 822                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 823                                     WM8994_BIAS_ENA |
 824                                     WM8994_VMID_SEL_MASK, 0);
 825
 826                 /* Discharge line */
 827                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 828                                     WM8994_LINEOUT1_DISCH |
 829                                     WM8994_LINEOUT2_DISCH,
 830                                     WM8994_LINEOUT1_DISCH |
 831                                     WM8994_LINEOUT2_DISCH);
 832
 833                 msleep(5);
 834
 835                 /* Switch off startup biases */
 836                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 837                                     WM8994_BIAS_SRC |
 838                                     WM8994_STARTUP_BIAS_ENA |
 839                                     WM8994_VMID_BUF_ENA |
 840                                     WM8994_VMID_RAMP_MASK, 0);
 841         }
 842
 843         pm_runtime_put(codec->dev);
 844 }
 845
 846 static int vmid_event(struct snd_soc_dapm_widget *w,
 847                       struct snd_kcontrol *kcontrol, int event)
 848 {
 849         struct snd_soc_codec *codec = w->codec;
 850
 851         switch (event) {
 852         case SND_SOC_DAPM_PRE_PMU:
 853                 vmid_reference(codec);
 854                 break;
 855
 856         case SND_SOC_DAPM_POST_PMD:
 857                 vmid_dereference(codec);
 858                 break;
 859         }
 860
 861         return 0;
 862 }
 863
 864 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 865 {
 866         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 867         int enable = 1;
 868         int source = 0;  /* GCC flow analysis can't track enable */
 869         int reg, reg_r;
 870
 871         /* Only support direct DAC->headphone paths */
 872         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 873         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 874                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 875                 enable = 0;
 876         }
 877
 878         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 879         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 880                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 881                 enable = 0;
 882         }
 883
 884         /* We also need the same setting for L/R and only one path */
 885         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 886         switch (reg) {
 887         case WM8994_AIF2DACL_TO_DAC1L:
 888                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 889                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 890                 break;
 891         case WM8994_AIF1DAC2L_TO_DAC1L:
 892                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 893                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 894                 break;
 895         case WM8994_AIF1DAC1L_TO_DAC1L:
 896                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 897                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 898                 break;
 899         default:
 900                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 901                 enable = 0;
 902                 break;
 903         }
 904
 905         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 906         if (reg_r != reg) {
 907                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 908                 enable = 0;
 909         }
 910
 911         if (enable) {
 912                 dev_dbg(codec->dev, "Class W enabled\n");
 913                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 914                                     WM8994_CP_DYN_PWR |
 915                                     WM8994_CP_DYN_SRC_SEL_MASK,
 916                                     source | WM8994_CP_DYN_PWR);
 917                 wm8994->hubs.class_w = true;
 918
 919         } else {
 920                 dev_dbg(codec->dev, "Class W disabled\n");
 921                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 922                                     WM8994_CP_DYN_PWR, 0);
 923                 wm8994->hubs.class_w = false;
 924         }
 925 }
 926
 927 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 928                           struct snd_kcontrol *kcontrol, int event)
 929 {
 930         struct snd_soc_codec *codec = w->codec;
 931         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 932
 933         switch (event) {
 934         case SND_SOC_DAPM_PRE_PMU:
 935                 if (wm8994->aif1clk_enable) {
 936                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 937                                             WM8994_AIF1CLK_ENA_MASK,
 938                                             WM8994_AIF1CLK_ENA);
 939                         wm8994->aif1clk_enable = 0;
 940                 }
 941                 if (wm8994->aif2clk_enable) {
 942                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 943                                             WM8994_AIF2CLK_ENA_MASK,
 944                                             WM8994_AIF2CLK_ENA);
 945                         wm8994->aif2clk_enable = 0;
 946                 }
 947                 break;
 948         }
 949
 950         /* We may also have postponed startup of DSP, handle that. */
 951         wm8958_aif_ev(w, kcontrol, event);
 952
 953         return 0;
 954 }
 955
 956 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 957                            struct snd_kcontrol *kcontrol, int event)
 958 {
 959         struct snd_soc_codec *codec = w->codec;
 960         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 961
 962         switch (event) {
 963         case SND_SOC_DAPM_POST_PMD:
 964                 if (wm8994->aif1clk_disable) {
 965                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 966                                             WM8994_AIF1CLK_ENA_MASK, 0);
 967                         wm8994->aif1clk_disable = 0;
 968                 }
 969                 if (wm8994->aif2clk_disable) {
 970                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 971                                             WM8994_AIF2CLK_ENA_MASK, 0);
 972                         wm8994->aif2clk_disable = 0;
 973                 }
 974                 break;
 975         }
 976
 977         return 0;
 978 }
 979
 980 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 981                       struct snd_kcontrol *kcontrol, int event)
 982 {
 983         struct snd_soc_codec *codec = w->codec;
 984         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 985
 986         switch (event) {
 987         case SND_SOC_DAPM_PRE_PMU:
 988                 wm8994->aif1clk_enable = 1;
 989                 break;
 990         case SND_SOC_DAPM_POST_PMD:
 991                 wm8994->aif1clk_disable = 1;
 992                 break;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 999                       struct snd_kcontrol *kcontrol, int event)
1000 {
1001         struct snd_soc_codec *codec = w->codec;
1002         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1003
1004         switch (event) {
1005         case SND_SOC_DAPM_PRE_PMU:
1006                 wm8994->aif2clk_enable = 1;
1007                 break;
1008         case SND_SOC_DAPM_POST_PMD:
1009                 wm8994->aif2clk_disable = 1;
1010                 break;
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1017                       struct snd_kcontrol *kcontrol, int event)
1018 {
1019         late_enable_ev(w, kcontrol, event);
1020         return 0;
1021 }
1022
1023 static int micbias_ev(struct snd_soc_dapm_widget *w,
1024                       struct snd_kcontrol *kcontrol, int event)
1025 {
1026         late_enable_ev(w, kcontrol, event);
1027         return 0;
1028 }
1029
1030 static int dac_ev(struct snd_soc_dapm_widget *w,
1031                   struct snd_kcontrol *kcontrol, int event)
1032 {
1033         struct snd_soc_codec *codec = w->codec;
1034         unsigned int mask = 1 << w->shift;
1035
1036         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1037                             mask, mask);
1038         return 0;
1039 }
1040
1041 static const char *hp_mux_text[] = {
1042         "Mixer",
1043         "DAC",
1044 };
1045
1046 #define WM8994_HP_ENUM(xname, xenum) \
1047 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1048         .info = snd_soc_info_enum_double, \
1049         .get = snd_soc_dapm_get_enum_double, \
1050         .put = wm8994_put_hp_enum, \
1051         .private_value = (unsigned long)&xenum }
1052
1053 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1054                               struct snd_ctl_elem_value *ucontrol)
1055 {
1056         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1057         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1058         struct snd_soc_codec *codec = w->codec;
1059         int ret;
1060
1061         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1062
1063         wm8994_update_class_w(codec);
1064
1065         return ret;
1066 }
1067
1068 static const struct soc_enum hpl_enum =
1069         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1070
1071 static const struct snd_kcontrol_new hpl_mux =
1072         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1073
1074 static const struct soc_enum hpr_enum =
1075         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1076
1077 static const struct snd_kcontrol_new hpr_mux =
1078         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1079
1080 static const char *adc_mux_text[] = {
1081         "ADC",
1082         "DMIC",
1083 };
1084
1085 static const struct soc_enum adc_enum =
1086         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1087
1088 static const struct snd_kcontrol_new adcl_mux =
1089         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1090
1091 static const struct snd_kcontrol_new adcr_mux =
1092         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1093
1094 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1095 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1096 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1097 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1098 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1099 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1100 };
1101
1102 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1103 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1104 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1105 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1106 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1107 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1108 };
1109
1110 /* Debugging; dump chip status after DAPM transitions */
1111 static int post_ev(struct snd_soc_dapm_widget *w,
1112             struct snd_kcontrol *kcontrol, int event)
1113 {
1114         struct snd_soc_codec *codec = w->codec;
1115         dev_dbg(codec->dev, "SRC status: %x\n",
1116                 snd_soc_read(codec,
1117                              WM8994_RATE_STATUS));
1118         return 0;
1119 }
1120
1121 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1122 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1123                 1, 1, 0),
1124 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1125                 0, 1, 0),
1126 };
1127
1128 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1129 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1130                 1, 1, 0),
1131 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1132                 0, 1, 0),
1133 };
1134
1135 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1136 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1137                 1, 1, 0),
1138 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1139                 0, 1, 0),
1140 };
1141
1142 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1143 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1144                 1, 1, 0),
1145 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1146                 0, 1, 0),
1147 };
1148
1149 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1150 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1151                 5, 1, 0),
1152 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1153                 4, 1, 0),
1154 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1155                 2, 1, 0),
1156 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1157                 1, 1, 0),
1158 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1159                 0, 1, 0),
1160 };
1161
1162 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1163 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1164                 5, 1, 0),
1165 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1166                 4, 1, 0),
1167 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1168                 2, 1, 0),
1169 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1170                 1, 1, 0),
1171 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1172                 0, 1, 0),
1173 };
1174
1175 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1176 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1177         .info = snd_soc_info_volsw, \
1178         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1179         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1180
1181 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1182                               struct snd_ctl_elem_value *ucontrol)
1183 {
1184         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1185         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1186         struct snd_soc_codec *codec = w->codec;
1187         int ret;
1188
1189         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1190
1191         wm8994_update_class_w(codec);
1192
1193         return ret;
1194 }
1195
1196 static const struct snd_kcontrol_new dac1l_mix[] = {
1197 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1198                       5, 1, 0),
1199 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1200                       4, 1, 0),
1201 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1202                       2, 1, 0),
1203 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1204                       1, 1, 0),
1205 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1206                       0, 1, 0),
1207 };
1208
1209 static const struct snd_kcontrol_new dac1r_mix[] = {
1210 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1211                       5, 1, 0),
1212 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1213                       4, 1, 0),
1214 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1215                       2, 1, 0),
1216 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1217                       1, 1, 0),
1218 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1219                       0, 1, 0),
1220 };
1221
1222 static const char *sidetone_text[] = {
1223         "ADC/DMIC1", "DMIC2",
1224 };
1225
1226 static const struct soc_enum sidetone1_enum =
1227         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1228
1229 static const struct snd_kcontrol_new sidetone1_mux =
1230         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1231
1232 static const struct soc_enum sidetone2_enum =
1233         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1234
1235 static const struct snd_kcontrol_new sidetone2_mux =
1236         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1237
1238 static const char *aif1dac_text[] = {
1239         "AIF1DACDAT", "AIF3DACDAT",
1240 };
1241
1242 static const struct soc_enum aif1dac_enum =
1243         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1244
1245 static const struct snd_kcontrol_new aif1dac_mux =
1246         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1247
1248 static const char *aif2dac_text[] = {
1249         "AIF2DACDAT", "AIF3DACDAT",
1250 };
1251
1252 static const struct soc_enum aif2dac_enum =
1253         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1254
1255 static const struct snd_kcontrol_new aif2dac_mux =
1256         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1257
1258 static const char *aif2adc_text[] = {
1259         "AIF2ADCDAT", "AIF3DACDAT",
1260 };
1261
1262 static const struct soc_enum aif2adc_enum =
1263         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1264
1265 static const struct snd_kcontrol_new aif2adc_mux =
1266         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1267
1268 static const char *aif3adc_text[] = {
1269         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1270 };
1271
1272 static const struct soc_enum wm8994_aif3adc_enum =
1273         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1274
1275 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1276         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1277
1278 static const struct soc_enum wm8958_aif3adc_enum =
1279         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1280
1281 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1282         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1283
1284 static const char *mono_pcm_out_text[] = {
1285         "None", "AIF2ADCL", "AIF2ADCR",
1286 };
1287
1288 static const struct soc_enum mono_pcm_out_enum =
1289         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1290
1291 static const struct snd_kcontrol_new mono_pcm_out_mux =
1292         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1293
1294 static const char *aif2dac_src_text[] = {
1295         "AIF2", "AIF3",
1296 };
1297
1298 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1299 static const struct soc_enum aif2dacl_src_enum =
1300         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1301
1302 static const struct snd_kcontrol_new aif2dacl_src_mux =
1303         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1304
1305 static const struct soc_enum aif2dacr_src_enum =
1306         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1307
1308 static const struct snd_kcontrol_new aif2dacr_src_mux =
1309         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1310
1311 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1312 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1313         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1314 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1315         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1316
1317 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1318         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1319 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1320         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1321 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1322         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1323 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1324         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1325 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1326         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1327
1328 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1329                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1330                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1331 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1332                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1333                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1334 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1335                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1336 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1337                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338
1339 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1340 };
1341
1342 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1343 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1344 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1345 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1346 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1347                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1348 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1349                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1350 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1351 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1352 };
1353
1354 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1355 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1356         dac_ev, SND_SOC_DAPM_PRE_PMU),
1357 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1358         dac_ev, SND_SOC_DAPM_PRE_PMU),
1359 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1360         dac_ev, SND_SOC_DAPM_PRE_PMU),
1361 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1362         dac_ev, SND_SOC_DAPM_PRE_PMU),
1363 };
1364
1365 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1366 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1367 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1368 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1369 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1370 };
1371
1372 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1373 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1374                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1375 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1376                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1377 };
1378
1379 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1380 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1381 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1382 };
1383
1384 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1385 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1386 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1387 SND_SOC_DAPM_INPUT("Clock"),
1388
1389 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1390                       SND_SOC_DAPM_PRE_PMU),
1391 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1392                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1393
1394 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1395                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1396
1397 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1398 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1399 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1400
1401 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1402                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1403 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1404                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1405 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1406                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1407                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1408 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1409                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1410                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1411
1412 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1413                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1414 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1415                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1416 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1417                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1418                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1419 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1420                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1421                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1422
1423 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1424                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1425 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1426                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1427
1428 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1429                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1430 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1431                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1432
1433 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1434                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1435 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1436                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1437
1438 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1439 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1440
1441 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1442                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1443 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1444                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1445
1446 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1447                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1448 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1449                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1450 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1451                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1452                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1453 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1454                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1455                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1456
1457 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1458 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1459 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1460 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1461
1462 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1463 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1464 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1465
1466 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1467 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1468
1469 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1470
1471 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1472 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1473 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1474 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1475
1476 /* Power is done with the muxes since the ADC power also controls the
1477  * downsampling chain, the chip will automatically manage the analogue
1478  * specific portions.
1479  */
1480 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1481 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1482
1483 SND_SOC_DAPM_POST("Debug log", post_ev),
1484 };
1485
1486 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1487 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1488 };
1489
1490 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1491 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1492 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1493 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1494 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1495 };
1496
1497 static const struct snd_soc_dapm_route intercon[] = {
1498         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1499         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1500
1501         { "DSP1CLK", NULL, "CLK_SYS" },
1502         { "DSP2CLK", NULL, "CLK_SYS" },
1503         { "DSPINTCLK", NULL, "CLK_SYS" },
1504
1505         { "AIF1ADC1L", NULL, "AIF1CLK" },
1506         { "AIF1ADC1L", NULL, "DSP1CLK" },
1507         { "AIF1ADC1R", NULL, "AIF1CLK" },
1508         { "AIF1ADC1R", NULL, "DSP1CLK" },
1509         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1510
1511         { "AIF1DAC1L", NULL, "AIF1CLK" },
1512         { "AIF1DAC1L", NULL, "DSP1CLK" },
1513         { "AIF1DAC1R", NULL, "AIF1CLK" },
1514         { "AIF1DAC1R", NULL, "DSP1CLK" },
1515         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1516
1517         { "AIF1ADC2L", NULL, "AIF1CLK" },
1518         { "AIF1ADC2L", NULL, "DSP1CLK" },
1519         { "AIF1ADC2R", NULL, "AIF1CLK" },
1520         { "AIF1ADC2R", NULL, "DSP1CLK" },
1521         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1522
1523         { "AIF1DAC2L", NULL, "AIF1CLK" },
1524         { "AIF1DAC2L", NULL, "DSP1CLK" },
1525         { "AIF1DAC2R", NULL, "AIF1CLK" },
1526         { "AIF1DAC2R", NULL, "DSP1CLK" },
1527         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1528
1529         { "AIF2ADCL", NULL, "AIF2CLK" },
1530         { "AIF2ADCL", NULL, "DSP2CLK" },
1531         { "AIF2ADCR", NULL, "AIF2CLK" },
1532         { "AIF2ADCR", NULL, "DSP2CLK" },
1533         { "AIF2ADCR", NULL, "DSPINTCLK" },
1534
1535         { "AIF2DACL", NULL, "AIF2CLK" },
1536         { "AIF2DACL", NULL, "DSP2CLK" },
1537         { "AIF2DACR", NULL, "AIF2CLK" },
1538         { "AIF2DACR", NULL, "DSP2CLK" },
1539         { "AIF2DACR", NULL, "DSPINTCLK" },
1540
1541         { "DMIC1L", NULL, "DMIC1DAT" },
1542         { "DMIC1L", NULL, "CLK_SYS" },
1543         { "DMIC1R", NULL, "DMIC1DAT" },
1544         { "DMIC1R", NULL, "CLK_SYS" },
1545         { "DMIC2L", NULL, "DMIC2DAT" },
1546         { "DMIC2L", NULL, "CLK_SYS" },
1547         { "DMIC2R", NULL, "DMIC2DAT" },
1548         { "DMIC2R", NULL, "CLK_SYS" },
1549
1550         { "ADCL", NULL, "AIF1CLK" },
1551         { "ADCL", NULL, "DSP1CLK" },
1552         { "ADCL", NULL, "DSPINTCLK" },
1553
1554         { "ADCR", NULL, "AIF1CLK" },
1555         { "ADCR", NULL, "DSP1CLK" },
1556         { "ADCR", NULL, "DSPINTCLK" },
1557
1558         { "ADCL Mux", "ADC", "ADCL" },
1559         { "ADCL Mux", "DMIC", "DMIC1L" },
1560         { "ADCR Mux", "ADC", "ADCR" },
1561         { "ADCR Mux", "DMIC", "DMIC1R" },
1562
1563         { "DAC1L", NULL, "AIF1CLK" },
1564         { "DAC1L", NULL, "DSP1CLK" },
1565         { "DAC1L", NULL, "DSPINTCLK" },
1566
1567         { "DAC1R", NULL, "AIF1CLK" },
1568         { "DAC1R", NULL, "DSP1CLK" },
1569         { "DAC1R", NULL, "DSPINTCLK" },
1570
1571         { "DAC2L", NULL, "AIF2CLK" },
1572         { "DAC2L", NULL, "DSP2CLK" },
1573         { "DAC2L", NULL, "DSPINTCLK" },
1574
1575         { "DAC2R", NULL, "AIF2DACR" },
1576         { "DAC2R", NULL, "AIF2CLK" },
1577         { "DAC2R", NULL, "DSP2CLK" },
1578         { "DAC2R", NULL, "DSPINTCLK" },
1579
1580         { "TOCLK", NULL, "CLK_SYS" },
1581
1582         /* AIF1 outputs */
1583         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1584         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1585         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1586
1587         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1588         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1589         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1590
1591         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1592         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1593         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1594
1595         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1596         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1597         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1598
1599         /* Pin level routing for AIF3 */
1600         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1601         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1602         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1603         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1604
1605         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1606         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1607         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1608         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1609         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1610         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1611         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1612
1613         /* DAC1 inputs */
1614         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1615         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1616         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1617         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1618         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1619
1620         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1621         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1622         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1623         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1624         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1625
1626         /* DAC2/AIF2 outputs  */
1627         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1628         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1629         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1630         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1631         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1632         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1633
1634         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1635         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1636         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1637         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1638         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1639         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1640
1641         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1642         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1643         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1644         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1645
1646         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1647
1648         /* AIF3 output */
1649         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1650         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1651         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1652         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1653         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1654         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1655         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1656         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1657
1658         /* Sidetone */
1659         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1660         { "Left Sidetone", "DMIC2", "DMIC2L" },
1661         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1662         { "Right Sidetone", "DMIC2", "DMIC2R" },
1663
1664         /* Output stages */
1665         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1666         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1667
1668         { "SPKL", "DAC1 Switch", "DAC1L" },
1669         { "SPKL", "DAC2 Switch", "DAC2L" },
1670
1671         { "SPKR", "DAC1 Switch", "DAC1R" },
1672         { "SPKR", "DAC2 Switch", "DAC2R" },
1673
1674         { "Left Headphone Mux", "DAC", "DAC1L" },
1675         { "Right Headphone Mux", "DAC", "DAC1R" },
1676 };
1677
1678 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1679         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1680         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1681         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1682         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1683         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1684         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1685         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1686         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1687 };
1688
1689 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1690         { "DAC1L", NULL, "DAC1L Mixer" },
1691         { "DAC1R", NULL, "DAC1R Mixer" },
1692         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1693         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1694 };
1695
1696 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1697         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1698         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1699         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1700         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1701         { "MICBIAS1", NULL, "CLK_SYS" },
1702         { "MICBIAS1", NULL, "MICBIAS Supply" },
1703         { "MICBIAS2", NULL, "CLK_SYS" },
1704         { "MICBIAS2", NULL, "MICBIAS Supply" },
1705 };
1706
1707 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1708         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1709         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1710         { "MICBIAS1", NULL, "VMID" },
1711         { "MICBIAS2", NULL, "VMID" },
1712 };
1713
1714 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1715         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1716         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1717
1718         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1719         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1720         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1721         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1722
1723         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1724         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1725
1726         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1727 };
1728
1729 /* The size in bits of the FLL divide multiplied by 10
1730  * to allow rounding later */
1731 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1732
1733 struct fll_div {
1734         u16 outdiv;
1735         u16 n;
1736         u16 k;
1737         u16 clk_ref_div;
1738         u16 fll_fratio;
1739 };
1740
1741 static int wm8994_get_fll_config(struct fll_div *fll,
1742                                  int freq_in, int freq_out)
1743 {
1744         u64 Kpart;
1745         unsigned int K, Ndiv, Nmod;
1746
1747         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1748
1749         /* Scale the input frequency down to <= 13.5MHz */
1750         fll->clk_ref_div = 0;
1751         while (freq_in > 13500000) {
1752                 fll->clk_ref_div++;
1753                 freq_in /= 2;
1754
1755                 if (fll->clk_ref_div > 3)
1756                         return -EINVAL;
1757         }
1758         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1759
1760         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1761         fll->outdiv = 3;
1762         while (freq_out * (fll->outdiv + 1) < 90000000) {
1763                 fll->outdiv++;
1764                 if (fll->outdiv > 63)
1765                         return -EINVAL;
1766         }
1767         freq_out *= fll->outdiv + 1;
1768         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1769
1770         if (freq_in > 1000000) {
1771                 fll->fll_fratio = 0;
1772         } else if (freq_in > 256000) {
1773                 fll->fll_fratio = 1;
1774                 freq_in *= 2;
1775         } else if (freq_in > 128000) {
1776                 fll->fll_fratio = 2;
1777                 freq_in *= 4;
1778         } else if (freq_in > 64000) {
1779                 fll->fll_fratio = 3;
1780                 freq_in *= 8;
1781         } else {
1782                 fll->fll_fratio = 4;
1783                 freq_in *= 16;
1784         }
1785         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1786
1787         /* Now, calculate N.K */
1788         Ndiv = freq_out / freq_in;
1789
1790         fll->n = Ndiv;
1791         Nmod = freq_out % freq_in;
1792         pr_debug("Nmod=%d\n", Nmod);
1793
1794         /* Calculate fractional part - scale up so we can round. */
1795         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1796
1797         do_div(Kpart, freq_in);
1798
1799         K = Kpart & 0xFFFFFFFF;
1800
1801         if ((K % 10) >= 5)
1802                 K += 5;
1803
1804         /* Move down to proper range now rounding is done */
1805         fll->k = K / 10;
1806
1807         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1808
1809         return 0;
1810 }
1811
1812 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1813                           unsigned int freq_in, unsigned int freq_out)
1814 {
1815         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1816         struct wm8994 *control = wm8994->wm8994;
1817         int reg_offset, ret;
1818         struct fll_div fll;
1819         u16 reg, aif1, aif2;
1820         unsigned long timeout;
1821         bool was_enabled;
1822
1823         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1824                 & WM8994_AIF1CLK_ENA;
1825
1826         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1827                 & WM8994_AIF2CLK_ENA;
1828
1829         switch (id) {
1830         case WM8994_FLL1:
1831                 reg_offset = 0;
1832                 id = 0;
1833                 break;
1834         case WM8994_FLL2:
1835                 reg_offset = 0x20;
1836                 id = 1;
1837                 break;
1838         default:
1839                 return -EINVAL;
1840         }
1841
1842         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1843         was_enabled = reg & WM8994_FLL1_ENA;
1844
1845         switch (src) {
1846         case 0:
1847                 /* Allow no source specification when stopping */
1848                 if (freq_out)
1849                         return -EINVAL;
1850                 src = wm8994->fll[id].src;
1851                 break;
1852         case WM8994_FLL_SRC_MCLK1:
1853         case WM8994_FLL_SRC_MCLK2:
1854         case WM8994_FLL_SRC_LRCLK:
1855         case WM8994_FLL_SRC_BCLK:
1856                 break;
1857         default:
1858                 return -EINVAL;
1859         }
1860
1861         /* Are we changing anything? */
1862         if (wm8994->fll[id].src == src &&
1863             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1864                 return 0;
1865
1866         /* If we're stopping the FLL redo the old config - no
1867          * registers will actually be written but we avoid GCC flow
1868          * analysis bugs spewing warnings.
1869          */
1870         if (freq_out)
1871                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1872         else
1873                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1874                                             wm8994->fll[id].out);
1875         if (ret < 0)
1876                 return ret;
1877
1878         /* Gate the AIF clocks while we reclock */
1879         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1880                             WM8994_AIF1CLK_ENA, 0);
1881         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1882                             WM8994_AIF2CLK_ENA, 0);
1883
1884         /* We always need to disable the FLL while reconfiguring */
1885         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1886                             WM8994_FLL1_ENA, 0);
1887
1888         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1889                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1890         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1891                             WM8994_FLL1_OUTDIV_MASK |
1892                             WM8994_FLL1_FRATIO_MASK, reg);
1893
1894         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1895
1896         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1897                             WM8994_FLL1_N_MASK,
1898                                     fll.n << WM8994_FLL1_N_SHIFT);
1899
1900         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1901                             WM8994_FLL1_REFCLK_DIV_MASK |
1902                             WM8994_FLL1_REFCLK_SRC_MASK,
1903                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1904                             (src - 1));
1905
1906         /* Clear any pending completion from a previous failure */
1907         try_wait_for_completion(&wm8994->fll_locked[id]);
1908
1909         /* Enable (with fractional mode if required) */
1910         if (freq_out) {
1911                 /* Enable VMID if we need it */
1912                 if (!was_enabled) {
1913                         active_reference(codec);
1914
1915                         switch (control->type) {
1916                         case WM8994:
1917                                 vmid_reference(codec);
1918                                 break;
1919                         case WM8958:
1920                                 if (wm8994->revision < 1)
1921                                         vmid_reference(codec);
1922                                 break;
1923                         default:
1924                                 break;
1925                         }
1926                 }
1927
1928                 if (fll.k)
1929                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1930                 else
1931                         reg = WM8994_FLL1_ENA;
1932                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1933                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1934                                     reg);
1935
1936                 if (wm8994->fll_locked_irq) {
1937                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1938                                                               msecs_to_jiffies(10));
1939                         if (timeout == 0)
1940                                 dev_warn(codec->dev,
1941                                          "Timed out waiting for FLL lock\n");
1942                 } else {
1943                         msleep(5);
1944                 }
1945         } else {
1946                 if (was_enabled) {
1947                         switch (control->type) {
1948                         case WM8994:
1949                                 vmid_dereference(codec);
1950                                 break;
1951                         case WM8958:
1952                                 if (wm8994->revision < 1)
1953                                         vmid_dereference(codec);
1954                                 break;
1955                         default:
1956                                 break;
1957                         }
1958
1959                         active_dereference(codec);
1960                 }
1961         }
1962
1963         wm8994->fll[id].in = freq_in;
1964         wm8994->fll[id].out = freq_out;
1965         wm8994->fll[id].src = src;
1966
1967         /* Enable any gated AIF clocks */
1968         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1969                             WM8994_AIF1CLK_ENA, aif1);
1970         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1971                             WM8994_AIF2CLK_ENA, aif2);
1972
1973         configure_clock(codec);
1974
1975         return 0;
1976 }
1977
1978 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1979 {
1980         struct completion *completion = data;
1981
1982         complete(completion);
1983
1984         return IRQ_HANDLED;
1985 }
1986
1987 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1988
1989 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1990                           unsigned int freq_in, unsigned int freq_out)
1991 {
1992         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1993 }
1994
1995 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1996                 int clk_id, unsigned int freq, int dir)
1997 {
1998         struct snd_soc_codec *codec = dai->codec;
1999         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2000         int i;
2001
2002         switch (dai->id) {
2003         case 1:
2004         case 2:
2005                 break;
2006
2007         default:
2008                 /* AIF3 shares clocking with AIF1/2 */
2009                 return -EINVAL;
2010         }
2011
2012         switch (clk_id) {
2013         case WM8994_SYSCLK_MCLK1:
2014                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2015                 wm8994->mclk[0] = freq;
2016                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2017                         dai->id, freq);
2018                 break;
2019
2020         case WM8994_SYSCLK_MCLK2:
2021                 /* TODO: Set GPIO AF */
2022                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2023                 wm8994->mclk[1] = freq;
2024                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2025                         dai->id, freq);
2026                 break;
2027
2028         case WM8994_SYSCLK_FLL1:
2029                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2030                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2031                 break;
2032
2033         case WM8994_SYSCLK_FLL2:
2034                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2035                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2036                 break;
2037
2038         case WM8994_SYSCLK_OPCLK:
2039                 /* Special case - a division (times 10) is given and
2040                  * no effect on main clocking.
2041                  */
2042                 if (freq) {
2043                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2044                                 if (opclk_divs[i] == freq)
2045                                         break;
2046                         if (i == ARRAY_SIZE(opclk_divs))
2047                                 return -EINVAL;
2048                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2049                                             WM8994_OPCLK_DIV_MASK, i);
2050                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2051                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2052                 } else {
2053                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2054                                             WM8994_OPCLK_ENA, 0);
2055                 }
2056
2057         default:
2058                 return -EINVAL;
2059         }
2060
2061         configure_clock(codec);
2062
2063         return 0;
2064 }
2065
2066 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2067                                  enum snd_soc_bias_level level)
2068 {
2069         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2070         struct wm8994 *control = wm8994->wm8994;
2071
2072         switch (level) {
2073         case SND_SOC_BIAS_ON:
2074                 break;
2075
2076         case SND_SOC_BIAS_PREPARE:
2077                 /* MICBIAS into regulating mode */
2078                 switch (control->type) {
2079                 case WM8958:
2080                 case WM1811:
2081                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2082                                             WM8958_MICB1_MODE, 0);
2083                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2084                                             WM8958_MICB2_MODE, 0);
2085                         break;
2086                 default:
2087                         break;
2088                 }
2089
2090                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2091                         active_reference(codec);
2092                 break;
2093
2094         case SND_SOC_BIAS_STANDBY:
2095                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2096                         switch (control->type) {
2097                         case WM8994:
2098                                 if (wm8994->revision < 4) {
2099                                         /* Tweak DC servo and DSP
2100                                          * configuration for improved
2101                                          * performance. */
2102                                         snd_soc_write(codec, 0x102, 0x3);
2103                                         snd_soc_write(codec, 0x56, 0x3);
2104                                         snd_soc_write(codec, 0x817, 0);
2105                                         snd_soc_write(codec, 0x102, 0);
2106                                 }
2107                                 break;
2108
2109                         case WM8958:
2110                                 if (wm8994->revision == 0) {
2111                                         /* Optimise performance for rev A */
2112                                         snd_soc_write(codec, 0x102, 0x3);
2113                                         snd_soc_write(codec, 0xcb, 0x81);
2114                                         snd_soc_write(codec, 0x817, 0);
2115                                         snd_soc_write(codec, 0x102, 0);
2116
2117                                         snd_soc_update_bits(codec,
2118                                                             WM8958_CHARGE_PUMP_2,
2119                                                             WM8958_CP_DISCH,
2120                                                             WM8958_CP_DISCH);
2121                                 }
2122                                 break;
2123
2124                         case WM1811:
2125                                 if (wm8994->revision < 2) {
2126                                         snd_soc_write(codec, 0x102, 0x3);
2127                                         snd_soc_write(codec, 0x5d, 0x7e);
2128                                         snd_soc_write(codec, 0x5e, 0x0);
2129                                         snd_soc_write(codec, 0x102, 0x0);
2130                                 }
2131                                 break;
2132                         }
2133
2134                         /* Discharge LINEOUT1 & 2 */
2135                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2136                                             WM8994_LINEOUT1_DISCH |
2137                                             WM8994_LINEOUT2_DISCH,
2138                                             WM8994_LINEOUT1_DISCH |
2139                                             WM8994_LINEOUT2_DISCH);
2140                 }
2141
2142                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2143                         active_dereference(codec);
2144
2145                 /* MICBIAS into bypass mode on newer devices */
2146                 switch (control->type) {
2147                 case WM8958:
2148                 case WM1811:
2149                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2150                                             WM8958_MICB1_MODE,
2151                                             WM8958_MICB1_MODE);
2152                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2153                                             WM8958_MICB2_MODE,
2154                                             WM8958_MICB2_MODE);
2155                         break;
2156                 default:
2157                         break;
2158                 }
2159                 break;
2160
2161         case SND_SOC_BIAS_OFF:
2162                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2163                         wm8994->cur_fw = NULL;
2164                 break;
2165         }
2166         codec->dapm.bias_level = level;
2167
2168         return 0;
2169 }
2170
2171 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2172 {
2173         struct snd_soc_codec *codec = dai->codec;
2174         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2175         struct wm8994 *control = wm8994->wm8994;
2176         int ms_reg;
2177         int aif1_reg;
2178         int ms = 0;
2179         int aif1 = 0;
2180
2181         switch (dai->id) {
2182         case 1:
2183                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2184                 aif1_reg = WM8994_AIF1_CONTROL_1;
2185                 break;
2186         case 2:
2187                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2188                 aif1_reg = WM8994_AIF2_CONTROL_1;
2189                 break;
2190         default:
2191                 return -EINVAL;
2192         }
2193
2194         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2195         case SND_SOC_DAIFMT_CBS_CFS:
2196                 break;
2197         case SND_SOC_DAIFMT_CBM_CFM:
2198                 ms = WM8994_AIF1_MSTR;
2199                 break;
2200         default:
2201                 return -EINVAL;
2202         }
2203
2204         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2205         case SND_SOC_DAIFMT_DSP_B:
2206                 aif1 |= WM8994_AIF1_LRCLK_INV;
2207         case SND_SOC_DAIFMT_DSP_A:
2208                 aif1 |= 0x18;
2209                 break;
2210         case SND_SOC_DAIFMT_I2S:
2211                 aif1 |= 0x10;
2212                 break;
2213         case SND_SOC_DAIFMT_RIGHT_J:
2214                 break;
2215         case SND_SOC_DAIFMT_LEFT_J:
2216                 aif1 |= 0x8;
2217                 break;
2218         default:
2219                 return -EINVAL;
2220         }
2221
2222         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2223         case SND_SOC_DAIFMT_DSP_A:
2224         case SND_SOC_DAIFMT_DSP_B:
2225                 /* frame inversion not valid for DSP modes */
2226                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2227                 case SND_SOC_DAIFMT_NB_NF:
2228                         break;
2229                 case SND_SOC_DAIFMT_IB_NF:
2230                         aif1 |= WM8994_AIF1_BCLK_INV;
2231                         break;
2232                 default:
2233                         return -EINVAL;
2234                 }
2235                 break;
2236
2237         case SND_SOC_DAIFMT_I2S:
2238         case SND_SOC_DAIFMT_RIGHT_J:
2239         case SND_SOC_DAIFMT_LEFT_J:
2240                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2241                 case SND_SOC_DAIFMT_NB_NF:
2242                         break;
2243                 case SND_SOC_DAIFMT_IB_IF:
2244                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2245                         break;
2246                 case SND_SOC_DAIFMT_IB_NF:
2247                         aif1 |= WM8994_AIF1_BCLK_INV;
2248                         break;
2249                 case SND_SOC_DAIFMT_NB_IF:
2250                         aif1 |= WM8994_AIF1_LRCLK_INV;
2251                         break;
2252                 default:
2253                         return -EINVAL;
2254                 }
2255                 break;
2256         default:
2257                 return -EINVAL;
2258         }
2259
2260         /* The AIF2 format configuration needs to be mirrored to AIF3
2261          * on WM8958 if it's in use so just do it all the time. */
2262         switch (control->type) {
2263         case WM1811:
2264         case WM8958:
2265                 if (dai->id == 2)
2266                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2267                                             WM8994_AIF1_LRCLK_INV |
2268                                             WM8958_AIF3_FMT_MASK, aif1);
2269                 break;
2270
2271         default:
2272                 break;
2273         }
2274
2275         snd_soc_update_bits(codec, aif1_reg,
2276                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2277                             WM8994_AIF1_FMT_MASK,
2278                             aif1);
2279         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2280                             ms);
2281
2282         return 0;
2283 }
2284
2285 static struct {
2286         int val, rate;
2287 } srs[] = {
2288         { 0,   8000 },
2289         { 1,  11025 },
2290         { 2,  12000 },
2291         { 3,  16000 },
2292         { 4,  22050 },
2293         { 5,  24000 },
2294         { 6,  32000 },
2295         { 7,  44100 },
2296         { 8,  48000 },
2297         { 9,  88200 },
2298         { 10, 96000 },
2299 };
2300
2301 static int fs_ratios[] = {
2302         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2303 };
2304
2305 static int bclk_divs[] = {
2306         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2307         640, 880, 960, 1280, 1760, 1920
2308 };
2309
2310 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2311                             struct snd_pcm_hw_params *params,
2312                             struct snd_soc_dai *dai)
2313 {
2314         struct snd_soc_codec *codec = dai->codec;
2315         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2316         int aif1_reg;
2317         int aif2_reg;
2318         int bclk_reg;
2319         int lrclk_reg;
2320         int rate_reg;
2321         int aif1 = 0;
2322         int aif2 = 0;
2323         int bclk = 0;
2324         int lrclk = 0;
2325         int rate_val = 0;
2326         int id = dai->id - 1;
2327
2328         int i, cur_val, best_val, bclk_rate, best;
2329
2330         switch (dai->id) {
2331         case 1:
2332                 aif1_reg = WM8994_AIF1_CONTROL_1;
2333                 aif2_reg = WM8994_AIF1_CONTROL_2;
2334                 bclk_reg = WM8994_AIF1_BCLK;
2335                 rate_reg = WM8994_AIF1_RATE;
2336                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2337                     wm8994->lrclk_shared[0]) {
2338                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2339                 } else {
2340                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2341                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2342                 }
2343                 break;
2344         case 2:
2345                 aif1_reg = WM8994_AIF2_CONTROL_1;
2346                 aif2_reg = WM8994_AIF2_CONTROL_2;
2347                 bclk_reg = WM8994_AIF2_BCLK;
2348                 rate_reg = WM8994_AIF2_RATE;
2349                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2350                     wm8994->lrclk_shared[1]) {
2351                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2352                 } else {
2353                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2354                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2355                 }
2356                 break;
2357         default:
2358                 return -EINVAL;
2359         }
2360
2361         bclk_rate = params_rate(params) * 2;
2362         switch (params_format(params)) {
2363         case SNDRV_PCM_FORMAT_S16_LE:
2364                 bclk_rate *= 16;
2365                 break;
2366         case SNDRV_PCM_FORMAT_S20_3LE:
2367                 bclk_rate *= 20;
2368                 aif1 |= 0x20;
2369                 break;
2370         case SNDRV_PCM_FORMAT_S24_LE:
2371                 bclk_rate *= 24;
2372                 aif1 |= 0x40;
2373                 break;
2374         case SNDRV_PCM_FORMAT_S32_LE:
2375                 bclk_rate *= 32;
2376                 aif1 |= 0x60;
2377                 break;
2378         default:
2379                 return -EINVAL;
2380         }
2381
2382         /* Try to find an appropriate sample rate; look for an exact match. */
2383         for (i = 0; i < ARRAY_SIZE(srs); i++)
2384                 if (srs[i].rate == params_rate(params))
2385                         break;
2386         if (i == ARRAY_SIZE(srs))
2387                 return -EINVAL;
2388         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2389
2390         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2391         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2392                 dai->id, wm8994->aifclk[id], bclk_rate);
2393
2394         if (params_channels(params) == 1 &&
2395             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2396                 aif2 |= WM8994_AIF1_MONO;
2397
2398         if (wm8994->aifclk[id] == 0) {
2399                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2400                 return -EINVAL;
2401         }
2402
2403         /* AIFCLK/fs ratio; look for a close match in either direction */
2404         best = 0;
2405         best_val = abs((fs_ratios[0] * params_rate(params))
2406                        - wm8994->aifclk[id]);
2407         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2408                 cur_val = abs((fs_ratios[i] * params_rate(params))
2409                               - wm8994->aifclk[id]);
2410                 if (cur_val >= best_val)
2411                         continue;
2412                 best = i;
2413                 best_val = cur_val;
2414         }
2415         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2416                 dai->id, fs_ratios[best]);
2417         rate_val |= best;
2418
2419         /* We may not get quite the right frequency if using
2420          * approximate clocks so look for the closest match that is
2421          * higher than the target (we need to ensure that there enough
2422          * BCLKs to clock out the samples).
2423          */
2424         best = 0;
2425         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2426                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2427                 if (cur_val < 0) /* BCLK table is sorted */
2428                         break;
2429                 best = i;
2430         }
2431         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2432         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2433                 bclk_divs[best], bclk_rate);
2434         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2435
2436         lrclk = bclk_rate / params_rate(params);
2437         if (!lrclk) {
2438                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2439                         bclk_rate);
2440                 return -EINVAL;
2441         }
2442         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2443                 lrclk, bclk_rate / lrclk);
2444
2445         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2446         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2447         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2448         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2449                             lrclk);
2450         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2451                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2452
2453         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2454                 switch (dai->id) {
2455                 case 1:
2456                         wm8994->dac_rates[0] = params_rate(params);
2457                         wm8994_set_retune_mobile(codec, 0);
2458                         wm8994_set_retune_mobile(codec, 1);
2459                         break;
2460                 case 2:
2461                         wm8994->dac_rates[1] = params_rate(params);
2462                         wm8994_set_retune_mobile(codec, 2);
2463                         break;
2464                 }
2465         }
2466
2467         return 0;
2468 }
2469
2470 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2471                                  struct snd_pcm_hw_params *params,
2472                                  struct snd_soc_dai *dai)
2473 {
2474         struct snd_soc_codec *codec = dai->codec;
2475         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2476         struct wm8994 *control = wm8994->wm8994;
2477         int aif1_reg;
2478         int aif1 = 0;
2479
2480         switch (dai->id) {
2481         case 3:
2482                 switch (control->type) {
2483                 case WM1811:
2484                 case WM8958:
2485                         aif1_reg = WM8958_AIF3_CONTROL_1;
2486                         break;
2487                 default:
2488                         return 0;
2489                 }
2490         default:
2491                 return 0;
2492         }
2493
2494         switch (params_format(params)) {
2495         case SNDRV_PCM_FORMAT_S16_LE:
2496                 break;
2497         case SNDRV_PCM_FORMAT_S20_3LE:
2498                 aif1 |= 0x20;
2499                 break;
2500         case SNDRV_PCM_FORMAT_S24_LE:
2501                 aif1 |= 0x40;
2502                 break;
2503         case SNDRV_PCM_FORMAT_S32_LE:
2504                 aif1 |= 0x60;
2505                 break;
2506         default:
2507                 return -EINVAL;
2508         }
2509
2510         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2511 }
2512
2513 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2514                                 struct snd_soc_dai *dai)
2515 {
2516         struct snd_soc_codec *codec = dai->codec;
2517         int rate_reg = 0;
2518
2519         switch (dai->id) {
2520         case 1:
2521                 rate_reg = WM8994_AIF1_RATE;
2522                 break;
2523         case 2:
2524                 rate_reg = WM8994_AIF2_RATE;
2525                 break;
2526         default:
2527                 break;
2528         }
2529
2530         /* If the DAI is idle then configure the divider tree for the
2531          * lowest output rate to save a little power if the clock is
2532          * still active (eg, because it is system clock).
2533          */
2534         if (rate_reg && !dai->playback_active && !dai->capture_active)
2535                 snd_soc_update_bits(codec, rate_reg,
2536                                     WM8994_AIF1_SR_MASK |
2537                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2538 }
2539
2540 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2541 {
2542         struct snd_soc_codec *codec = codec_dai->codec;
2543         int mute_reg;
2544         int reg;
2545
2546         switch (codec_dai->id) {
2547         case 1:
2548                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2549                 break;
2550         case 2:
2551                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2552                 break;
2553         default:
2554                 return -EINVAL;
2555         }
2556
2557         if (mute)
2558                 reg = WM8994_AIF1DAC1_MUTE;
2559         else
2560                 reg = 0;
2561
2562         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2563
2564         return 0;
2565 }
2566
2567 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2568 {
2569         struct snd_soc_codec *codec = codec_dai->codec;
2570         int reg, val, mask;
2571
2572         switch (codec_dai->id) {
2573         case 1:
2574                 reg = WM8994_AIF1_MASTER_SLAVE;
2575                 mask = WM8994_AIF1_TRI;
2576                 break;
2577         case 2:
2578                 reg = WM8994_AIF2_MASTER_SLAVE;
2579                 mask = WM8994_AIF2_TRI;
2580                 break;
2581         case 3:
2582                 reg = WM8994_POWER_MANAGEMENT_6;
2583                 mask = WM8994_AIF3_TRI;
2584                 break;
2585         default:
2586                 return -EINVAL;
2587         }
2588
2589         if (tristate)
2590                 val = mask;
2591         else
2592                 val = 0;
2593
2594         return snd_soc_update_bits(codec, reg, mask, val);
2595 }
2596
2597 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2598 {
2599         struct snd_soc_codec *codec = dai->codec;
2600
2601         /* Disable the pulls on the AIF if we're using it to save power. */
2602         snd_soc_update_bits(codec, WM8994_GPIO_3,
2603                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2604         snd_soc_update_bits(codec, WM8994_GPIO_4,
2605                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2606         snd_soc_update_bits(codec, WM8994_GPIO_5,
2607                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2608
2609         return 0;
2610 }
2611
2612 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2613
2614 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2615                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2616
2617 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2618         .set_sysclk     = wm8994_set_dai_sysclk,
2619         .set_fmt        = wm8994_set_dai_fmt,
2620         .hw_params      = wm8994_hw_params,
2621         .shutdown       = wm8994_aif_shutdown,
2622         .digital_mute   = wm8994_aif_mute,
2623         .set_pll        = wm8994_set_fll,
2624         .set_tristate   = wm8994_set_tristate,
2625 };
2626
2627 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2628         .set_sysclk     = wm8994_set_dai_sysclk,
2629         .set_fmt        = wm8994_set_dai_fmt,
2630         .hw_params      = wm8994_hw_params,
2631         .shutdown       = wm8994_aif_shutdown,
2632         .digital_mute   = wm8994_aif_mute,
2633         .set_pll        = wm8994_set_fll,
2634         .set_tristate   = wm8994_set_tristate,
2635 };
2636
2637 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2638         .hw_params      = wm8994_aif3_hw_params,
2639         .set_tristate   = wm8994_set_tristate,
2640 };
2641
2642 static struct snd_soc_dai_driver wm8994_dai[] = {
2643         {
2644                 .name = "wm8994-aif1",
2645                 .id = 1,
2646                 .playback = {
2647                         .stream_name = "AIF1 Playback",
2648                         .channels_min = 1,
2649                         .channels_max = 2,
2650                         .rates = WM8994_RATES,
2651                         .formats = WM8994_FORMATS,
2652                 },
2653                 .capture = {
2654                         .stream_name = "AIF1 Capture",
2655                         .channels_min = 1,
2656                         .channels_max = 2,
2657                         .rates = WM8994_RATES,
2658                         .formats = WM8994_FORMATS,
2659                  },
2660                 .ops = &wm8994_aif1_dai_ops,
2661         },
2662         {
2663                 .name = "wm8994-aif2",
2664                 .id = 2,
2665                 .playback = {
2666                         .stream_name = "AIF2 Playback",
2667                         .channels_min = 1,
2668                         .channels_max = 2,
2669                         .rates = WM8994_RATES,
2670                         .formats = WM8994_FORMATS,
2671                 },
2672                 .capture = {
2673                         .stream_name = "AIF2 Capture",
2674                         .channels_min = 1,
2675                         .channels_max = 2,
2676                         .rates = WM8994_RATES,
2677                         .formats = WM8994_FORMATS,
2678                 },
2679                 .probe = wm8994_aif2_probe,
2680                 .ops = &wm8994_aif2_dai_ops,
2681         },
2682         {
2683                 .name = "wm8994-aif3",
2684                 .id = 3,
2685                 .playback = {
2686                         .stream_name = "AIF3 Playback",
2687                         .channels_min = 1,
2688                         .channels_max = 2,
2689                         .rates = WM8994_RATES,
2690                         .formats = WM8994_FORMATS,
2691                 },
2692                 .capture = {
2693                         .stream_name = "AIF3 Capture",
2694                         .channels_min = 1,
2695                         .channels_max = 2,
2696                         .rates = WM8994_RATES,
2697                         .formats = WM8994_FORMATS,
2698                 },
2699                 .ops = &wm8994_aif3_dai_ops,
2700         }
2701 };
2702
2703 #ifdef CONFIG_PM
2704 static int wm8994_suspend(struct snd_soc_codec *codec)
2705 {
2706         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2707         struct wm8994 *control = wm8994->wm8994;
2708         int i, ret;
2709
2710         switch (control->type) {
2711         case WM8994:
2712                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2713                 break;
2714         case WM1811:
2715                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2716                                     WM1811_JACKDET_MODE_MASK, 0);
2717                 /* Fall through */
2718         case WM8958:
2719                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2720                                     WM8958_MICD_ENA, 0);
2721                 break;
2722         }
2723
2724         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2725                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2726                        sizeof(struct wm8994_fll_config));
2727                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2728                 if (ret < 0)
2729                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2730                                  i + 1, ret);
2731         }
2732
2733         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2734
2735         return 0;
2736 }
2737
2738 static int wm8994_resume(struct snd_soc_codec *codec)
2739 {
2740         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2741         struct wm8994 *control = wm8994->wm8994;
2742         int i, ret;
2743         unsigned int val, mask;
2744
2745         if (wm8994->revision < 4) {
2746                 /* force a HW read */
2747                 ret = regmap_read(control->regmap,
2748                                   WM8994_POWER_MANAGEMENT_5, &val);
2749
2750                 /* modify the cache only */
2751                 codec->cache_only = 1;
2752                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2753                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2754                 val &= mask;
2755                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2756                                     mask, val);
2757                 codec->cache_only = 0;
2758         }
2759
2760         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2761
2762         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2763                 if (!wm8994->fll_suspend[i].out)
2764                         continue;
2765
2766                 ret = _wm8994_set_fll(codec, i + 1,
2767                                      wm8994->fll_suspend[i].src,
2768                                      wm8994->fll_suspend[i].in,
2769                                      wm8994->fll_suspend[i].out);
2770                 if (ret < 0)
2771                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2772                                  i + 1, ret);
2773         }
2774
2775         switch (control->type) {
2776         case WM8994:
2777                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2778                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2779                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2780                 break;
2781         case WM1811:
2782                 if (wm8994->jackdet && wm8994->jack_cb) {
2783                         /* Restart from idle */
2784                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2785                                             WM1811_JACKDET_MODE_MASK,
2786                                             WM1811_JACKDET_MODE_JACK);
2787                         break;
2788                 }
2789         case WM8958:
2790                 if (wm8994->jack_cb)
2791                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2792                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2793                 break;
2794         }
2795
2796         return 0;
2797 }
2798 #else
2799 #define wm8994_suspend NULL
2800 #define wm8994_resume NULL
2801 #endif
2802
2803 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2804 {
2805         struct snd_soc_codec *codec = wm8994->codec;
2806         struct wm8994_pdata *pdata = wm8994->pdata;
2807         struct snd_kcontrol_new controls[] = {
2808                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2809                              wm8994->retune_mobile_enum,
2810                              wm8994_get_retune_mobile_enum,
2811                              wm8994_put_retune_mobile_enum),
2812                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2813                              wm8994->retune_mobile_enum,
2814                              wm8994_get_retune_mobile_enum,
2815                              wm8994_put_retune_mobile_enum),
2816                 SOC_ENUM_EXT("AIF2 EQ Mode",
2817                              wm8994->retune_mobile_enum,
2818                              wm8994_get_retune_mobile_enum,
2819                              wm8994_put_retune_mobile_enum),
2820         };
2821         int ret, i, j;
2822         const char **t;
2823
2824         /* We need an array of texts for the enum API but the number
2825          * of texts is likely to be less than the number of
2826          * configurations due to the sample rate dependency of the
2827          * configurations. */
2828         wm8994->num_retune_mobile_texts = 0;
2829         wm8994->retune_mobile_texts = NULL;
2830         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2831                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2832                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2833                                    wm8994->retune_mobile_texts[j]) == 0)
2834                                 break;
2835                 }
2836
2837                 if (j != wm8994->num_retune_mobile_texts)
2838                         continue;
2839
2840                 /* Expand the array... */
2841                 t = krealloc(wm8994->retune_mobile_texts,
2842                              sizeof(char *) *
2843                              (wm8994->num_retune_mobile_texts + 1),
2844                              GFP_KERNEL);
2845                 if (t == NULL)
2846                         continue;
2847
2848                 /* ...store the new entry... */
2849                 t[wm8994->num_retune_mobile_texts] =
2850                         pdata->retune_mobile_cfgs[i].name;
2851
2852                 /* ...and remember the new version. */
2853                 wm8994->num_retune_mobile_texts++;
2854                 wm8994->retune_mobile_texts = t;
2855         }
2856
2857         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2858                 wm8994->num_retune_mobile_texts);
2859
2860         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2861         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2862
2863         ret = snd_soc_add_controls(wm8994->codec, controls,
2864                                    ARRAY_SIZE(controls));
2865         if (ret != 0)
2866                 dev_err(wm8994->codec->dev,
2867                         "Failed to add ReTune Mobile controls: %d\n", ret);
2868 }
2869
2870 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2871 {
2872         struct snd_soc_codec *codec = wm8994->codec;
2873         struct wm8994_pdata *pdata = wm8994->pdata;
2874         int ret, i;
2875
2876         if (!pdata)
2877                 return;
2878
2879         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2880                                       pdata->lineout2_diff,
2881                                       pdata->lineout1fb,
2882                                       pdata->lineout2fb,
2883                                       pdata->jd_scthr,
2884                                       pdata->jd_thr,
2885                                       pdata->micbias1_lvl,
2886                                       pdata->micbias2_lvl);
2887
2888         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2889
2890         if (pdata->num_drc_cfgs) {
2891                 struct snd_kcontrol_new controls[] = {
2892                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2893                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2894                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2895                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2896                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2897                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2898                 };
2899
2900                 /* We need an array of texts for the enum API */
2901                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2902                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2903                 if (!wm8994->drc_texts) {
2904                         dev_err(wm8994->codec->dev,
2905                                 "Failed to allocate %d DRC config texts\n",
2906                                 pdata->num_drc_cfgs);
2907                         return;
2908                 }
2909
2910                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2911                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2912
2913                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2914                 wm8994->drc_enum.texts = wm8994->drc_texts;
2915
2916                 ret = snd_soc_add_controls(wm8994->codec, controls,
2917                                            ARRAY_SIZE(controls));
2918                 if (ret != 0)
2919                         dev_err(wm8994->codec->dev,
2920                                 "Failed to add DRC mode controls: %d\n", ret);
2921
2922                 for (i = 0; i < WM8994_NUM_DRC; i++)
2923                         wm8994_set_drc(codec, i);
2924         }
2925
2926         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2927                 pdata->num_retune_mobile_cfgs);
2928
2929         if (pdata->num_retune_mobile_cfgs)
2930                 wm8994_handle_retune_mobile_pdata(wm8994);
2931         else
2932                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2933                                      ARRAY_SIZE(wm8994_eq_controls));
2934
2935         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2936                 if (pdata->micbias[i]) {
2937                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2938                                 pdata->micbias[i] & 0xffff);
2939                 }
2940         }
2941 }
2942
2943 /**
2944  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2945  *
2946  * @codec:   WM8994 codec
2947  * @jack:    jack to report detection events on
2948  * @micbias: microphone bias to detect on
2949  * @det:     value to report for presence detection
2950  * @shrt:    value to report for short detection
2951  *
2952  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2953  * being used to bring out signals to the processor then only platform
2954  * data configuration is needed for WM8994 and processor GPIOs should
2955  * be configured using snd_soc_jack_add_gpios() instead.
2956  *
2957  * Configuration of detection levels is available via the micbias1_lvl
2958  * and micbias2_lvl platform data members.
2959  */
2960 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2961                       int micbias, int det, int shrt)
2962 {
2963         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2964         struct wm8994_micdet *micdet;
2965         struct wm8994 *control = wm8994->wm8994;
2966         int reg;
2967
2968         if (control->type != WM8994)
2969                 return -EINVAL;
2970
2971         switch (micbias) {
2972         case 1:
2973                 micdet = &wm8994->micdet[0];
2974                 break;
2975         case 2:
2976                 micdet = &wm8994->micdet[1];
2977                 break;
2978         default:
2979                 return -EINVAL;
2980         }
2981
2982         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2983                 micbias, det, shrt);
2984
2985         /* Store the configuration */
2986         micdet->jack = jack;
2987         micdet->det = det;
2988         micdet->shrt = shrt;
2989
2990         /* If either of the jacks is set up then enable detection */
2991         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2992                 reg = WM8994_MICD_ENA;
2993         else
2994                 reg = 0;
2995
2996         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2997
2998         return 0;
2999 }
3000 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3001
3002 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3003 {
3004         struct wm8994_priv *priv = data;
3005         struct snd_soc_codec *codec = priv->codec;
3006         int reg;
3007         int report;
3008
3009 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3010         trace_snd_soc_jack_irq(dev_name(codec->dev));
3011 #endif
3012
3013         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3014         if (reg < 0) {
3015                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3016                         reg);
3017                 return IRQ_HANDLED;
3018         }
3019
3020         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3021
3022         report = 0;
3023         if (reg & WM8994_MIC1_DET_STS)
3024                 report |= priv->micdet[0].det;
3025         if (reg & WM8994_MIC1_SHRT_STS)
3026                 report |= priv->micdet[0].shrt;
3027         snd_soc_jack_report(priv->micdet[0].jack, report,
3028                             priv->micdet[0].det | priv->micdet[0].shrt);
3029
3030         report = 0;
3031         if (reg & WM8994_MIC2_DET_STS)
3032                 report |= priv->micdet[1].det;
3033         if (reg & WM8994_MIC2_SHRT_STS)
3034                 report |= priv->micdet[1].shrt;
3035         snd_soc_jack_report(priv->micdet[1].jack, report,
3036                             priv->micdet[1].det | priv->micdet[1].shrt);
3037
3038         return IRQ_HANDLED;
3039 }
3040
3041 /* Default microphone detection handler for WM8958 - the user can
3042  * override this if they wish.
3043  */
3044 static void wm8958_default_micdet(u16 status, void *data)
3045 {
3046         struct snd_soc_codec *codec = data;
3047         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3048         int report;
3049
3050         dev_dbg(codec->dev, "MICDET %x\n", status);
3051
3052         /* Either nothing present or just starting detection */
3053         if (!(status & WM8958_MICD_STS)) {
3054                 if (!wm8994->jackdet) {
3055                         /* If nothing present then clear our statuses */
3056                         dev_dbg(codec->dev, "Detected open circuit\n");
3057                         wm8994->jack_mic = false;
3058                         wm8994->mic_detecting = true;
3059
3060                         wm8958_micd_set_rate(codec);
3061
3062                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3063                                             wm8994->btn_mask |
3064                                              SND_JACK_HEADSET);
3065                 }
3066                 return;
3067         }
3068
3069         /* If the measurement is showing a high impedence we've got a
3070          * microphone.
3071          */
3072         if (wm8994->mic_detecting && (status & 0x600)) {
3073                 dev_dbg(codec->dev, "Detected microphone\n");
3074
3075                 wm8994->mic_detecting = false;
3076                 wm8994->jack_mic = true;
3077
3078                 wm8958_micd_set_rate(codec);
3079
3080                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3081                                     SND_JACK_HEADSET);
3082         }
3083
3084
3085         if (wm8994->mic_detecting && status & 0x4) {
3086                 dev_dbg(codec->dev, "Detected headphone\n");
3087                 wm8994->mic_detecting = false;
3088
3089                 wm8958_micd_set_rate(codec);
3090
3091                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3092                                     SND_JACK_HEADSET);
3093
3094                 /* If we have jackdet that will detect removal */
3095                 if (wm8994->jackdet) {
3096                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3097                                             WM8958_MICD_ENA, 0);
3098
3099                         wm1811_jackdet_set_mode(codec,
3100                                                 WM1811_JACKDET_MODE_JACK);
3101                 }
3102         }
3103
3104         /* Report short circuit as a button */
3105         if (wm8994->jack_mic) {
3106                 report = 0;
3107                 if (status & 0x4)
3108                         report |= SND_JACK_BTN_0;
3109
3110                 if (status & 0x8)
3111                         report |= SND_JACK_BTN_1;
3112
3113                 if (status & 0x10)
3114                         report |= SND_JACK_BTN_2;
3115
3116                 if (status & 0x20)
3117                         report |= SND_JACK_BTN_3;
3118
3119                 if (status & 0x40)
3120                         report |= SND_JACK_BTN_4;
3121
3122                 if (status & 0x80)
3123                         report |= SND_JACK_BTN_5;
3124
3125                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3126                                     wm8994->btn_mask);
3127         }
3128 }
3129
3130 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3131 {
3132         struct wm8994_priv *wm8994 = data;
3133         struct snd_soc_codec *codec = wm8994->codec;
3134         int reg;
3135
3136         mutex_lock(&wm8994->accdet_lock);
3137
3138         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3139         if (reg < 0) {
3140                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3141                 mutex_unlock(&wm8994->accdet_lock);
3142                 return IRQ_NONE;
3143         }
3144
3145         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3146
3147         if (reg & WM1811_JACKDET_LVL) {
3148                 dev_dbg(codec->dev, "Jack detected\n");
3149
3150                 snd_soc_jack_report(wm8994->micdet[0].jack,
3151                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3152
3153                 /*
3154                  * Start off measument of microphone impedence to find
3155                  * out what's actually there.
3156                  */
3157                 wm8994->mic_detecting = true;
3158                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3159                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3160                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3161         } else {
3162                 dev_dbg(codec->dev, "Jack not detected\n");
3163
3164                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3165                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3166                                     wm8994->btn_mask);
3167
3168                 wm8994->mic_detecting = false;
3169                 wm8994->jack_mic = false;
3170                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3171                                     WM8958_MICD_ENA, 0);
3172                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3173         }
3174
3175         mutex_unlock(&wm8994->accdet_lock);
3176
3177         return IRQ_HANDLED;
3178 }
3179
3180 /**
3181  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3182  *
3183  * @codec:   WM8958 codec
3184  * @jack:    jack to report detection events on
3185  *
3186  * Enable microphone detection functionality for the WM8958.  By
3187  * default simple detection which supports the detection of up to 6
3188  * buttons plus video and microphone functionality is supported.
3189  *
3190  * The WM8958 has an advanced jack detection facility which is able to
3191  * support complex accessory detection, especially when used in
3192  * conjunction with external circuitry.  In order to provide maximum
3193  * flexiblity a callback is provided which allows a completely custom
3194  * detection algorithm.
3195  */
3196 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3197                       wm8958_micdet_cb cb, void *cb_data)
3198 {
3199         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3200         struct wm8994 *control = wm8994->wm8994;
3201         u16 micd_lvl_sel;
3202
3203         switch (control->type) {
3204         case WM1811:
3205         case WM8958:
3206                 break;
3207         default:
3208                 return -EINVAL;
3209         }
3210
3211         if (jack) {
3212                 if (!cb) {
3213                         dev_dbg(codec->dev, "Using default micdet callback\n");
3214                         cb = wm8958_default_micdet;
3215                         cb_data = codec;
3216                 }
3217
3218                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3219
3220                 wm8994->micdet[0].jack = jack;
3221                 wm8994->jack_cb = cb;
3222                 wm8994->jack_cb_data = cb_data;
3223
3224                 wm8994->mic_detecting = true;
3225                 wm8994->jack_mic = false;
3226
3227                 wm8958_micd_set_rate(codec);
3228
3229                 /* Detect microphones and short circuits by default */
3230                 if (wm8994->pdata->micd_lvl_sel)
3231                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3232                 else
3233                         micd_lvl_sel = 0x41;
3234
3235                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3236                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3237                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3238
3239                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3240                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3241
3242                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3243
3244                 /*
3245                  * If we can use jack detection start off with that,
3246                  * otherwise jump straight to microphone detection.
3247                  */
3248                 if (wm8994->jackdet) {
3249                         snd_soc_update_bits(codec, WM8994_LDO_1,
3250                                             WM8994_LDO1_DISCH, 0);
3251                         wm1811_jackdet_set_mode(codec,
3252                                                 WM1811_JACKDET_MODE_JACK);
3253                 } else {
3254                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3255                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3256                 }
3257
3258         } else {
3259                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3260                                     WM8958_MICD_ENA, 0);
3261                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3262         }
3263
3264         return 0;
3265 }
3266 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3267
3268 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3269 {
3270         struct wm8994_priv *wm8994 = data;
3271         struct snd_soc_codec *codec = wm8994->codec;
3272         int reg, count;
3273
3274         mutex_lock(&wm8994->accdet_lock);
3275
3276         /*
3277          * Jack detection may have detected a removal simulataneously
3278          * with an update of the MICDET status; if so it will have
3279          * stopped detection and we can ignore this interrupt.
3280          */
3281         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3282                 mutex_unlock(&wm8994->accdet_lock);
3283                 return IRQ_HANDLED;
3284         }
3285
3286         /* We may occasionally read a detection without an impedence
3287          * range being provided - if that happens loop again.
3288          */
3289         count = 10;
3290         do {
3291                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3292                 if (reg < 0) {
3293                         mutex_unlock(&wm8994->accdet_lock);
3294                         dev_err(codec->dev,
3295                                 "Failed to read mic detect status: %d\n",
3296                                 reg);
3297                         return IRQ_NONE;
3298                 }
3299
3300                 if (!(reg & WM8958_MICD_VALID)) {
3301                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3302                         goto out;
3303                 }
3304
3305                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3306                         break;
3307
3308                 msleep(1);
3309         } while (count--);
3310
3311         if (count == 0)
3312                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3313
3314 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3315         trace_snd_soc_jack_irq(dev_name(codec->dev));
3316 #endif
3317
3318         if (wm8994->jack_cb)
3319                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3320         else
3321                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3322
3323 out:
3324         mutex_unlock(&wm8994->accdet_lock);
3325
3326         return IRQ_HANDLED;
3327 }
3328
3329 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3330 {
3331         struct snd_soc_codec *codec = data;
3332
3333         dev_err(codec->dev, "FIFO error\n");
3334
3335         return IRQ_HANDLED;
3336 }
3337
3338 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3339 {
3340         struct snd_soc_codec *codec = data;
3341
3342         dev_err(codec->dev, "Thermal warning\n");
3343
3344         return IRQ_HANDLED;
3345 }
3346
3347 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3348 {
3349         struct snd_soc_codec *codec = data;
3350
3351         dev_crit(codec->dev, "Thermal shutdown\n");
3352
3353         return IRQ_HANDLED;
3354 }
3355
3356 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3357 {
3358         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3359         struct wm8994_priv *wm8994;
3360         struct snd_soc_dapm_context *dapm = &codec->dapm;
3361         unsigned int reg;
3362         int ret, i;
3363
3364         codec->control_data = control->regmap;
3365
3366         wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3367                               GFP_KERNEL);
3368         if (wm8994 == NULL)
3369                 return -ENOMEM;
3370         snd_soc_codec_set_drvdata(codec, wm8994);
3371
3372         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3373
3374         wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3375         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3376         wm8994->codec = codec;
3377
3378         mutex_init(&wm8994->accdet_lock);
3379
3380         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3381                 init_completion(&wm8994->fll_locked[i]);
3382
3383         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3384                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3385         else if (wm8994->pdata && wm8994->pdata->irq_base)
3386                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3387                                      WM8994_IRQ_MIC1_DET;
3388
3389         pm_runtime_enable(codec->dev);
3390         pm_runtime_resume(codec->dev);
3391
3392         /* Set revision-specific configuration */
3393         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3394         switch (control->type) {
3395         case WM8994:
3396                 switch (wm8994->revision) {
3397                 case 2:
3398                 case 3:
3399                         wm8994->hubs.dcs_codes_l = -5;
3400                         wm8994->hubs.dcs_codes_r = -5;
3401                         wm8994->hubs.hp_startup_mode = 1;
3402                         wm8994->hubs.dcs_readback_mode = 1;
3403                         wm8994->hubs.series_startup = 1;
3404                         break;
3405                 default:
3406                         wm8994->hubs.dcs_readback_mode = 2;
3407                         break;
3408                 }
3409                 break;
3410
3411         case WM8958:
3412                 wm8994->hubs.dcs_readback_mode = 1;
3413                 break;
3414
3415         case WM1811:
3416                 wm8994->hubs.dcs_readback_mode = 2;
3417                 wm8994->hubs.no_series_update = 1;
3418
3419                 switch (wm8994->revision) {
3420                 case 0:
3421                 case 1:
3422                 case 2:
3423                 case 3:
3424                         wm8994->hubs.dcs_codes_l = -9;
3425                         wm8994->hubs.dcs_codes_r = -5;
3426                         break;
3427                 default:
3428                         break;
3429                 }
3430
3431                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3432                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3433                 break;
3434
3435         default:
3436                 break;
3437         }
3438
3439         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3440                            wm8994_fifo_error, "FIFO error", codec);
3441         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3442                            wm8994_temp_warn, "Thermal warning", codec);
3443         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3444                            wm8994_temp_shut, "Thermal shutdown", codec);
3445
3446         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3447                                  wm_hubs_dcs_done, "DC servo done",
3448                                  &wm8994->hubs);
3449         if (ret == 0)
3450                 wm8994->hubs.dcs_done_irq = true;
3451
3452         switch (control->type) {
3453         case WM8994:
3454                 if (wm8994->micdet_irq) {
3455                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3456                                                    wm8994_mic_irq,
3457                                                    IRQF_TRIGGER_RISING,
3458                                                    "Mic1 detect",
3459                                                    wm8994);
3460                         if (ret != 0)
3461                                 dev_warn(codec->dev,
3462                                          "Failed to request Mic1 detect IRQ: %d\n",
3463                                          ret);
3464                 }
3465
3466                 ret = wm8994_request_irq(wm8994->wm8994,
3467                                          WM8994_IRQ_MIC1_SHRT,
3468                                          wm8994_mic_irq, "Mic 1 short",
3469                                          wm8994);
3470                 if (ret != 0)
3471                         dev_warn(codec->dev,
3472                                  "Failed to request Mic1 short IRQ: %d\n",
3473                                  ret);
3474
3475                 ret = wm8994_request_irq(wm8994->wm8994,
3476                                          WM8994_IRQ_MIC2_DET,
3477                                          wm8994_mic_irq, "Mic 2 detect",
3478                                          wm8994);
3479                 if (ret != 0)
3480                         dev_warn(codec->dev,
3481                                  "Failed to request Mic2 detect IRQ: %d\n",
3482                                  ret);
3483
3484                 ret = wm8994_request_irq(wm8994->wm8994,
3485                                          WM8994_IRQ_MIC2_SHRT,
3486                                          wm8994_mic_irq, "Mic 2 short",
3487                                          wm8994);
3488                 if (ret != 0)
3489                         dev_warn(codec->dev,
3490                                  "Failed to request Mic2 short IRQ: %d\n",
3491                                  ret);
3492                 break;
3493
3494         case WM8958:
3495         case WM1811:
3496                 if (wm8994->micdet_irq) {
3497                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3498                                                    wm8958_mic_irq,
3499                                                    IRQF_TRIGGER_RISING,
3500                                                    "Mic detect",
3501                                                    wm8994);
3502                         if (ret != 0)
3503                                 dev_warn(codec->dev,
3504                                          "Failed to request Mic detect IRQ: %d\n",
3505                                          ret);
3506                 }
3507         }
3508
3509         switch (control->type) {
3510         case WM1811:
3511                 if (wm8994->revision > 1) {
3512                         ret = wm8994_request_irq(wm8994->wm8994,
3513                                                  WM8994_IRQ_GPIO(6),
3514                                                  wm1811_jackdet_irq, "JACKDET",
3515                                                  wm8994);
3516                         if (ret == 0)
3517                                 wm8994->jackdet = true;
3518                 }
3519                 break;
3520         default:
3521                 break;
3522         }
3523
3524         wm8994->fll_locked_irq = true;
3525         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3526                 ret = wm8994_request_irq(wm8994->wm8994,
3527                                          WM8994_IRQ_FLL1_LOCK + i,
3528                                          wm8994_fll_locked_irq, "FLL lock",
3529                                          &wm8994->fll_locked[i]);
3530                 if (ret != 0)
3531                         wm8994->fll_locked_irq = false;
3532         }
3533
3534         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3535          * configured on init - if a system wants to do this dynamically
3536          * at runtime we can deal with that then.
3537          */
3538         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3539         if (ret < 0) {
3540                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3541                 goto err_irq;
3542         }
3543         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3544                 wm8994->lrclk_shared[0] = 1;
3545                 wm8994_dai[0].symmetric_rates = 1;
3546         } else {
3547                 wm8994->lrclk_shared[0] = 0;
3548         }
3549
3550         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3551         if (ret < 0) {
3552                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3553                 goto err_irq;
3554         }
3555         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3556                 wm8994->lrclk_shared[1] = 1;
3557                 wm8994_dai[1].symmetric_rates = 1;
3558         } else {
3559                 wm8994->lrclk_shared[1] = 0;
3560         }
3561
3562         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3563
3564         /* Latch volume updates (right only; we always do left then right). */
3565         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3566                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3567         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3568                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3569         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3570                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3571         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3572                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3573         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3574                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3575         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3576                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3577         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3578                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3579         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3580                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3581         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3582                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3583         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3584                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3585         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3586                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3587         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3588                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3589         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3590                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3591         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3592                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3593         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3594                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3595         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3596                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3597
3598         /* Set the low bit of the 3D stereo depth so TLV matches */
3599         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3600                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3601                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3602         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3603                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3604                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3605         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3606                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3607                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3608
3609         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3610          * use this; it only affects behaviour on idle TDM clock
3611          * cycles. */
3612         switch (control->type) {
3613         case WM8994:
3614         case WM8958:
3615                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3616                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3617                 break;
3618         default:
3619                 break;
3620         }
3621
3622         /* Put MICBIAS into bypass mode by default on newer devices */
3623         switch (control->type) {
3624         case WM8958:
3625         case WM1811:
3626                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3627                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3628                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3629                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3630                 break;
3631         default:
3632                 break;
3633         }
3634
3635         wm8994_update_class_w(codec);
3636
3637         wm8994_handle_pdata(wm8994);
3638
3639         wm_hubs_add_analogue_controls(codec);
3640         snd_soc_add_controls(codec, wm8994_snd_controls,
3641                              ARRAY_SIZE(wm8994_snd_controls));
3642         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3643                                   ARRAY_SIZE(wm8994_dapm_widgets));
3644
3645         switch (control->type) {
3646         case WM8994:
3647                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3648                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3649                 if (wm8994->revision < 4) {
3650                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3651                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3652                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3653                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3654                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3655                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3656                 } else {
3657                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3658                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3659                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3660                                                   ARRAY_SIZE(wm8994_adc_widgets));
3661                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3662                                                   ARRAY_SIZE(wm8994_dac_widgets));
3663                 }
3664                 break;
3665         case WM8958:
3666                 snd_soc_add_controls(codec, wm8958_snd_controls,
3667                                      ARRAY_SIZE(wm8958_snd_controls));
3668                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3669                                           ARRAY_SIZE(wm8958_dapm_widgets));
3670                 if (wm8994->revision < 1) {
3671                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3672                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3673                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3674                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3675                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3676                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3677                 } else {
3678                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3679                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3680                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3681                                                   ARRAY_SIZE(wm8994_adc_widgets));
3682                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3683                                                   ARRAY_SIZE(wm8994_dac_widgets));
3684                 }
3685                 break;
3686
3687         case WM1811:
3688                 snd_soc_add_controls(codec, wm8958_snd_controls,
3689                                      ARRAY_SIZE(wm8958_snd_controls));
3690                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3691                                           ARRAY_SIZE(wm8958_dapm_widgets));
3692                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3693                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3694                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3695                                           ARRAY_SIZE(wm8994_adc_widgets));
3696                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3697                                           ARRAY_SIZE(wm8994_dac_widgets));
3698                 break;
3699         }
3700
3701
3702         wm_hubs_add_analogue_routes(codec, 0, 0);
3703         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3704
3705         switch (control->type) {
3706         case WM8994:
3707                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3708                                         ARRAY_SIZE(wm8994_intercon));
3709
3710                 if (wm8994->revision < 4) {
3711                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3712                                                 ARRAY_SIZE(wm8994_revd_intercon));
3713                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3714                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3715                 } else {
3716                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3717                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3718                 }
3719                 break;
3720         case WM8958:
3721                 if (wm8994->revision < 1) {
3722                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3723                                                 ARRAY_SIZE(wm8994_revd_intercon));
3724                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3725                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3726                 } else {
3727                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3728                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3729                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3730                                                 ARRAY_SIZE(wm8958_intercon));
3731                 }
3732
3733                 wm8958_dsp2_init(codec);
3734                 break;
3735         case WM1811:
3736                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3737                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3738                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3739                                         ARRAY_SIZE(wm8958_intercon));
3740                 break;
3741         }
3742
3743         return 0;
3744
3745 err_irq:
3746         if (wm8994->jackdet)
3747                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3748         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3749         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3750         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3751         if (wm8994->micdet_irq)
3752                 free_irq(wm8994->micdet_irq, wm8994);
3753         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3754                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3755                                 &wm8994->fll_locked[i]);
3756         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3757                         &wm8994->hubs);
3758         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3759         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3760         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3761
3762         return ret;
3763 }
3764
3765 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3766 {
3767         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3768         struct wm8994 *control = wm8994->wm8994;
3769         int i;
3770
3771         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3772
3773         pm_runtime_disable(codec->dev);
3774
3775         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3776                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3777                                 &wm8994->fll_locked[i]);
3778
3779         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3780                         &wm8994->hubs);
3781         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3782         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3783         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3784
3785         if (wm8994->jackdet)
3786                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3787
3788         switch (control->type) {
3789         case WM8994:
3790                 if (wm8994->micdet_irq)
3791                         free_irq(wm8994->micdet_irq, wm8994);
3792                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3793                                 wm8994);
3794                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3795                                 wm8994);
3796                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3797                                 wm8994);
3798                 break;
3799
3800         case WM1811:
3801         case WM8958:
3802                 if (wm8994->micdet_irq)
3803                         free_irq(wm8994->micdet_irq, wm8994);
3804                 break;
3805         }
3806         if (wm8994->mbc)
3807                 release_firmware(wm8994->mbc);
3808         if (wm8994->mbc_vss)
3809                 release_firmware(wm8994->mbc_vss);
3810         if (wm8994->enh_eq)
3811                 release_firmware(wm8994->enh_eq);
3812         kfree(wm8994->retune_mobile_texts);
3813
3814         return 0;
3815 }
3816
3817 static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3818                                unsigned int reg)
3819 {
3820         return true;
3821 }
3822
3823 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3824         .probe =        wm8994_codec_probe,
3825         .remove =       wm8994_codec_remove,
3826         .suspend =      wm8994_suspend,
3827         .resume =       wm8994_resume,
3828         .set_bias_level = wm8994_set_bias_level,
3829         .reg_cache_size = WM8994_MAX_REGISTER,
3830         .volatile_register = wm8994_soc_volatile,
3831 };
3832
3833 static int __devinit wm8994_probe(struct platform_device *pdev)
3834 {
3835         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3836                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3837 }
3838
3839 static int __devexit wm8994_remove(struct platform_device *pdev)
3840 {
3841         snd_soc_unregister_codec(&pdev->dev);
3842         return 0;
3843 }
3844
3845 static struct platform_driver wm8994_codec_driver = {
3846         .driver = {
3847                    .name = "wm8994-codec",
3848                    .owner = THIS_MODULE,
3849                    },
3850         .probe = wm8994_probe,
3851         .remove = __devexit_p(wm8994_remove),
3852 };
3853
3854 module_platform_driver(wm8994_codec_driver);
3855
3856 MODULE_DESCRIPTION("ASoC WM8994 driver");
3857 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3858 MODULE_LICENSE("GPL");
3859 MODULE_ALIAS("platform:wm8994-codec");