2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
30 #include <sound/wm9081.h>
33 static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
101 } clk_sys_rates[] = {
132 int div; /* *10 due to .5s */
159 struct snd_soc_codec codec;
160 u16 reg_cache[WM9081_MAX_REGISTER + 1];
170 struct wm9081_retune_mobile_config *retune;
173 static int wm9081_volatile_register(unsigned int reg)
176 case WM9081_SOFTWARE_RESET:
183 static int wm9081_reset(struct snd_soc_codec *codec)
185 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
188 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
189 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
190 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
191 static unsigned int drc_max_tlv[] = {
192 TLV_DB_RANGE_HEAD(4),
193 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
194 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
195 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
196 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
198 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
199 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
201 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
203 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
204 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
205 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
207 static const char *drc_high_text[] = {
216 static const struct soc_enum drc_high =
217 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
219 static const char *drc_low_text[] = {
227 static const struct soc_enum drc_low =
228 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
230 static const char *drc_atk_text[] = {
245 static const struct soc_enum drc_atk =
246 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
248 static const char *drc_dcy_text[] = {
260 static const struct soc_enum drc_dcy =
261 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
263 static const char *drc_qr_dcy_text[] = {
269 static const struct soc_enum drc_qr_dcy =
270 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
272 static const char *dac_deemph_text[] = {
279 static const struct soc_enum dac_deemph =
280 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
282 static const char *speaker_mode_text[] = {
287 static const struct soc_enum speaker_mode =
288 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
290 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
291 struct snd_ctl_elem_value *ucontrol)
293 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
296 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
297 if (reg & WM9081_SPK_MODE)
298 ucontrol->value.integer.value[0] = 1;
300 ucontrol->value.integer.value[0] = 0;
306 * Stop any attempts to change speaker mode while the speaker is enabled.
308 * We also have some special anti-pop controls dependant on speaker
309 * mode which must be changed along with the mode.
311 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
314 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
315 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
316 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
318 /* Are we changing anything? */
319 if (ucontrol->value.integer.value[0] ==
320 ((reg2 & WM9081_SPK_MODE) != 0))
323 /* Don't try to change modes while enabled */
324 if (reg_pwr & WM9081_SPK_ENA)
327 if (ucontrol->value.integer.value[0]) {
329 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
330 reg2 |= WM9081_SPK_MODE;
333 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
334 reg2 &= ~WM9081_SPK_MODE;
337 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
342 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
343 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
344 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
346 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
348 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
349 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
350 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
352 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
353 SOC_ENUM("DRC High Slope", drc_high),
354 SOC_ENUM("DRC Low Slope", drc_low),
355 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
356 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
357 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
358 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
359 SOC_ENUM("DRC Attack", drc_atk),
360 SOC_ENUM("DRC Decay", drc_dcy),
361 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
362 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
363 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
364 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
366 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
368 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
369 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
370 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
371 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
372 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
374 SOC_ENUM("DAC Deemphasis", dac_deemph),
375 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
378 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
379 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
380 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
381 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
382 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
383 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
386 static const struct snd_kcontrol_new mixer[] = {
387 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
388 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
389 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
392 static int speaker_event(struct snd_soc_dapm_widget *w,
393 struct snd_kcontrol *kcontrol, int event)
395 struct snd_soc_codec *codec = w->codec;
396 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
399 case SND_SOC_DAPM_POST_PMU:
400 reg |= WM9081_SPK_ENA;
403 case SND_SOC_DAPM_PRE_PMD:
404 reg &= ~WM9081_SPK_ENA;
408 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
421 /* The size in bits of the FLL divide multiplied by 10
422 * to allow rounding later */
423 #define FIXED_FLL_SIZE ((1 << 16) * 10)
432 { 64000, 128000, 3, 8 },
433 { 128000, 256000, 2, 4 },
434 { 256000, 1000000, 1, 2 },
435 { 1000000, 13500000, 0, 1 },
438 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
442 unsigned int K, Ndiv, Nmod, target;
446 /* Fref must be <=13.5MHz */
448 while ((Fref / div) > 13500000) {
452 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
457 fll_div->fll_clk_ref_div = div / 2;
459 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
461 /* Apply the division for our remaining calculations */
464 /* Fvco should be 90-100MHz; don't check the upper bound */
467 while (target < 90000000) {
471 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
476 fll_div->fll_outdiv = div;
478 pr_debug("Fvco=%dHz\n", target);
480 /* Find an appropraite FLL_FRATIO and factor it out of the target */
481 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
482 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
483 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
484 target /= fll_fratios[i].ratio;
488 if (i == ARRAY_SIZE(fll_fratios)) {
489 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
493 /* Now, calculate N.K */
494 Ndiv = target / Fref;
497 Nmod = target % Fref;
498 pr_debug("Nmod=%d\n", Nmod);
500 /* Calculate fractional part - scale up so we can round. */
501 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
505 K = Kpart & 0xFFFFFFFF;
510 /* Move down to proper range now rounding is done */
513 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
514 fll_div->n, fll_div->k,
515 fll_div->fll_fratio, fll_div->fll_outdiv,
516 fll_div->fll_clk_ref_div);
521 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
522 unsigned int Fref, unsigned int Fout)
524 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
525 u16 reg1, reg4, reg5;
526 struct _fll_div fll_div;
531 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
534 /* Disable the FLL */
536 dev_dbg(codec->dev, "FLL disabled\n");
537 wm9081->fll_fref = 0;
538 wm9081->fll_fout = 0;
543 ret = fll_factors(&fll_div, Fref, Fout);
547 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
548 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
551 case WM9081_SYSCLK_FLL_MCLK:
556 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
560 /* Disable CLK_SYS while we reconfigure */
561 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
562 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
563 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
564 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
566 /* Any FLL configuration change requires that the FLL be
568 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
569 reg1 &= ~WM9081_FLL_ENA;
570 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
572 /* Apply the configuration */
574 reg1 |= WM9081_FLL_FRAC_MASK;
576 reg1 &= ~WM9081_FLL_FRAC_MASK;
577 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
579 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
580 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
581 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
582 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
584 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
585 reg4 &= ~WM9081_FLL_N_MASK;
586 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
587 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
589 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
590 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
591 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
594 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
596 /* Then bring CLK_SYS up again if it was disabled */
597 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
598 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
600 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
602 wm9081->fll_fref = Fref;
603 wm9081->fll_fout = Fout;
608 static int configure_clock(struct snd_soc_codec *codec)
610 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
611 int new_sysclk, i, target;
617 switch (wm9081->sysclk_source) {
618 case WM9081_SYSCLK_MCLK:
619 if (wm9081->mclk_rate > 12225000) {
621 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
623 wm9081->sysclk_rate = wm9081->mclk_rate;
625 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
628 case WM9081_SYSCLK_FLL_MCLK:
629 /* If we have a sample rate calculate a CLK_SYS that
630 * gives us a suitable DAC configuration, plus BCLK.
631 * Ideally we would check to see if we can clock
632 * directly from MCLK and only use the FLL if this is
633 * not the case, though care must be taken with free
636 if (wm9081->master && wm9081->bclk) {
637 /* Make sure we can generate CLK_SYS and BCLK
638 * and that we've got 3MHz for optimal
640 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
641 target = wm9081->fs * clk_sys_rates[i].ratio;
643 if (target >= wm9081->bclk &&
648 if (i == ARRAY_SIZE(clk_sys_rates))
651 } else if (wm9081->fs) {
652 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
653 new_sysclk = clk_sys_rates[i].ratio
655 if (new_sysclk > 3000000)
659 if (i == ARRAY_SIZE(clk_sys_rates))
663 new_sysclk = 12288000;
666 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
667 wm9081->mclk_rate, new_sysclk);
669 wm9081->sysclk_rate = new_sysclk;
671 /* Switch SYSCLK over to FLL */
674 wm9081->sysclk_rate = wm9081->mclk_rate;
682 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
684 reg |= WM9081_MCLKDIV2;
686 reg &= ~WM9081_MCLKDIV2;
687 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
689 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
691 reg |= WM9081_CLK_SRC_SEL;
693 reg &= ~WM9081_CLK_SRC_SEL;
694 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
696 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
701 static int clk_sys_event(struct snd_soc_dapm_widget *w,
702 struct snd_kcontrol *kcontrol, int event)
704 struct snd_soc_codec *codec = w->codec;
705 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
707 /* This should be done on init() for bypass paths */
708 switch (wm9081->sysclk_source) {
709 case WM9081_SYSCLK_MCLK:
710 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
712 case WM9081_SYSCLK_FLL_MCLK:
713 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
717 dev_err(codec->dev, "System clock not configured\n");
722 case SND_SOC_DAPM_PRE_PMU:
723 configure_clock(codec);
726 case SND_SOC_DAPM_POST_PMD:
727 /* Disable the FLL if it's running */
728 wm9081_set_fll(codec, 0, 0, 0);
735 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
736 SND_SOC_DAPM_INPUT("IN1"),
737 SND_SOC_DAPM_INPUT("IN2"),
739 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
741 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
742 mixer, ARRAY_SIZE(mixer)),
744 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
746 SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
748 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
750 SND_SOC_DAPM_OUTPUT("LINEOUT"),
751 SND_SOC_DAPM_OUTPUT("SPKN"),
752 SND_SOC_DAPM_OUTPUT("SPKP"),
754 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
755 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
756 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
757 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
761 static const struct snd_soc_dapm_route audio_paths[] = {
762 { "DAC", NULL, "CLK_SYS" },
763 { "DAC", NULL, "CLK_DSP" },
765 { "Mixer", "IN1 Switch", "IN1" },
766 { "Mixer", "IN2 Switch", "IN2" },
767 { "Mixer", "Playback Switch", "DAC" },
769 { "LINEOUT PGA", NULL, "Mixer" },
770 { "LINEOUT PGA", NULL, "TOCLK" },
771 { "LINEOUT PGA", NULL, "CLK_SYS" },
773 { "LINEOUT", NULL, "LINEOUT PGA" },
775 { "Speaker PGA", NULL, "Mixer" },
776 { "Speaker PGA", NULL, "TOCLK" },
777 { "Speaker PGA", NULL, "CLK_SYS" },
779 { "SPKN", NULL, "Speaker PGA" },
780 { "SPKP", NULL, "Speaker PGA" },
783 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
784 enum snd_soc_bias_level level)
789 case SND_SOC_BIAS_ON:
792 case SND_SOC_BIAS_PREPARE:
794 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
795 reg &= ~WM9081_VMID_SEL_MASK;
797 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
799 /* Normal bias current */
800 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
801 reg &= ~WM9081_STBY_BIAS_ENA;
802 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
805 case SND_SOC_BIAS_STANDBY:
806 /* Initial cold start */
807 if (codec->bias_level == SND_SOC_BIAS_OFF) {
808 /* Disable LINEOUT discharge */
809 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
810 reg &= ~WM9081_LINEOUT_DISCH;
811 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
813 /* Select startup bias source */
814 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
815 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
816 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
818 /* VMID 2*4k; Soft VMID ramp enable */
819 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
820 reg |= WM9081_VMID_RAMP | 0x6;
821 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
825 /* Normal bias enable & soft start off */
826 reg |= WM9081_BIAS_ENA;
827 reg &= ~WM9081_VMID_RAMP;
828 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
830 /* Standard bias source */
831 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
832 reg &= ~WM9081_BIAS_SRC;
833 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
837 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
838 reg &= ~WM9081_VMID_SEL_MASK;
840 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
842 /* Standby bias current on */
843 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
844 reg |= WM9081_STBY_BIAS_ENA;
845 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
848 case SND_SOC_BIAS_OFF:
849 /* Startup bias source */
850 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
851 reg |= WM9081_BIAS_SRC;
852 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
854 /* Disable VMID and biases with soft ramping */
855 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
856 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
857 reg |= WM9081_VMID_RAMP;
858 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
860 /* Actively discharge LINEOUT */
861 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
862 reg |= WM9081_LINEOUT_DISCH;
863 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
867 codec->bias_level = level;
872 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
875 struct snd_soc_codec *codec = dai->codec;
876 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
877 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
879 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
880 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
882 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
883 case SND_SOC_DAIFMT_CBS_CFS:
886 case SND_SOC_DAIFMT_CBS_CFM:
887 aif2 |= WM9081_LRCLK_DIR;
890 case SND_SOC_DAIFMT_CBM_CFS:
891 aif2 |= WM9081_BCLK_DIR;
894 case SND_SOC_DAIFMT_CBM_CFM:
895 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
902 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
903 case SND_SOC_DAIFMT_DSP_B:
904 aif2 |= WM9081_AIF_LRCLK_INV;
905 case SND_SOC_DAIFMT_DSP_A:
908 case SND_SOC_DAIFMT_I2S:
911 case SND_SOC_DAIFMT_RIGHT_J:
913 case SND_SOC_DAIFMT_LEFT_J:
920 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
921 case SND_SOC_DAIFMT_DSP_A:
922 case SND_SOC_DAIFMT_DSP_B:
923 /* frame inversion not valid for DSP modes */
924 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
925 case SND_SOC_DAIFMT_NB_NF:
927 case SND_SOC_DAIFMT_IB_NF:
928 aif2 |= WM9081_AIF_BCLK_INV;
935 case SND_SOC_DAIFMT_I2S:
936 case SND_SOC_DAIFMT_RIGHT_J:
937 case SND_SOC_DAIFMT_LEFT_J:
938 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
939 case SND_SOC_DAIFMT_NB_NF:
941 case SND_SOC_DAIFMT_IB_IF:
942 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
944 case SND_SOC_DAIFMT_IB_NF:
945 aif2 |= WM9081_AIF_BCLK_INV;
947 case SND_SOC_DAIFMT_NB_IF:
948 aif2 |= WM9081_AIF_LRCLK_INV;
958 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
963 static int wm9081_hw_params(struct snd_pcm_substream *substream,
964 struct snd_pcm_hw_params *params,
965 struct snd_soc_dai *dai)
967 struct snd_soc_codec *codec = dai->codec;
968 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
969 int ret, i, best, best_val, cur_val;
970 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
972 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
973 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
975 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
977 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
978 aif2 &= ~WM9081_AIF_WL_MASK;
980 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
981 aif3 &= ~WM9081_BCLK_DIV_MASK;
983 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
984 aif4 &= ~WM9081_LRCLK_RATE_MASK;
986 wm9081->fs = params_rate(params);
988 if (wm9081->tdm_width) {
989 /* If TDM is set up then that fixes our BCLK. */
990 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
991 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
993 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
995 /* Otherwise work out a BCLK from the sample size */
996 wm9081->bclk = 2 * wm9081->fs;
998 switch (params_format(params)) {
999 case SNDRV_PCM_FORMAT_S16_LE:
1002 case SNDRV_PCM_FORMAT_S20_3LE:
1006 case SNDRV_PCM_FORMAT_S24_LE:
1010 case SNDRV_PCM_FORMAT_S32_LE:
1019 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1021 ret = configure_clock(codec);
1025 /* Select nearest CLK_SYS_RATE */
1027 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1029 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1030 cur_val = abs((wm9081->sysclk_rate /
1031 clk_sys_rates[i].ratio) - wm9081->fs);
1032 if (cur_val < best_val) {
1037 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1038 clk_sys_rates[best].ratio);
1039 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1040 << WM9081_CLK_SYS_RATE_SHIFT);
1044 best_val = abs(wm9081->fs - sample_rates[0].rate);
1045 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1047 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1048 if (cur_val < best_val) {
1053 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1054 sample_rates[best].rate);
1055 clk_ctrl2 |= (sample_rates[best].sample_rate
1056 << WM9081_SAMPLE_RATE_SHIFT);
1061 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1062 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1064 if (cur_val < 0) /* Table is sorted */
1066 if (cur_val < best_val) {
1071 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1072 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1073 bclk_divs[best].div, wm9081->bclk);
1074 aif3 |= bclk_divs[best].bclk_div;
1076 /* LRCLK is a simple fraction of BCLK */
1077 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1078 aif4 |= wm9081->bclk / wm9081->fs;
1080 /* Apply a ReTune Mobile configuration if it's in use */
1081 if (wm9081->retune) {
1082 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1083 struct wm9081_retune_mobile_setting *s;
1087 best_val = abs(retune->configs[0].rate - wm9081->fs);
1088 for (i = 0; i < retune->num_configs; i++) {
1089 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1090 if (cur_val < best_val) {
1095 s = &retune->configs[best];
1097 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1100 /* If the EQ is enabled then disable it while we write out */
1101 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1102 if (eq1 & WM9081_EQ_ENA)
1103 snd_soc_write(codec, WM9081_EQ_1, 0);
1105 /* Write out the other values */
1106 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1107 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1109 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1110 snd_soc_write(codec, WM9081_EQ_1, eq1);
1113 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1114 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1115 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1116 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1121 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1123 struct snd_soc_codec *codec = codec_dai->codec;
1126 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1129 reg |= WM9081_DAC_MUTE;
1131 reg &= ~WM9081_DAC_MUTE;
1133 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1138 static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1139 int clk_id, unsigned int freq, int dir)
1141 struct snd_soc_codec *codec = codec_dai->codec;
1142 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1145 case WM9081_SYSCLK_MCLK:
1146 case WM9081_SYSCLK_FLL_MCLK:
1147 wm9081->sysclk_source = clk_id;
1148 wm9081->mclk_rate = freq;
1158 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1159 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1161 struct snd_soc_codec *codec = dai->codec;
1162 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1163 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1165 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1167 if (slots < 0 || slots > 4)
1170 wm9081->tdm_width = slot_width;
1175 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1193 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1198 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1200 #define WM9081_FORMATS \
1201 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1202 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1204 static struct snd_soc_dai_ops wm9081_dai_ops = {
1205 .hw_params = wm9081_hw_params,
1206 .set_sysclk = wm9081_set_sysclk,
1207 .set_fmt = wm9081_set_dai_fmt,
1208 .digital_mute = wm9081_digital_mute,
1209 .set_tdm_slot = wm9081_set_tdm_slot,
1212 /* We report two channels because the CODEC processes a stereo signal, even
1213 * though it is only capable of handling a mono output.
1215 struct snd_soc_dai wm9081_dai = {
1218 .stream_name = "HiFi Playback",
1221 .rates = WM9081_RATES,
1222 .formats = WM9081_FORMATS,
1224 .ops = &wm9081_dai_ops,
1226 EXPORT_SYMBOL_GPL(wm9081_dai);
1229 static struct snd_soc_codec *wm9081_codec;
1231 static int wm9081_probe(struct platform_device *pdev)
1233 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1234 struct snd_soc_codec *codec;
1235 struct wm9081_priv *wm9081;
1238 if (wm9081_codec == NULL) {
1239 dev_err(&pdev->dev, "Codec device not registered\n");
1243 socdev->card->codec = wm9081_codec;
1244 codec = wm9081_codec;
1245 wm9081 = snd_soc_codec_get_drvdata(codec);
1248 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1250 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
1254 snd_soc_add_controls(codec, wm9081_snd_controls,
1255 ARRAY_SIZE(wm9081_snd_controls));
1256 if (!wm9081->retune) {
1258 "No ReTune Mobile data, using normal EQ\n");
1259 snd_soc_add_controls(codec, wm9081_eq_controls,
1260 ARRAY_SIZE(wm9081_eq_controls));
1263 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1264 ARRAY_SIZE(wm9081_dapm_widgets));
1265 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1273 static int wm9081_remove(struct platform_device *pdev)
1275 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1277 snd_soc_free_pcms(socdev);
1278 snd_soc_dapm_free(socdev);
1284 static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
1286 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1287 struct snd_soc_codec *codec = socdev->card->codec;
1289 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1294 static int wm9081_resume(struct platform_device *pdev)
1296 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1297 struct snd_soc_codec *codec = socdev->card->codec;
1298 u16 *reg_cache = codec->reg_cache;
1301 for (i = 0; i < codec->reg_cache_size; i++) {
1302 if (i == WM9081_SOFTWARE_RESET)
1305 snd_soc_write(codec, i, reg_cache[i]);
1308 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1313 #define wm9081_suspend NULL
1314 #define wm9081_resume NULL
1317 struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1318 .probe = wm9081_probe,
1319 .remove = wm9081_remove,
1320 .suspend = wm9081_suspend,
1321 .resume = wm9081_resume,
1323 EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1325 static int wm9081_register(struct wm9081_priv *wm9081,
1326 enum snd_soc_control_type control)
1328 struct snd_soc_codec *codec = &wm9081->codec;
1333 dev_err(codec->dev, "Another WM9081 is registered\n");
1338 mutex_init(&codec->mutex);
1339 INIT_LIST_HEAD(&codec->dapm_widgets);
1340 INIT_LIST_HEAD(&codec->dapm_paths);
1342 snd_soc_codec_set_drvdata(codec, wm9081);
1343 codec->name = "WM9081";
1344 codec->owner = THIS_MODULE;
1345 codec->dai = &wm9081_dai;
1347 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1348 codec->reg_cache = &wm9081->reg_cache;
1349 codec->bias_level = SND_SOC_BIAS_OFF;
1350 codec->set_bias_level = wm9081_set_bias_level;
1351 codec->volatile_register = wm9081_volatile_register;
1353 memcpy(codec->reg_cache, wm9081_reg_defaults,
1354 sizeof(wm9081_reg_defaults));
1356 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1358 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1362 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1363 if (reg != 0x9081) {
1364 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1369 ret = wm9081_reset(codec);
1371 dev_err(codec->dev, "Failed to issue reset\n");
1375 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1377 /* Enable zero cross by default */
1378 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1379 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1380 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1381 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1382 reg | WM9081_SPKPGAZC);
1384 wm9081_dai.dev = codec->dev;
1386 wm9081_codec = codec;
1388 ret = snd_soc_register_codec(codec);
1390 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1394 ret = snd_soc_register_dai(&wm9081_dai);
1396 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1403 snd_soc_unregister_codec(codec);
1409 static void wm9081_unregister(struct wm9081_priv *wm9081)
1411 wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
1412 snd_soc_unregister_dai(&wm9081_dai);
1413 snd_soc_unregister_codec(&wm9081->codec);
1415 wm9081_codec = NULL;
1418 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1419 const struct i2c_device_id *id)
1421 struct wm9081_priv *wm9081;
1422 struct snd_soc_codec *codec;
1424 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1428 codec = &wm9081->codec;
1429 codec->hw_write = (hw_write_t)i2c_master_send;
1430 wm9081->retune = i2c->dev.platform_data;
1432 i2c_set_clientdata(i2c, wm9081);
1433 codec->control_data = i2c;
1435 codec->dev = &i2c->dev;
1437 return wm9081_register(wm9081, SND_SOC_I2C);
1440 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1442 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1443 wm9081_unregister(wm9081);
1447 static const struct i2c_device_id wm9081_i2c_id[] = {
1451 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1453 static struct i2c_driver wm9081_i2c_driver = {
1456 .owner = THIS_MODULE,
1458 .probe = wm9081_i2c_probe,
1459 .remove = __devexit_p(wm9081_i2c_remove),
1460 .id_table = wm9081_i2c_id,
1463 static int __init wm9081_modinit(void)
1467 ret = i2c_add_driver(&wm9081_i2c_driver);
1469 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1475 module_init(wm9081_modinit);
1477 static void __exit wm9081_exit(void)
1479 i2c_del_driver(&wm9081_i2c_driver);
1481 module_exit(wm9081_exit);
1484 MODULE_DESCRIPTION("ASoC WM9081 driver");
1485 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1486 MODULE_LICENSE("GPL");