2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009 Wolfson Microelectronics plc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
30 #include <sound/wm9081.h>
33 static u16 wm9081_reg_defaults[] = {
34 0x0000, /* R0 - Software Reset */
36 0x00B9, /* R2 - Analogue Lineout */
37 0x00B9, /* R3 - Analogue Speaker PGA */
38 0x0001, /* R4 - VMID Control */
39 0x0068, /* R5 - Bias Control 1 */
41 0x0000, /* R7 - Analogue Mixer */
42 0x0000, /* R8 - Anti Pop Control */
43 0x01DB, /* R9 - Analogue Speaker 1 */
44 0x0018, /* R10 - Analogue Speaker 2 */
45 0x0180, /* R11 - Power Management */
46 0x0000, /* R12 - Clock Control 1 */
47 0x0038, /* R13 - Clock Control 2 */
48 0x4000, /* R14 - Clock Control 3 */
50 0x0000, /* R16 - FLL Control 1 */
51 0x0200, /* R17 - FLL Control 2 */
52 0x0000, /* R18 - FLL Control 3 */
53 0x0204, /* R19 - FLL Control 4 */
54 0x0000, /* R20 - FLL Control 5 */
56 0x0000, /* R22 - Audio Interface 1 */
57 0x0002, /* R23 - Audio Interface 2 */
58 0x0008, /* R24 - Audio Interface 3 */
59 0x0022, /* R25 - Audio Interface 4 */
60 0x0000, /* R26 - Interrupt Status */
61 0x0006, /* R27 - Interrupt Status Mask */
62 0x0000, /* R28 - Interrupt Polarity */
63 0x0000, /* R29 - Interrupt Control */
64 0x00C0, /* R30 - DAC Digital 1 */
65 0x0008, /* R31 - DAC Digital 2 */
66 0x09AF, /* R32 - DRC 1 */
67 0x4201, /* R33 - DRC 2 */
68 0x0000, /* R34 - DRC 3 */
69 0x0000, /* R35 - DRC 4 */
72 0x0000, /* R38 - Write Sequencer 1 */
73 0x0000, /* R39 - Write Sequencer 2 */
74 0x0002, /* R40 - MW Slave 1 */
76 0x0000, /* R42 - EQ 1 */
77 0x0000, /* R43 - EQ 2 */
78 0x0FCA, /* R44 - EQ 3 */
79 0x0400, /* R45 - EQ 4 */
80 0x00B8, /* R46 - EQ 5 */
81 0x1EB5, /* R47 - EQ 6 */
82 0xF145, /* R48 - EQ 7 */
83 0x0B75, /* R49 - EQ 8 */
84 0x01C5, /* R50 - EQ 9 */
85 0x169E, /* R51 - EQ 10 */
86 0xF829, /* R52 - EQ 11 */
87 0x07AD, /* R53 - EQ 12 */
88 0x1103, /* R54 - EQ 13 */
89 0x1C58, /* R55 - EQ 14 */
90 0xF373, /* R56 - EQ 15 */
91 0x0A54, /* R57 - EQ 16 */
92 0x0558, /* R58 - EQ 17 */
93 0x0564, /* R59 - EQ 18 */
94 0x0559, /* R60 - EQ 19 */
95 0x4000, /* R61 - EQ 20 */
101 } clk_sys_rates[] = {
132 int div; /* *10 due to .5s */
159 enum snd_soc_control_type control_type;
161 u16 reg_cache[WM9081_MAX_REGISTER + 1];
171 struct wm9081_retune_mobile_config *retune;
174 static int wm9081_volatile_register(unsigned int reg)
177 case WM9081_SOFTWARE_RESET:
184 static int wm9081_reset(struct snd_soc_codec *codec)
186 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
189 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
190 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
191 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
192 static unsigned int drc_max_tlv[] = {
193 TLV_DB_RANGE_HEAD(4),
194 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
195 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
196 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
197 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
199 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
200 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
202 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
204 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
205 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
206 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
208 static const char *drc_high_text[] = {
217 static const struct soc_enum drc_high =
218 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
220 static const char *drc_low_text[] = {
228 static const struct soc_enum drc_low =
229 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
231 static const char *drc_atk_text[] = {
246 static const struct soc_enum drc_atk =
247 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
249 static const char *drc_dcy_text[] = {
261 static const struct soc_enum drc_dcy =
262 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
264 static const char *drc_qr_dcy_text[] = {
270 static const struct soc_enum drc_qr_dcy =
271 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
273 static const char *dac_deemph_text[] = {
280 static const struct soc_enum dac_deemph =
281 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
283 static const char *speaker_mode_text[] = {
288 static const struct soc_enum speaker_mode =
289 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
291 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
292 struct snd_ctl_elem_value *ucontrol)
294 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
297 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
298 if (reg & WM9081_SPK_MODE)
299 ucontrol->value.integer.value[0] = 1;
301 ucontrol->value.integer.value[0] = 0;
307 * Stop any attempts to change speaker mode while the speaker is enabled.
309 * We also have some special anti-pop controls dependant on speaker
310 * mode which must be changed along with the mode.
312 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
315 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
316 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
317 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
319 /* Are we changing anything? */
320 if (ucontrol->value.integer.value[0] ==
321 ((reg2 & WM9081_SPK_MODE) != 0))
324 /* Don't try to change modes while enabled */
325 if (reg_pwr & WM9081_SPK_ENA)
328 if (ucontrol->value.integer.value[0]) {
330 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
331 reg2 |= WM9081_SPK_MODE;
334 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
335 reg2 &= ~WM9081_SPK_MODE;
338 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
343 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
344 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
345 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
347 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
349 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
350 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
351 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
353 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
354 SOC_ENUM("DRC High Slope", drc_high),
355 SOC_ENUM("DRC Low Slope", drc_low),
356 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
357 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
358 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
359 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
360 SOC_ENUM("DRC Attack", drc_atk),
361 SOC_ENUM("DRC Decay", drc_dcy),
362 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
363 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
364 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
365 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
367 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
369 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
370 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
371 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
372 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
373 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
375 SOC_ENUM("DAC Deemphasis", dac_deemph),
376 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
379 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
380 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
381 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
382 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
383 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
384 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
387 static const struct snd_kcontrol_new mixer[] = {
388 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
389 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
390 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
393 static int speaker_event(struct snd_soc_dapm_widget *w,
394 struct snd_kcontrol *kcontrol, int event)
396 struct snd_soc_codec *codec = w->codec;
397 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
400 case SND_SOC_DAPM_POST_PMU:
401 reg |= WM9081_SPK_ENA;
404 case SND_SOC_DAPM_PRE_PMD:
405 reg &= ~WM9081_SPK_ENA;
409 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
422 /* The size in bits of the FLL divide multiplied by 10
423 * to allow rounding later */
424 #define FIXED_FLL_SIZE ((1 << 16) * 10)
433 { 64000, 128000, 3, 8 },
434 { 128000, 256000, 2, 4 },
435 { 256000, 1000000, 1, 2 },
436 { 1000000, 13500000, 0, 1 },
439 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
443 unsigned int K, Ndiv, Nmod, target;
447 /* Fref must be <=13.5MHz */
449 while ((Fref / div) > 13500000) {
453 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
458 fll_div->fll_clk_ref_div = div / 2;
460 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
462 /* Apply the division for our remaining calculations */
465 /* Fvco should be 90-100MHz; don't check the upper bound */
468 while (target < 90000000) {
472 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
477 fll_div->fll_outdiv = div;
479 pr_debug("Fvco=%dHz\n", target);
481 /* Find an appropraite FLL_FRATIO and factor it out of the target */
482 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
483 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
484 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
485 target /= fll_fratios[i].ratio;
489 if (i == ARRAY_SIZE(fll_fratios)) {
490 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
494 /* Now, calculate N.K */
495 Ndiv = target / Fref;
498 Nmod = target % Fref;
499 pr_debug("Nmod=%d\n", Nmod);
501 /* Calculate fractional part - scale up so we can round. */
502 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
506 K = Kpart & 0xFFFFFFFF;
511 /* Move down to proper range now rounding is done */
514 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
515 fll_div->n, fll_div->k,
516 fll_div->fll_fratio, fll_div->fll_outdiv,
517 fll_div->fll_clk_ref_div);
522 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
523 unsigned int Fref, unsigned int Fout)
525 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
526 u16 reg1, reg4, reg5;
527 struct _fll_div fll_div;
532 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
535 /* Disable the FLL */
537 dev_dbg(codec->dev, "FLL disabled\n");
538 wm9081->fll_fref = 0;
539 wm9081->fll_fout = 0;
544 ret = fll_factors(&fll_div, Fref, Fout);
548 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
549 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
552 case WM9081_SYSCLK_FLL_MCLK:
557 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
561 /* Disable CLK_SYS while we reconfigure */
562 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
563 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
564 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
565 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
567 /* Any FLL configuration change requires that the FLL be
569 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
570 reg1 &= ~WM9081_FLL_ENA;
571 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
573 /* Apply the configuration */
575 reg1 |= WM9081_FLL_FRAC_MASK;
577 reg1 &= ~WM9081_FLL_FRAC_MASK;
578 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
580 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
581 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
582 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
583 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
585 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
586 reg4 &= ~WM9081_FLL_N_MASK;
587 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
588 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
590 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
591 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
592 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
595 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
597 /* Then bring CLK_SYS up again if it was disabled */
598 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
599 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
601 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
603 wm9081->fll_fref = Fref;
604 wm9081->fll_fout = Fout;
609 static int configure_clock(struct snd_soc_codec *codec)
611 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
612 int new_sysclk, i, target;
618 switch (wm9081->sysclk_source) {
619 case WM9081_SYSCLK_MCLK:
620 if (wm9081->mclk_rate > 12225000) {
622 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
624 wm9081->sysclk_rate = wm9081->mclk_rate;
626 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
629 case WM9081_SYSCLK_FLL_MCLK:
630 /* If we have a sample rate calculate a CLK_SYS that
631 * gives us a suitable DAC configuration, plus BCLK.
632 * Ideally we would check to see if we can clock
633 * directly from MCLK and only use the FLL if this is
634 * not the case, though care must be taken with free
637 if (wm9081->master && wm9081->bclk) {
638 /* Make sure we can generate CLK_SYS and BCLK
639 * and that we've got 3MHz for optimal
641 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
642 target = wm9081->fs * clk_sys_rates[i].ratio;
644 if (target >= wm9081->bclk &&
649 if (i == ARRAY_SIZE(clk_sys_rates))
652 } else if (wm9081->fs) {
653 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
654 new_sysclk = clk_sys_rates[i].ratio
656 if (new_sysclk > 3000000)
660 if (i == ARRAY_SIZE(clk_sys_rates))
664 new_sysclk = 12288000;
667 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
668 wm9081->mclk_rate, new_sysclk);
670 wm9081->sysclk_rate = new_sysclk;
672 /* Switch SYSCLK over to FLL */
675 wm9081->sysclk_rate = wm9081->mclk_rate;
683 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
685 reg |= WM9081_MCLKDIV2;
687 reg &= ~WM9081_MCLKDIV2;
688 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
690 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
692 reg |= WM9081_CLK_SRC_SEL;
694 reg &= ~WM9081_CLK_SRC_SEL;
695 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
697 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
702 static int clk_sys_event(struct snd_soc_dapm_widget *w,
703 struct snd_kcontrol *kcontrol, int event)
705 struct snd_soc_codec *codec = w->codec;
706 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
708 /* This should be done on init() for bypass paths */
709 switch (wm9081->sysclk_source) {
710 case WM9081_SYSCLK_MCLK:
711 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
713 case WM9081_SYSCLK_FLL_MCLK:
714 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
718 dev_err(codec->dev, "System clock not configured\n");
723 case SND_SOC_DAPM_PRE_PMU:
724 configure_clock(codec);
727 case SND_SOC_DAPM_POST_PMD:
728 /* Disable the FLL if it's running */
729 wm9081_set_fll(codec, 0, 0, 0);
736 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
737 SND_SOC_DAPM_INPUT("IN1"),
738 SND_SOC_DAPM_INPUT("IN2"),
740 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
742 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
743 mixer, ARRAY_SIZE(mixer)),
745 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
747 SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
749 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
751 SND_SOC_DAPM_OUTPUT("LINEOUT"),
752 SND_SOC_DAPM_OUTPUT("SPKN"),
753 SND_SOC_DAPM_OUTPUT("SPKP"),
755 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
757 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
758 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
762 static const struct snd_soc_dapm_route audio_paths[] = {
763 { "DAC", NULL, "CLK_SYS" },
764 { "DAC", NULL, "CLK_DSP" },
766 { "Mixer", "IN1 Switch", "IN1" },
767 { "Mixer", "IN2 Switch", "IN2" },
768 { "Mixer", "Playback Switch", "DAC" },
770 { "LINEOUT PGA", NULL, "Mixer" },
771 { "LINEOUT PGA", NULL, "TOCLK" },
772 { "LINEOUT PGA", NULL, "CLK_SYS" },
774 { "LINEOUT", NULL, "LINEOUT PGA" },
776 { "Speaker PGA", NULL, "Mixer" },
777 { "Speaker PGA", NULL, "TOCLK" },
778 { "Speaker PGA", NULL, "CLK_SYS" },
780 { "SPKN", NULL, "Speaker PGA" },
781 { "SPKP", NULL, "Speaker PGA" },
784 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
785 enum snd_soc_bias_level level)
790 case SND_SOC_BIAS_ON:
793 case SND_SOC_BIAS_PREPARE:
795 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
796 reg &= ~WM9081_VMID_SEL_MASK;
798 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
800 /* Normal bias current */
801 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
802 reg &= ~WM9081_STBY_BIAS_ENA;
803 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
806 case SND_SOC_BIAS_STANDBY:
807 /* Initial cold start */
808 if (codec->bias_level == SND_SOC_BIAS_OFF) {
809 /* Disable LINEOUT discharge */
810 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
811 reg &= ~WM9081_LINEOUT_DISCH;
812 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
814 /* Select startup bias source */
815 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
816 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
817 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
819 /* VMID 2*4k; Soft VMID ramp enable */
820 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
821 reg |= WM9081_VMID_RAMP | 0x6;
822 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
826 /* Normal bias enable & soft start off */
827 reg |= WM9081_BIAS_ENA;
828 reg &= ~WM9081_VMID_RAMP;
829 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
831 /* Standard bias source */
832 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
833 reg &= ~WM9081_BIAS_SRC;
834 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
838 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
839 reg &= ~WM9081_VMID_SEL_MASK;
841 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
843 /* Standby bias current on */
844 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
845 reg |= WM9081_STBY_BIAS_ENA;
846 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
849 case SND_SOC_BIAS_OFF:
850 /* Startup bias source */
851 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
852 reg |= WM9081_BIAS_SRC;
853 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
855 /* Disable VMID and biases with soft ramping */
856 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
857 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
858 reg |= WM9081_VMID_RAMP;
859 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
861 /* Actively discharge LINEOUT */
862 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
863 reg |= WM9081_LINEOUT_DISCH;
864 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
868 codec->bias_level = level;
873 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
876 struct snd_soc_codec *codec = dai->codec;
877 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
878 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
880 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
881 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
883 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
884 case SND_SOC_DAIFMT_CBS_CFS:
887 case SND_SOC_DAIFMT_CBS_CFM:
888 aif2 |= WM9081_LRCLK_DIR;
891 case SND_SOC_DAIFMT_CBM_CFS:
892 aif2 |= WM9081_BCLK_DIR;
895 case SND_SOC_DAIFMT_CBM_CFM:
896 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
903 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
904 case SND_SOC_DAIFMT_DSP_B:
905 aif2 |= WM9081_AIF_LRCLK_INV;
906 case SND_SOC_DAIFMT_DSP_A:
909 case SND_SOC_DAIFMT_I2S:
912 case SND_SOC_DAIFMT_RIGHT_J:
914 case SND_SOC_DAIFMT_LEFT_J:
921 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
922 case SND_SOC_DAIFMT_DSP_A:
923 case SND_SOC_DAIFMT_DSP_B:
924 /* frame inversion not valid for DSP modes */
925 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
926 case SND_SOC_DAIFMT_NB_NF:
928 case SND_SOC_DAIFMT_IB_NF:
929 aif2 |= WM9081_AIF_BCLK_INV;
936 case SND_SOC_DAIFMT_I2S:
937 case SND_SOC_DAIFMT_RIGHT_J:
938 case SND_SOC_DAIFMT_LEFT_J:
939 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
940 case SND_SOC_DAIFMT_NB_NF:
942 case SND_SOC_DAIFMT_IB_IF:
943 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
945 case SND_SOC_DAIFMT_IB_NF:
946 aif2 |= WM9081_AIF_BCLK_INV;
948 case SND_SOC_DAIFMT_NB_IF:
949 aif2 |= WM9081_AIF_LRCLK_INV;
959 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
964 static int wm9081_hw_params(struct snd_pcm_substream *substream,
965 struct snd_pcm_hw_params *params,
966 struct snd_soc_dai *dai)
968 struct snd_soc_codec *codec = dai->codec;
969 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
970 int ret, i, best, best_val, cur_val;
971 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
973 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
974 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
976 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
978 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
979 aif2 &= ~WM9081_AIF_WL_MASK;
981 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
982 aif3 &= ~WM9081_BCLK_DIV_MASK;
984 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
985 aif4 &= ~WM9081_LRCLK_RATE_MASK;
987 wm9081->fs = params_rate(params);
989 if (wm9081->tdm_width) {
990 /* If TDM is set up then that fixes our BCLK. */
991 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
992 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
994 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
996 /* Otherwise work out a BCLK from the sample size */
997 wm9081->bclk = 2 * wm9081->fs;
999 switch (params_format(params)) {
1000 case SNDRV_PCM_FORMAT_S16_LE:
1003 case SNDRV_PCM_FORMAT_S20_3LE:
1007 case SNDRV_PCM_FORMAT_S24_LE:
1011 case SNDRV_PCM_FORMAT_S32_LE:
1020 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1022 ret = configure_clock(codec);
1026 /* Select nearest CLK_SYS_RATE */
1028 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1030 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1031 cur_val = abs((wm9081->sysclk_rate /
1032 clk_sys_rates[i].ratio) - wm9081->fs);
1033 if (cur_val < best_val) {
1038 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1039 clk_sys_rates[best].ratio);
1040 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1041 << WM9081_CLK_SYS_RATE_SHIFT);
1045 best_val = abs(wm9081->fs - sample_rates[0].rate);
1046 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1048 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1049 if (cur_val < best_val) {
1054 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1055 sample_rates[best].rate);
1056 clk_ctrl2 |= (sample_rates[best].sample_rate
1057 << WM9081_SAMPLE_RATE_SHIFT);
1062 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1063 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1065 if (cur_val < 0) /* Table is sorted */
1067 if (cur_val < best_val) {
1072 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1073 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1074 bclk_divs[best].div, wm9081->bclk);
1075 aif3 |= bclk_divs[best].bclk_div;
1077 /* LRCLK is a simple fraction of BCLK */
1078 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1079 aif4 |= wm9081->bclk / wm9081->fs;
1081 /* Apply a ReTune Mobile configuration if it's in use */
1082 if (wm9081->retune) {
1083 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1084 struct wm9081_retune_mobile_setting *s;
1088 best_val = abs(retune->configs[0].rate - wm9081->fs);
1089 for (i = 0; i < retune->num_configs; i++) {
1090 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1091 if (cur_val < best_val) {
1096 s = &retune->configs[best];
1098 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1101 /* If the EQ is enabled then disable it while we write out */
1102 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1103 if (eq1 & WM9081_EQ_ENA)
1104 snd_soc_write(codec, WM9081_EQ_1, 0);
1106 /* Write out the other values */
1107 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1108 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1110 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1111 snd_soc_write(codec, WM9081_EQ_1, eq1);
1114 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1115 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1116 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1117 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1122 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1124 struct snd_soc_codec *codec = codec_dai->codec;
1127 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1130 reg |= WM9081_DAC_MUTE;
1132 reg &= ~WM9081_DAC_MUTE;
1134 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1139 static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1140 int clk_id, unsigned int freq, int dir)
1142 struct snd_soc_codec *codec = codec_dai->codec;
1143 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1146 case WM9081_SYSCLK_MCLK:
1147 case WM9081_SYSCLK_FLL_MCLK:
1148 wm9081->sysclk_source = clk_id;
1149 wm9081->mclk_rate = freq;
1159 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1160 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1162 struct snd_soc_codec *codec = dai->codec;
1163 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1164 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1166 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1168 if (slots < 0 || slots > 4)
1171 wm9081->tdm_width = slot_width;
1176 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1194 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1199 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1201 #define WM9081_FORMATS \
1202 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1203 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1205 static struct snd_soc_dai_ops wm9081_dai_ops = {
1206 .hw_params = wm9081_hw_params,
1207 .set_sysclk = wm9081_set_sysclk,
1208 .set_fmt = wm9081_set_dai_fmt,
1209 .digital_mute = wm9081_digital_mute,
1210 .set_tdm_slot = wm9081_set_tdm_slot,
1213 /* We report two channels because the CODEC processes a stereo signal, even
1214 * though it is only capable of handling a mono output.
1216 static struct snd_soc_dai_driver wm9081_dai = {
1217 .name = "wm9081-hifi",
1219 .stream_name = "HiFi Playback",
1222 .rates = WM9081_RATES,
1223 .formats = WM9081_FORMATS,
1225 .ops = &wm9081_dai_ops,
1228 static int wm9081_probe(struct snd_soc_codec *codec)
1230 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1234 codec->control_data = wm9081->control_data;
1235 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm9081->control_type);
1237 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1241 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
1242 if (reg != 0x9081) {
1243 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1248 ret = wm9081_reset(codec);
1250 dev_err(codec->dev, "Failed to issue reset\n");
1254 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1256 /* Enable zero cross by default */
1257 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1258 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1259 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1260 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1261 reg | WM9081_SPKPGAZC);
1263 snd_soc_add_controls(codec, wm9081_snd_controls,
1264 ARRAY_SIZE(wm9081_snd_controls));
1265 if (!wm9081->retune) {
1267 "No ReTune Mobile data, using normal EQ\n");
1268 snd_soc_add_controls(codec, wm9081_eq_controls,
1269 ARRAY_SIZE(wm9081_eq_controls));
1272 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1273 ARRAY_SIZE(wm9081_dapm_widgets));
1274 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1279 static int wm9081_remove(struct snd_soc_codec *codec)
1281 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1286 static int wm9081_suspend(struct snd_soc_codec *codec, pm_message_t state)
1288 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1293 static int wm9081_resume(struct snd_soc_codec *codec)
1295 u16 *reg_cache = codec->reg_cache;
1298 for (i = 0; i < codec->driver->reg_cache_size; i++) {
1299 if (i == WM9081_SOFTWARE_RESET)
1302 snd_soc_write(codec, i, reg_cache[i]);
1305 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1310 #define wm9081_suspend NULL
1311 #define wm9081_resume NULL
1314 static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
1315 .probe = wm9081_probe,
1316 .remove = wm9081_remove,
1317 .suspend = wm9081_suspend,
1318 .resume = wm9081_resume,
1319 .set_bias_level = wm9081_set_bias_level,
1320 .reg_cache_size = ARRAY_SIZE(wm9081_reg_defaults),
1321 .reg_word_size = sizeof(u16),
1322 .reg_cache_default = wm9081_reg_defaults,
1323 .volatile_register = wm9081_volatile_register,
1326 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1327 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1328 const struct i2c_device_id *id)
1330 struct wm9081_priv *wm9081;
1333 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1337 i2c_set_clientdata(i2c, wm9081);
1338 wm9081->control_data = i2c;
1340 ret = snd_soc_register_codec(&i2c->dev,
1341 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1347 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1349 snd_soc_unregister_codec(&client->dev);
1350 kfree(i2c_get_clientdata(client));
1354 static const struct i2c_device_id wm9081_i2c_id[] = {
1358 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1360 static struct i2c_driver wm9081_i2c_driver = {
1362 .name = "wm9081-codec",
1363 .owner = THIS_MODULE,
1365 .probe = wm9081_i2c_probe,
1366 .remove = __devexit_p(wm9081_i2c_remove),
1367 .id_table = wm9081_i2c_id,
1371 static int __init wm9081_modinit(void)
1374 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1375 ret = i2c_add_driver(&wm9081_i2c_driver);
1377 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1383 module_init(wm9081_modinit);
1385 static void __exit wm9081_exit(void)
1387 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1388 i2c_del_driver(&wm9081_i2c_driver);
1391 module_exit(wm9081_exit);
1394 MODULE_DESCRIPTION("ASoC WM9081 driver");
1395 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1396 MODULE_LICENSE("GPL");