2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/firmware.h>
18 #include <linux/list.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
33 #include <linux/mfd/arizona/registers.h>
38 #define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
40 #define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
42 #define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
44 #define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
46 #define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
49 #define ADSP1_CONTROL_1 0x00
50 #define ADSP1_CONTROL_2 0x02
51 #define ADSP1_CONTROL_3 0x03
52 #define ADSP1_CONTROL_4 0x04
53 #define ADSP1_CONTROL_5 0x06
54 #define ADSP1_CONTROL_6 0x07
55 #define ADSP1_CONTROL_7 0x08
56 #define ADSP1_CONTROL_8 0x09
57 #define ADSP1_CONTROL_9 0x0A
58 #define ADSP1_CONTROL_10 0x0B
59 #define ADSP1_CONTROL_11 0x0C
60 #define ADSP1_CONTROL_12 0x0D
61 #define ADSP1_CONTROL_13 0x0F
62 #define ADSP1_CONTROL_14 0x10
63 #define ADSP1_CONTROL_15 0x11
64 #define ADSP1_CONTROL_16 0x12
65 #define ADSP1_CONTROL_17 0x13
66 #define ADSP1_CONTROL_18 0x14
67 #define ADSP1_CONTROL_19 0x16
68 #define ADSP1_CONTROL_20 0x17
69 #define ADSP1_CONTROL_21 0x18
70 #define ADSP1_CONTROL_22 0x1A
71 #define ADSP1_CONTROL_23 0x1B
72 #define ADSP1_CONTROL_24 0x1C
73 #define ADSP1_CONTROL_25 0x1E
74 #define ADSP1_CONTROL_26 0x20
75 #define ADSP1_CONTROL_27 0x21
76 #define ADSP1_CONTROL_28 0x22
77 #define ADSP1_CONTROL_29 0x23
78 #define ADSP1_CONTROL_30 0x24
79 #define ADSP1_CONTROL_31 0x26
84 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
85 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
86 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
92 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
93 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
94 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
95 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
96 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
97 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
98 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
99 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
100 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
101 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
102 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
103 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
104 #define ADSP1_START 0x0001 /* DSP1_START */
105 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
106 #define ADSP1_START_SHIFT 0 /* DSP1_START */
107 #define ADSP1_START_WIDTH 1 /* DSP1_START */
112 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
113 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
114 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
116 #define ADSP2_CONTROL 0x0
117 #define ADSP2_CLOCKING 0x1
118 #define ADSP2_STATUS1 0x4
119 #define ADSP2_WDMA_CONFIG_1 0x30
120 #define ADSP2_WDMA_CONFIG_2 0x31
121 #define ADSP2_RDMA_CONFIG_1 0x34
127 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
128 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
129 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
130 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
131 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
132 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
133 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
134 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
135 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
136 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
137 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
138 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
139 #define ADSP2_START 0x0001 /* DSP1_START */
140 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
141 #define ADSP2_START_SHIFT 0 /* DSP1_START */
142 #define ADSP2_START_WIDTH 1 /* DSP1_START */
147 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
148 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
149 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
154 #define ADSP2_RAM_RDY 0x0001
155 #define ADSP2_RAM_RDY_MASK 0x0001
156 #define ADSP2_RAM_RDY_SHIFT 0
157 #define ADSP2_RAM_RDY_WIDTH 1
160 struct list_head list;
164 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
165 struct list_head *list)
167 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
172 buf->buf = kmemdup(src, len, GFP_KERNEL | GFP_DMA);
179 list_add_tail(&buf->list, list);
184 static void wm_adsp_buf_free(struct list_head *list)
186 while (!list_empty(list)) {
187 struct wm_adsp_buf *buf = list_first_entry(list,
190 list_del(&buf->list);
196 #define WM_ADSP_NUM_FW 4
198 #define WM_ADSP_FW_MBC_VSS 0
199 #define WM_ADSP_FW_TX 1
200 #define WM_ADSP_FW_TX_SPK 2
201 #define WM_ADSP_FW_RX_ANC 3
203 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
204 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
205 [WM_ADSP_FW_TX] = "Tx",
206 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
207 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
212 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
213 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
214 [WM_ADSP_FW_TX] = { .file = "tx" },
215 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
216 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
219 struct wm_coeff_ctl_ops {
220 int (*xget)(struct snd_kcontrol *kcontrol,
221 struct snd_ctl_elem_value *ucontrol);
222 int (*xput)(struct snd_kcontrol *kcontrol,
223 struct snd_ctl_elem_value *ucontrol);
224 int (*xinfo)(struct snd_kcontrol *kcontrol,
225 struct snd_ctl_elem_info *uinfo);
228 struct wm_coeff_ctl {
230 struct wm_adsp_alg_region region;
231 struct wm_coeff_ctl_ops ops;
232 struct wm_adsp *adsp;
234 unsigned int enabled:1;
235 struct list_head list;
239 struct snd_kcontrol *kcontrol;
242 static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
243 struct snd_ctl_elem_value *ucontrol)
245 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
246 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
247 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
249 ucontrol->value.integer.value[0] = adsp[e->shift_l].fw;
254 static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
255 struct snd_ctl_elem_value *ucontrol)
257 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
258 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
259 struct wm_adsp *adsp = snd_soc_codec_get_drvdata(codec);
261 if (ucontrol->value.integer.value[0] == adsp[e->shift_l].fw)
264 if (ucontrol->value.integer.value[0] >= WM_ADSP_NUM_FW)
267 if (adsp[e->shift_l].running)
270 adsp[e->shift_l].fw = ucontrol->value.integer.value[0];
275 static const struct soc_enum wm_adsp_fw_enum[] = {
276 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
277 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
278 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
279 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
282 const struct snd_kcontrol_new wm_adsp1_fw_controls[] = {
283 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
284 wm_adsp_fw_get, wm_adsp_fw_put),
285 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
286 wm_adsp_fw_get, wm_adsp_fw_put),
287 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
288 wm_adsp_fw_get, wm_adsp_fw_put),
290 EXPORT_SYMBOL_GPL(wm_adsp1_fw_controls);
292 #if IS_ENABLED(CONFIG_SND_SOC_ARIZONA)
293 static const struct soc_enum wm_adsp2_rate_enum[] = {
294 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP1_CONTROL_1,
295 ARIZONA_DSP1_RATE_SHIFT, 0xf,
296 ARIZONA_RATE_ENUM_SIZE,
297 arizona_rate_text, arizona_rate_val),
298 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP2_CONTROL_1,
299 ARIZONA_DSP1_RATE_SHIFT, 0xf,
300 ARIZONA_RATE_ENUM_SIZE,
301 arizona_rate_text, arizona_rate_val),
302 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP3_CONTROL_1,
303 ARIZONA_DSP1_RATE_SHIFT, 0xf,
304 ARIZONA_RATE_ENUM_SIZE,
305 arizona_rate_text, arizona_rate_val),
306 SOC_VALUE_ENUM_SINGLE(ARIZONA_DSP4_CONTROL_1,
307 ARIZONA_DSP1_RATE_SHIFT, 0xf,
308 ARIZONA_RATE_ENUM_SIZE,
309 arizona_rate_text, arizona_rate_val),
312 const struct snd_kcontrol_new wm_adsp2_fw_controls[] = {
313 SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
314 wm_adsp_fw_get, wm_adsp_fw_put),
315 SOC_ENUM("DSP1 Rate", wm_adsp2_rate_enum[0]),
316 SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
317 wm_adsp_fw_get, wm_adsp_fw_put),
318 SOC_ENUM("DSP2 Rate", wm_adsp2_rate_enum[1]),
319 SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
320 wm_adsp_fw_get, wm_adsp_fw_put),
321 SOC_ENUM("DSP3 Rate", wm_adsp2_rate_enum[2]),
322 SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
323 wm_adsp_fw_get, wm_adsp_fw_put),
324 SOC_ENUM("DSP4 Rate", wm_adsp2_rate_enum[3]),
326 EXPORT_SYMBOL_GPL(wm_adsp2_fw_controls);
329 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
334 for (i = 0; i < dsp->num_mems; i++)
335 if (dsp->mem[i].type == type)
341 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *region,
344 switch (region->type) {
346 return region->base + (offset * 3);
348 return region->base + (offset * 2);
350 return region->base + (offset * 2);
352 return region->base + (offset * 2);
354 return region->base + (offset * 2);
356 WARN_ON(NULL != "Unknown memory region type");
361 static int wm_coeff_info(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_info *uinfo)
364 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
366 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
367 uinfo->count = ctl->len;
371 static int wm_coeff_write_control(struct snd_kcontrol *kcontrol,
372 const void *buf, size_t len)
374 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
375 struct wm_adsp_alg_region *region = &ctl->region;
376 const struct wm_adsp_region *mem;
377 struct wm_adsp *adsp = ctl->adsp;
382 mem = wm_adsp_find_region(adsp, region->type);
384 adsp_err(adsp, "No base for region %x\n",
389 reg = ctl->region.base;
390 reg = wm_adsp_region_to_reg(mem, reg);
392 scratch = kmemdup(buf, ctl->len, GFP_KERNEL | GFP_DMA);
396 ret = regmap_raw_write(adsp->regmap, reg, scratch,
399 adsp_err(adsp, "Failed to write %zu bytes to %x\n",
410 static int wm_coeff_put(struct snd_kcontrol *kcontrol,
411 struct snd_ctl_elem_value *ucontrol)
413 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
414 char *p = ucontrol->value.bytes.data;
416 memcpy(ctl->cache, p, ctl->len);
423 return wm_coeff_write_control(kcontrol, p, ctl->len);
426 static int wm_coeff_read_control(struct snd_kcontrol *kcontrol,
427 void *buf, size_t len)
429 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
430 struct wm_adsp_alg_region *region = &ctl->region;
431 const struct wm_adsp_region *mem;
432 struct wm_adsp *adsp = ctl->adsp;
437 mem = wm_adsp_find_region(adsp, region->type);
439 adsp_err(adsp, "No base for region %x\n",
444 reg = ctl->region.base;
445 reg = wm_adsp_region_to_reg(mem, reg);
447 scratch = kmalloc(ctl->len, GFP_KERNEL | GFP_DMA);
451 ret = regmap_raw_read(adsp->regmap, reg, scratch, ctl->len);
453 adsp_err(adsp, "Failed to read %zu bytes from %x\n",
459 memcpy(buf, scratch, ctl->len);
465 static int wm_coeff_get(struct snd_kcontrol *kcontrol,
466 struct snd_ctl_elem_value *ucontrol)
468 struct wm_coeff_ctl *ctl = (struct wm_coeff_ctl *)kcontrol->private_value;
469 char *p = ucontrol->value.bytes.data;
471 memcpy(p, ctl->cache, ctl->len);
475 struct wmfw_ctl_work {
476 struct wm_adsp *adsp;
477 struct wm_coeff_ctl *ctl;
478 struct work_struct work;
481 static int wmfw_add_ctl(struct wm_adsp *adsp, struct wm_coeff_ctl *ctl)
483 struct snd_kcontrol_new *kcontrol;
486 if (!ctl || !ctl->name)
489 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
492 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
494 kcontrol->name = ctl->name;
495 kcontrol->info = wm_coeff_info;
496 kcontrol->get = wm_coeff_get;
497 kcontrol->put = wm_coeff_put;
498 kcontrol->private_value = (unsigned long)ctl;
500 ret = snd_soc_add_card_controls(adsp->card,
507 ctl->kcontrol = snd_soc_card_get_kcontrol(adsp->card,
510 list_add(&ctl->list, &adsp->ctl_list);
518 static int wm_adsp_load(struct wm_adsp *dsp)
521 const struct firmware *firmware;
522 struct regmap *regmap = dsp->regmap;
523 unsigned int pos = 0;
524 const struct wmfw_header *header;
525 const struct wmfw_adsp1_sizes *adsp1_sizes;
526 const struct wmfw_adsp2_sizes *adsp2_sizes;
527 const struct wmfw_footer *footer;
528 const struct wmfw_region *region;
529 const struct wm_adsp_region *mem;
530 const char *region_name;
532 struct wm_adsp_buf *buf;
535 int ret, offset, type, sizes;
537 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
541 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.wmfw", dsp->part, dsp->num,
542 wm_adsp_fw[dsp->fw].file);
543 file[PAGE_SIZE - 1] = '\0';
545 ret = request_firmware(&firmware, file, dsp->dev);
547 adsp_err(dsp, "Failed to request '%s'\n", file);
552 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
553 if (pos >= firmware->size) {
554 adsp_err(dsp, "%s: file too short, %zu bytes\n",
555 file, firmware->size);
559 header = (void*)&firmware->data[0];
561 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
562 adsp_err(dsp, "%s: invalid magic\n", file);
566 if (header->ver != 0) {
567 adsp_err(dsp, "%s: unknown file format %d\n",
572 if (header->core != dsp->type) {
573 adsp_err(dsp, "%s: invalid core %d != %d\n",
574 file, header->core, dsp->type);
580 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
581 adsp1_sizes = (void *)&(header[1]);
582 footer = (void *)&(adsp1_sizes[1]);
583 sizes = sizeof(*adsp1_sizes);
585 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
586 file, le32_to_cpu(adsp1_sizes->dm),
587 le32_to_cpu(adsp1_sizes->pm),
588 le32_to_cpu(adsp1_sizes->zm));
592 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
593 adsp2_sizes = (void *)&(header[1]);
594 footer = (void *)&(adsp2_sizes[1]);
595 sizes = sizeof(*adsp2_sizes);
597 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
598 file, le32_to_cpu(adsp2_sizes->xm),
599 le32_to_cpu(adsp2_sizes->ym),
600 le32_to_cpu(adsp2_sizes->pm),
601 le32_to_cpu(adsp2_sizes->zm));
605 BUG_ON(NULL == "Unknown DSP type");
609 if (le32_to_cpu(header->len) != sizeof(*header) +
610 sizes + sizeof(*footer)) {
611 adsp_err(dsp, "%s: unexpected header length %d\n",
612 file, le32_to_cpu(header->len));
616 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
617 le64_to_cpu(footer->timestamp));
619 while (pos < firmware->size &&
620 pos - firmware->size > sizeof(*region)) {
621 region = (void *)&(firmware->data[pos]);
622 region_name = "Unknown";
625 offset = le32_to_cpu(region->offset) & 0xffffff;
626 type = be32_to_cpu(region->type) & 0xff;
627 mem = wm_adsp_find_region(dsp, type);
631 region_name = "Firmware name";
632 text = kzalloc(le32_to_cpu(region->len) + 1,
636 region_name = "Information";
637 text = kzalloc(le32_to_cpu(region->len) + 1,
641 region_name = "Absolute";
647 reg = wm_adsp_region_to_reg(mem, offset);
652 reg = wm_adsp_region_to_reg(mem, offset);
657 reg = wm_adsp_region_to_reg(mem, offset);
662 reg = wm_adsp_region_to_reg(mem, offset);
667 reg = wm_adsp_region_to_reg(mem, offset);
671 "%s.%d: Unknown region type %x at %d(%x)\n",
672 file, regions, type, pos, pos);
676 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
677 regions, le32_to_cpu(region->len), offset,
681 memcpy(text, region->data, le32_to_cpu(region->len));
682 adsp_info(dsp, "%s: %s\n", file, text);
687 buf = wm_adsp_buf_alloc(region->data,
688 le32_to_cpu(region->len),
691 adsp_err(dsp, "Out of memory\n");
695 ret = regmap_raw_write_async(regmap, reg, buf->buf,
696 le32_to_cpu(region->len));
699 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
701 le32_to_cpu(region->len), offset,
707 pos += le32_to_cpu(region->len) + sizeof(*region);
711 ret = regmap_async_complete(regmap);
713 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
717 if (pos > firmware->size)
718 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
719 file, regions, pos - firmware->size);
722 regmap_async_complete(regmap);
723 wm_adsp_buf_free(&buf_list);
724 release_firmware(firmware);
731 static int wm_coeff_init_control_caches(struct wm_adsp *adsp)
733 struct wm_coeff_ctl *ctl;
736 list_for_each_entry(ctl, &adsp->ctl_list, list) {
737 if (!ctl->enabled || ctl->set)
739 ret = wm_coeff_read_control(ctl->kcontrol,
749 static int wm_coeff_sync_controls(struct wm_adsp *adsp)
751 struct wm_coeff_ctl *ctl;
754 list_for_each_entry(ctl, &adsp->ctl_list, list) {
758 ret = wm_coeff_write_control(ctl->kcontrol,
769 static void wm_adsp_ctl_work(struct work_struct *work)
771 struct wmfw_ctl_work *ctl_work = container_of(work,
772 struct wmfw_ctl_work,
775 wmfw_add_ctl(ctl_work->adsp, ctl_work->ctl);
779 static int wm_adsp_create_control(struct wm_adsp *dsp,
780 const struct wm_adsp_alg_region *region)
783 struct wm_coeff_ctl *ctl;
784 struct wmfw_ctl_work *ctl_work;
789 name = kmalloc(PAGE_SIZE, GFP_KERNEL);
793 switch (region->type) {
814 snprintf(name, PAGE_SIZE, "DSP%d %s %x",
815 dsp->num, region_name, region->alg);
817 list_for_each_entry(ctl, &dsp->ctl_list,
819 if (!strcmp(ctl->name, name)) {
826 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
831 ctl->region = *region;
832 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
839 ctl->ops.xget = wm_coeff_get;
840 ctl->ops.xput = wm_coeff_put;
843 ctl->len = region->len;
844 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
850 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
856 ctl_work->adsp = dsp;
858 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
859 schedule_work(&ctl_work->work);
877 static int wm_adsp_setup_algs(struct wm_adsp *dsp)
879 struct regmap *regmap = dsp->regmap;
880 struct wmfw_adsp1_id_hdr adsp1_id;
881 struct wmfw_adsp2_id_hdr adsp2_id;
882 struct wmfw_adsp1_alg_hdr *adsp1_alg;
883 struct wmfw_adsp2_alg_hdr *adsp2_alg;
885 struct wm_adsp_alg_region *region;
886 const struct wm_adsp_region *mem;
887 unsigned int pos, term;
888 size_t algs, buf_size;
894 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
897 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
911 ret = regmap_raw_read(regmap, mem->base, &adsp1_id,
914 adsp_err(dsp, "Failed to read algorithm info: %d\n",
920 buf_size = sizeof(adsp1_id);
922 algs = be32_to_cpu(adsp1_id.algs);
923 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
924 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
926 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
927 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
928 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
931 region = kzalloc(sizeof(*region), GFP_KERNEL);
934 region->type = WMFW_ADSP1_ZM;
935 region->alg = be32_to_cpu(adsp1_id.fw.id);
936 region->base = be32_to_cpu(adsp1_id.zm);
937 list_add_tail(®ion->list, &dsp->alg_regions);
939 region = kzalloc(sizeof(*region), GFP_KERNEL);
942 region->type = WMFW_ADSP1_DM;
943 region->alg = be32_to_cpu(adsp1_id.fw.id);
944 region->base = be32_to_cpu(adsp1_id.dm);
945 list_add_tail(®ion->list, &dsp->alg_regions);
947 pos = sizeof(adsp1_id) / 2;
948 term = pos + ((sizeof(*adsp1_alg) * algs) / 2);
952 ret = regmap_raw_read(regmap, mem->base, &adsp2_id,
955 adsp_err(dsp, "Failed to read algorithm info: %d\n",
961 buf_size = sizeof(adsp2_id);
963 algs = be32_to_cpu(adsp2_id.algs);
964 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
965 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
967 (be32_to_cpu(adsp2_id.fw.ver) & 0xff0000) >> 16,
968 (be32_to_cpu(adsp2_id.fw.ver) & 0xff00) >> 8,
969 be32_to_cpu(adsp2_id.fw.ver) & 0xff,
972 region = kzalloc(sizeof(*region), GFP_KERNEL);
975 region->type = WMFW_ADSP2_XM;
976 region->alg = be32_to_cpu(adsp2_id.fw.id);
977 region->base = be32_to_cpu(adsp2_id.xm);
978 list_add_tail(®ion->list, &dsp->alg_regions);
980 region = kzalloc(sizeof(*region), GFP_KERNEL);
983 region->type = WMFW_ADSP2_YM;
984 region->alg = be32_to_cpu(adsp2_id.fw.id);
985 region->base = be32_to_cpu(adsp2_id.ym);
986 list_add_tail(®ion->list, &dsp->alg_regions);
988 region = kzalloc(sizeof(*region), GFP_KERNEL);
991 region->type = WMFW_ADSP2_ZM;
992 region->alg = be32_to_cpu(adsp2_id.fw.id);
993 region->base = be32_to_cpu(adsp2_id.zm);
994 list_add_tail(®ion->list, &dsp->alg_regions);
996 pos = sizeof(adsp2_id) / 2;
997 term = pos + ((sizeof(*adsp2_alg) * algs) / 2);
1001 BUG_ON(NULL == "Unknown DSP type");
1006 adsp_err(dsp, "No algorithms\n");
1011 adsp_err(dsp, "Algorithm count %zx excessive\n", algs);
1012 print_hex_dump_bytes(dev_name(dsp->dev), DUMP_PREFIX_OFFSET,
1017 /* Read the terminator first to validate the length */
1018 ret = regmap_raw_read(regmap, mem->base + term, &val, sizeof(val));
1020 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1025 if (be32_to_cpu(val) != 0xbedead)
1026 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
1027 term, be32_to_cpu(val));
1029 alg = kzalloc((term - pos) * 2, GFP_KERNEL | GFP_DMA);
1033 ret = regmap_raw_read(regmap, mem->base + pos, alg, (term - pos) * 2);
1035 adsp_err(dsp, "Failed to read algorithm list: %d\n",
1043 for (i = 0; i < algs; i++) {
1044 switch (dsp->type) {
1046 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
1047 i, be32_to_cpu(adsp1_alg[i].alg.id),
1048 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
1049 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
1050 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
1051 be32_to_cpu(adsp1_alg[i].dm),
1052 be32_to_cpu(adsp1_alg[i].zm));
1054 region = kzalloc(sizeof(*region), GFP_KERNEL);
1057 region->type = WMFW_ADSP1_DM;
1058 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1059 region->base = be32_to_cpu(adsp1_alg[i].dm);
1061 list_add_tail(®ion->list, &dsp->alg_regions);
1063 region->len = be32_to_cpu(adsp1_alg[i + 1].dm);
1064 region->len -= be32_to_cpu(adsp1_alg[i].dm);
1065 wm_adsp_create_control(dsp, region);
1067 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
1068 be32_to_cpu(adsp1_alg[i].alg.id));
1071 region = kzalloc(sizeof(*region), GFP_KERNEL);
1074 region->type = WMFW_ADSP1_ZM;
1075 region->alg = be32_to_cpu(adsp1_alg[i].alg.id);
1076 region->base = be32_to_cpu(adsp1_alg[i].zm);
1078 list_add_tail(®ion->list, &dsp->alg_regions);
1080 region->len = be32_to_cpu(adsp1_alg[i + 1].zm);
1081 region->len -= be32_to_cpu(adsp1_alg[i].zm);
1082 wm_adsp_create_control(dsp, region);
1084 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1085 be32_to_cpu(adsp1_alg[i].alg.id));
1091 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
1092 i, be32_to_cpu(adsp2_alg[i].alg.id),
1093 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
1094 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
1095 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
1096 be32_to_cpu(adsp2_alg[i].xm),
1097 be32_to_cpu(adsp2_alg[i].ym),
1098 be32_to_cpu(adsp2_alg[i].zm));
1100 region = kzalloc(sizeof(*region), GFP_KERNEL);
1103 region->type = WMFW_ADSP2_XM;
1104 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1105 region->base = be32_to_cpu(adsp2_alg[i].xm);
1107 list_add_tail(®ion->list, &dsp->alg_regions);
1109 region->len = be32_to_cpu(adsp2_alg[i + 1].xm);
1110 region->len -= be32_to_cpu(adsp2_alg[i].xm);
1111 wm_adsp_create_control(dsp, region);
1113 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
1114 be32_to_cpu(adsp2_alg[i].alg.id));
1117 region = kzalloc(sizeof(*region), GFP_KERNEL);
1120 region->type = WMFW_ADSP2_YM;
1121 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1122 region->base = be32_to_cpu(adsp2_alg[i].ym);
1124 list_add_tail(®ion->list, &dsp->alg_regions);
1126 region->len = be32_to_cpu(adsp2_alg[i + 1].ym);
1127 region->len -= be32_to_cpu(adsp2_alg[i].ym);
1128 wm_adsp_create_control(dsp, region);
1130 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
1131 be32_to_cpu(adsp2_alg[i].alg.id));
1134 region = kzalloc(sizeof(*region), GFP_KERNEL);
1137 region->type = WMFW_ADSP2_ZM;
1138 region->alg = be32_to_cpu(adsp2_alg[i].alg.id);
1139 region->base = be32_to_cpu(adsp2_alg[i].zm);
1141 list_add_tail(®ion->list, &dsp->alg_regions);
1143 region->len = be32_to_cpu(adsp2_alg[i + 1].zm);
1144 region->len -= be32_to_cpu(adsp2_alg[i].zm);
1145 wm_adsp_create_control(dsp, region);
1147 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
1148 be32_to_cpu(adsp2_alg[i].alg.id));
1159 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
1161 LIST_HEAD(buf_list);
1162 struct regmap *regmap = dsp->regmap;
1163 struct wmfw_coeff_hdr *hdr;
1164 struct wmfw_coeff_item *blk;
1165 const struct firmware *firmware;
1166 const struct wm_adsp_region *mem;
1167 struct wm_adsp_alg_region *alg_region;
1168 const char *region_name;
1169 int ret, pos, blocks, type, offset, reg;
1171 struct wm_adsp_buf *buf;
1174 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1178 snprintf(file, PAGE_SIZE, "%s-dsp%d-%s.bin", dsp->part, dsp->num,
1179 wm_adsp_fw[dsp->fw].file);
1180 file[PAGE_SIZE - 1] = '\0';
1182 ret = request_firmware(&firmware, file, dsp->dev);
1184 adsp_warn(dsp, "Failed to request '%s'\n", file);
1190 if (sizeof(*hdr) >= firmware->size) {
1191 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1192 file, firmware->size);
1196 hdr = (void*)&firmware->data[0];
1197 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
1198 adsp_err(dsp, "%s: invalid magic\n", file);
1202 switch (be32_to_cpu(hdr->rev) & 0xff) {
1206 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
1207 file, be32_to_cpu(hdr->rev) & 0xff);
1212 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
1213 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
1214 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
1215 le32_to_cpu(hdr->ver) & 0xff);
1217 pos = le32_to_cpu(hdr->len);
1220 while (pos < firmware->size &&
1221 pos - firmware->size > sizeof(*blk)) {
1222 blk = (void*)(&firmware->data[pos]);
1224 type = le16_to_cpu(blk->type);
1225 offset = le16_to_cpu(blk->offset);
1227 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
1228 file, blocks, le32_to_cpu(blk->id),
1229 (le32_to_cpu(blk->ver) >> 16) & 0xff,
1230 (le32_to_cpu(blk->ver) >> 8) & 0xff,
1231 le32_to_cpu(blk->ver) & 0xff);
1232 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
1233 file, blocks, le32_to_cpu(blk->len), offset, type);
1236 region_name = "Unknown";
1238 case (WMFW_NAME_TEXT << 8):
1239 case (WMFW_INFO_TEXT << 8):
1241 case (WMFW_ABSOLUTE << 8):
1243 * Old files may use this for global
1246 if (le32_to_cpu(blk->id) == dsp->fw_id &&
1248 region_name = "global coefficients";
1249 mem = wm_adsp_find_region(dsp, type);
1251 adsp_err(dsp, "No ZM\n");
1254 reg = wm_adsp_region_to_reg(mem, 0);
1257 region_name = "register";
1266 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
1267 file, blocks, le32_to_cpu(blk->len),
1268 type, le32_to_cpu(blk->id));
1270 mem = wm_adsp_find_region(dsp, type);
1272 adsp_err(dsp, "No base for region %x\n", type);
1277 list_for_each_entry(alg_region,
1278 &dsp->alg_regions, list) {
1279 if (le32_to_cpu(blk->id) == alg_region->alg &&
1280 type == alg_region->type) {
1281 reg = alg_region->base;
1282 reg = wm_adsp_region_to_reg(mem,
1289 adsp_err(dsp, "No %x for algorithm %x\n",
1290 type, le32_to_cpu(blk->id));
1294 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
1295 file, blocks, type, pos);
1300 buf = wm_adsp_buf_alloc(blk->data,
1301 le32_to_cpu(blk->len),
1304 adsp_err(dsp, "Out of memory\n");
1309 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
1310 file, blocks, le32_to_cpu(blk->len),
1312 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1313 le32_to_cpu(blk->len));
1316 "%s.%d: Failed to write to %x in %s\n",
1317 file, blocks, reg, region_name);
1321 tmp = le32_to_cpu(blk->len) % 4;
1323 pos += le32_to_cpu(blk->len) + (4 - tmp) + sizeof(*blk);
1325 pos += le32_to_cpu(blk->len) + sizeof(*blk);
1330 ret = regmap_async_complete(regmap);
1332 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1334 if (pos > firmware->size)
1335 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1336 file, blocks, pos - firmware->size);
1339 release_firmware(firmware);
1340 wm_adsp_buf_free(&buf_list);
1346 int wm_adsp1_init(struct wm_adsp *adsp)
1348 INIT_LIST_HEAD(&adsp->alg_regions);
1352 EXPORT_SYMBOL_GPL(wm_adsp1_init);
1354 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
1355 struct snd_kcontrol *kcontrol,
1358 struct snd_soc_codec *codec = w->codec;
1359 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1360 struct wm_adsp *dsp = &dsps[w->shift];
1361 struct wm_coeff_ctl *ctl;
1365 dsp->card = codec->card;
1368 case SND_SOC_DAPM_POST_PMU:
1369 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1370 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
1373 * For simplicity set the DSP clock rate to be the
1374 * SYSCLK rate rather than making it configurable.
1376 if(dsp->sysclk_reg) {
1377 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
1379 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1384 val = (val & dsp->sysclk_mask)
1385 >> dsp->sysclk_shift;
1387 ret = regmap_update_bits(dsp->regmap,
1388 dsp->base + ADSP1_CONTROL_31,
1389 ADSP1_CLK_SEL_MASK, val);
1391 adsp_err(dsp, "Failed to set clock rate: %d\n",
1397 ret = wm_adsp_load(dsp);
1401 ret = wm_adsp_setup_algs(dsp);
1405 ret = wm_adsp_load_coeff(dsp);
1409 /* Initialize caches for enabled and unset controls */
1410 ret = wm_coeff_init_control_caches(dsp);
1414 /* Sync set controls */
1415 ret = wm_coeff_sync_controls(dsp);
1419 /* Start the core running */
1420 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1421 ADSP1_CORE_ENA | ADSP1_START,
1422 ADSP1_CORE_ENA | ADSP1_START);
1425 case SND_SOC_DAPM_PRE_PMD:
1427 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1428 ADSP1_CORE_ENA | ADSP1_START, 0);
1430 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
1431 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
1433 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1436 list_for_each_entry(ctl, &dsp->ctl_list, list)
1447 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
1451 EXPORT_SYMBOL_GPL(wm_adsp1_event);
1453 static int wm_adsp2_ena(struct wm_adsp *dsp)
1458 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1459 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
1463 /* Wait for the RAM to start, should be near instantaneous */
1466 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1,
1470 } while (!(val & ADSP2_RAM_RDY) && ++count < 10);
1472 if (!(val & ADSP2_RAM_RDY)) {
1473 adsp_err(dsp, "Failed to start DSP RAM\n");
1477 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
1478 adsp_info(dsp, "RAM ready after %d polls\n", count);
1483 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
1484 struct snd_kcontrol *kcontrol, int event)
1486 struct snd_soc_codec *codec = w->codec;
1487 struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
1488 struct wm_adsp *dsp = &dsps[w->shift];
1489 struct wm_adsp_alg_region *alg_region;
1490 struct wm_coeff_ctl *ctl;
1494 dsp->card = codec->card;
1497 case SND_SOC_DAPM_POST_PMU:
1499 * For simplicity set the DSP clock rate to be the
1500 * SYSCLK rate rather than making it configurable.
1502 ret = regmap_read(dsp->regmap, ARIZONA_SYSTEM_CLOCK_1, &val);
1504 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
1508 val = (val & ARIZONA_SYSCLK_FREQ_MASK)
1509 >> ARIZONA_SYSCLK_FREQ_SHIFT;
1511 ret = regmap_update_bits(dsp->regmap,
1512 dsp->base + ADSP2_CLOCKING,
1513 ADSP2_CLK_SEL_MASK, val);
1515 adsp_err(dsp, "Failed to set clock rate: %d\n",
1521 ret = regmap_read(dsp->regmap,
1522 dsp->base + ADSP2_CLOCKING, &val);
1525 "Failed to read clocking: %d\n", ret);
1529 if ((val & ADSP2_CLK_SEL_MASK) >= 3) {
1530 ret = regulator_enable(dsp->dvfs);
1533 "Failed to enable supply: %d\n",
1538 ret = regulator_set_voltage(dsp->dvfs,
1543 "Failed to raise supply: %d\n",
1550 ret = wm_adsp2_ena(dsp);
1554 ret = wm_adsp_load(dsp);
1558 ret = wm_adsp_setup_algs(dsp);
1562 ret = wm_adsp_load_coeff(dsp);
1566 /* Initialize caches for enabled and unset controls */
1567 ret = wm_coeff_init_control_caches(dsp);
1571 /* Sync set controls */
1572 ret = wm_coeff_sync_controls(dsp);
1576 ret = regmap_update_bits(dsp->regmap,
1577 dsp->base + ADSP2_CONTROL,
1578 ADSP2_CORE_ENA | ADSP2_START,
1579 ADSP2_CORE_ENA | ADSP2_START);
1583 dsp->running = true;
1586 case SND_SOC_DAPM_PRE_PMD:
1587 dsp->running = false;
1589 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1590 ADSP2_SYS_ENA | ADSP2_CORE_ENA |
1593 /* Make sure DMAs are quiesced */
1594 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
1595 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
1596 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
1599 ret = regulator_set_voltage(dsp->dvfs, 1200000,
1603 "Failed to lower supply: %d\n",
1606 ret = regulator_disable(dsp->dvfs);
1609 "Failed to enable supply: %d\n",
1613 list_for_each_entry(ctl, &dsp->ctl_list, list)
1616 while (!list_empty(&dsp->alg_regions)) {
1617 alg_region = list_first_entry(&dsp->alg_regions,
1618 struct wm_adsp_alg_region,
1620 list_del(&alg_region->list);
1631 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
1632 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
1635 EXPORT_SYMBOL_GPL(wm_adsp2_event);
1637 int wm_adsp2_init(struct wm_adsp *adsp, bool dvfs)
1642 * Disable the DSP memory by default when in reset for a small
1645 ret = regmap_update_bits(adsp->regmap, adsp->base + ADSP2_CONTROL,
1648 adsp_err(adsp, "Failed to clear memory retention: %d\n", ret);
1652 INIT_LIST_HEAD(&adsp->alg_regions);
1653 INIT_LIST_HEAD(&adsp->ctl_list);
1656 adsp->dvfs = devm_regulator_get(adsp->dev, "DCVDD");
1657 if (IS_ERR(adsp->dvfs)) {
1658 ret = PTR_ERR(adsp->dvfs);
1659 dev_err(adsp->dev, "Failed to get DCVDD: %d\n", ret);
1663 ret = regulator_enable(adsp->dvfs);
1665 dev_err(adsp->dev, "Failed to enable DCVDD: %d\n",
1670 ret = regulator_set_voltage(adsp->dvfs, 1200000, 1800000);
1672 dev_err(adsp->dev, "Failed to initialise DVFS: %d\n",
1677 ret = regulator_disable(adsp->dvfs);
1679 dev_err(adsp->dev, "Failed to disable DCVDD: %d\n",
1687 EXPORT_SYMBOL_GPL(wm_adsp2_init);