2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/platform_data/davinci_asp.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
26 #include <sound/dmaengine_pcm.h>
29 #include "davinci-i2s.h"
33 * NOTE: terminology here is confusing.
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
51 #define DAVINCI_MCBSP_DRR_REG 0x00
52 #define DAVINCI_MCBSP_DXR_REG 0x04
53 #define DAVINCI_MCBSP_SPCR_REG 0x08
54 #define DAVINCI_MCBSP_RCR_REG 0x0c
55 #define DAVINCI_MCBSP_XCR_REG 0x10
56 #define DAVINCI_MCBSP_SRGR_REG 0x14
57 #define DAVINCI_MCBSP_PCR_REG 0x24
59 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
67 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
70 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
71 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
72 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
75 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
80 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
83 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
86 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
88 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
92 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
93 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
107 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
113 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
119 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
124 struct davinci_mcbsp_dev {
126 struct snd_dmaengine_dai_dma_data dma_data[2];
135 * Combining both channels into 1 element will at least double the
136 * amount of time between servicing the dma channel, increase
137 * effiency, and reduce the chance of overrun/underrun. But,
138 * it will result in the left & right channels being swapped.
140 * If relabeling the left and right channels is not possible,
141 * you may want to let the codec know to swap them back.
143 * It may allow x10 the amount of time to service dma requests,
144 * if the codec is master and is using an unnecessarily fast bit clock
145 * (ie. tlvaic23b), independent of the sample rate. So, having an
146 * entire frame at once means it can be serviced at the sample rate
147 * instead of the bit clock rate.
149 * In the now unlikely case that an underrun still
150 * occurs, both the left and right samples will be repeated
151 * so that no pops are heard, and the left and right channels
152 * won't end up being swapped because of the underrun.
154 unsigned enable_channel_combine:1;
159 bool i2s_accurate_sck;
162 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
165 __raw_writel(val, dev->base + reg);
168 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
170 return __raw_readl(dev->base + reg);
173 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
175 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
176 /* The clock needs to toggle to complete reset.
177 * So, fake it by toggling the clk polarity.
179 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
180 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
183 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
184 struct snd_pcm_substream *substream)
186 struct snd_soc_pcm_runtime *rtd = substream->private_data;
187 struct snd_soc_platform *platform = rtd->platform;
188 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
190 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
191 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
193 /* start off disabled */
194 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
196 toggle_clock(dev, playback);
198 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
199 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
200 /* Start the sample generator */
201 spcr |= DAVINCI_MCBSP_SPCR_GRST;
202 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
206 /* Stop the DMA to avoid data loss */
207 /* while the transmitter is out of reset to handle XSYNCERR */
208 if (platform->driver->ops->trigger) {
209 int ret = platform->driver->ops->trigger(substream,
210 SNDRV_PCM_TRIGGER_STOP);
212 printk(KERN_DEBUG "Playback DMA stop failed\n");
215 /* Enable the transmitter */
216 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
217 spcr |= DAVINCI_MCBSP_SPCR_XRST;
218 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
220 /* wait for any unexpected frame sync error to occur */
223 /* Disable the transmitter to clear any outstanding XSYNCERR */
224 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
225 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
226 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
227 toggle_clock(dev, playback);
229 /* Restart the DMA */
230 if (platform->driver->ops->trigger) {
231 int ret = platform->driver->ops->trigger(substream,
232 SNDRV_PCM_TRIGGER_START);
234 printk(KERN_DEBUG "Playback DMA start failed\n");
238 /* Enable transmitter or receiver */
239 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
242 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
243 /* Start frame sync */
244 spcr |= DAVINCI_MCBSP_SPCR_FRST;
246 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
249 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
253 /* Reset transmitter/receiver and sample rate/frame sync generators */
254 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
255 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
256 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
257 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
258 toggle_clock(dev, playback);
261 #define DEFAULT_BITPERSAMPLE 16
263 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
266 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
270 /* Attention srgr is updated by hw_params! */
271 srgr = DAVINCI_MCBSP_SRGR_FSGM |
272 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
273 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
276 /* set master/slave audio interface */
277 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
278 case SND_SOC_DAIFMT_CBS_CFS:
280 pcr = DAVINCI_MCBSP_PCR_FSXM |
281 DAVINCI_MCBSP_PCR_FSRM |
282 DAVINCI_MCBSP_PCR_CLKXM |
283 DAVINCI_MCBSP_PCR_CLKRM;
285 case SND_SOC_DAIFMT_CBM_CFS:
286 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
288 * Selection of the clock input pin that is the
289 * input for the Sample Rate Generator.
290 * McBSP FSR and FSX are driven by the Sample Rate
293 switch (dev->clk_input_pin) {
295 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
296 DAVINCI_MCBSP_PCR_CLKRM;
299 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
302 dev_err(dev->dev, "bad clk_input_pin\n");
307 case SND_SOC_DAIFMT_CBM_CFM:
308 /* codec is master */
312 printk(KERN_ERR "%s:bad master\n", __func__);
316 /* interface format */
317 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
318 case SND_SOC_DAIFMT_I2S:
319 /* Davinci doesn't support TRUE I2S, but some codecs will have
320 * the left and right channels contiguous. This allows
321 * dsp_a mode to be used with an inverted normal frame clk.
322 * If your codec is master and does not have contiguous
323 * channels, then you will have sound on only one channel.
324 * Try using a different mode, or codec as slave.
326 * The TLV320AIC33 is an example of a codec where this works.
327 * It has a variable bit clock frequency allowing it to have
328 * valid data on every bit clock.
330 * The TLV320AIC23 is an example of a codec where this does not
331 * work. It has a fixed bit clock frequency with progressively
332 * more empty bit clock slots between channels as the sample
336 case SND_SOC_DAIFMT_DSP_A:
337 dev->mode = MOD_DSP_A;
339 case SND_SOC_DAIFMT_DSP_B:
340 dev->mode = MOD_DSP_B;
343 printk(KERN_ERR "%s:bad format\n", __func__);
347 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
348 case SND_SOC_DAIFMT_NB_NF:
349 /* CLKRP Receive clock polarity,
350 * 1 - sampled on rising edge of CLKR
351 * valid on rising edge
352 * CLKXP Transmit clock polarity,
353 * 1 - clocked on falling edge of CLKX
354 * valid on rising edge
355 * FSRP Receive frame sync pol, 0 - active high
356 * FSXP Transmit frame sync pol, 0 - active high
358 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
360 case SND_SOC_DAIFMT_IB_IF:
361 /* CLKRP Receive clock polarity,
362 * 0 - sampled on falling edge of CLKR
363 * valid on falling edge
364 * CLKXP Transmit clock polarity,
365 * 0 - clocked on rising edge of CLKX
366 * valid on falling edge
367 * FSRP Receive frame sync pol, 1 - active low
368 * FSXP Transmit frame sync pol, 1 - active low
370 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
372 case SND_SOC_DAIFMT_NB_IF:
373 /* CLKRP Receive clock polarity,
374 * 1 - sampled on rising edge of CLKR
375 * valid on rising edge
376 * CLKXP Transmit clock polarity,
377 * 1 - clocked on falling edge of CLKX
378 * valid on rising edge
379 * FSRP Receive frame sync pol, 1 - active low
380 * FSXP Transmit frame sync pol, 1 - active low
382 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
383 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
385 case SND_SOC_DAIFMT_IB_NF:
386 /* CLKRP Receive clock polarity,
387 * 0 - sampled on falling edge of CLKR
388 * valid on falling edge
389 * CLKXP Transmit clock polarity,
390 * 0 - clocked on rising edge of CLKX
391 * valid on falling edge
392 * FSRP Receive frame sync pol, 0 - active high
393 * FSXP Transmit frame sync pol, 0 - active high
400 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
401 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
403 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
407 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
410 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
412 if (div_id != DAVINCI_MCBSP_CLKGDV)
419 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
420 struct snd_pcm_hw_params *params,
421 struct snd_soc_dai *dai)
423 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
424 struct snd_interval *i = NULL;
425 int mcbsp_word_length, master;
426 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
428 snd_pcm_format_t fmt;
429 unsigned element_cnt = 1;
431 /* general line settings */
432 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
433 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
434 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
435 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
437 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
438 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
441 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
442 fmt = params_format(params);
443 mcbsp_word_length = asp_word_length[fmt];
446 case SND_SOC_DAIFMT_CBS_CFS:
447 freq = clk_get_rate(dev->clk);
448 srgr = DAVINCI_MCBSP_SRGR_FSGM |
449 DAVINCI_MCBSP_SRGR_CLKSM;
450 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
452 if (dev->i2s_accurate_sck) {
455 framesize = (freq / (--clk_div)) /
458 } while (((framesize < 33) || (framesize > 4095)) &&
461 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
463 /* symmetric waveforms */
464 clk_div = freq / (mcbsp_word_length * 16) /
465 params->rate_num * params->rate_den;
466 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
472 case SND_SOC_DAIFMT_CBM_CFS:
473 srgr = DAVINCI_MCBSP_SRGR_FSGM;
474 clk_div = dev->clk_div - 1;
475 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
476 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
480 case SND_SOC_DAIFMT_CBM_CFM:
481 /* Clock and frame sync given from external sources */
482 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
483 srgr = DAVINCI_MCBSP_SRGR_FSGM;
484 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
485 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
486 __func__, __LINE__, snd_interval_value(i) - 1);
488 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
489 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
494 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
496 rcr = DAVINCI_MCBSP_RCR_RFIG;
497 xcr = DAVINCI_MCBSP_XCR_XFIG;
498 if (dev->mode == MOD_DSP_B) {
499 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
500 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
502 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
503 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
505 /* Determine xfer data type */
506 fmt = params_format(params);
507 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
508 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
512 if (params_channels(params) == 2) {
514 if (double_fmt[fmt] && dev->enable_channel_combine) {
516 fmt = double_fmt[fmt];
519 case SND_SOC_DAIFMT_CBS_CFS:
520 case SND_SOC_DAIFMT_CBS_CFM:
521 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
522 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
523 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
524 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
526 case SND_SOC_DAIFMT_CBM_CFM:
527 case SND_SOC_DAIFMT_CBM_CFS:
528 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
529 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
535 mcbsp_word_length = asp_word_length[fmt];
538 case SND_SOC_DAIFMT_CBS_CFS:
539 case SND_SOC_DAIFMT_CBS_CFM:
540 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
541 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
543 case SND_SOC_DAIFMT_CBM_CFM:
544 case SND_SOC_DAIFMT_CBM_CFS:
545 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
546 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
552 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
553 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
554 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
555 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
557 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
558 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
560 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
562 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
563 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
564 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
568 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
569 struct snd_soc_dai *dai)
571 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
572 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
573 davinci_mcbsp_stop(dev, playback);
577 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
578 struct snd_soc_dai *dai)
580 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
582 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
585 case SNDRV_PCM_TRIGGER_START:
586 case SNDRV_PCM_TRIGGER_RESUME:
587 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
588 davinci_mcbsp_start(dev, substream);
590 case SNDRV_PCM_TRIGGER_STOP:
591 case SNDRV_PCM_TRIGGER_SUSPEND:
592 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
593 davinci_mcbsp_stop(dev, playback);
601 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
602 struct snd_soc_dai *dai)
604 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
605 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
606 davinci_mcbsp_stop(dev, playback);
609 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
611 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
612 .shutdown = davinci_i2s_shutdown,
613 .prepare = davinci_i2s_prepare,
614 .trigger = davinci_i2s_trigger,
615 .hw_params = davinci_i2s_hw_params,
616 .set_fmt = davinci_i2s_set_dai_fmt,
617 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
621 static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
623 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
625 dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
626 dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
631 static struct snd_soc_dai_driver davinci_i2s_dai = {
632 .probe = davinci_i2s_dai_probe,
636 .rates = DAVINCI_I2S_RATES,
637 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
641 .rates = DAVINCI_I2S_RATES,
642 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
643 .ops = &davinci_i2s_dai_ops,
647 static const struct snd_soc_component_driver davinci_i2s_component = {
648 .name = "davinci-i2s",
651 static int davinci_i2s_probe(struct platform_device *pdev)
653 struct davinci_mcbsp_dev *dev;
654 struct resource *mem, *ioarea, *res;
658 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
660 dev_err(&pdev->dev, "no mem resource?\n");
664 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
668 dev_err(&pdev->dev, "McBSP region already claimed\n");
672 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
677 dev->clk = clk_get(&pdev->dev, NULL);
678 if (IS_ERR(dev->clk))
680 clk_enable(dev->clk);
682 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
684 dev_err(&pdev->dev, "ioremap failed\n");
686 goto err_release_clk;
689 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
690 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
692 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
693 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
695 /* first TX, then RX */
696 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
698 dev_err(&pdev->dev, "no DMA resource\n");
700 goto err_release_clk;
702 dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
704 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data = dma;
706 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
708 dev_err(&pdev->dev, "no DMA resource\n");
710 goto err_release_clk;
712 dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
714 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].filter_data = dma;
716 dev->dev = &pdev->dev;
717 dev_set_drvdata(&pdev->dev, dev);
719 ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
720 &davinci_i2s_dai, 1);
722 goto err_release_clk;
724 ret = edma_pcm_platform_register(&pdev->dev);
726 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
727 goto err_unregister_component;
732 err_unregister_component:
733 snd_soc_unregister_component(&pdev->dev);
735 clk_disable(dev->clk);
740 static int davinci_i2s_remove(struct platform_device *pdev)
742 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
744 snd_soc_unregister_component(&pdev->dev);
746 clk_disable(dev->clk);
753 static struct platform_driver davinci_mcbsp_driver = {
754 .probe = davinci_i2s_probe,
755 .remove = davinci_i2s_remove,
757 .name = "davinci-mcbsp",
761 module_platform_driver(davinci_mcbsp_driver);
763 MODULE_AUTHOR("Vladimir Barinov");
764 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
765 MODULE_LICENSE("GPL");