2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
18 #include <linux/clk.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/initval.h>
24 #include <sound/soc.h>
28 #include "davinci-pcm.h"
29 #include "davinci-i2s.h"
33 * NOTE: terminology here is confusing.
35 * - This driver supports the "Audio Serial Port" (ASP),
36 * found on dm6446, dm355, and other DaVinci chips.
38 * - But it labels it a "Multi-channel Buffered Serial Port"
39 * (McBSP) as on older chips like the dm642 ... which was
40 * backward-compatible, possibly explaining that confusion.
42 * - OMAP chips have a controller called McBSP, which is
43 * incompatible with the DaVinci flavor of McBSP.
45 * - Newer DaVinci chips have a controller called McASP,
46 * incompatible with ASP and with either McBSP.
48 * In short: this uses ASP to implement I2S, not McBSP.
49 * And it won't be the only DaVinci implemention of I2S.
51 #define DAVINCI_MCBSP_DRR_REG 0x00
52 #define DAVINCI_MCBSP_DXR_REG 0x04
53 #define DAVINCI_MCBSP_SPCR_REG 0x08
54 #define DAVINCI_MCBSP_RCR_REG 0x0c
55 #define DAVINCI_MCBSP_XCR_REG 0x10
56 #define DAVINCI_MCBSP_SRGR_REG 0x14
57 #define DAVINCI_MCBSP_PCR_REG 0x24
59 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
60 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
61 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
62 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
63 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
64 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
65 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
67 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
68 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
69 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
70 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
71 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
72 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
73 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
75 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
76 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
77 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
78 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
79 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
80 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
81 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
83 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
84 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
85 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
86 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
88 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
89 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
90 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
91 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
92 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
93 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
94 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
95 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
96 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
99 DAVINCI_MCBSP_WORD_8 = 0,
100 DAVINCI_MCBSP_WORD_12,
101 DAVINCI_MCBSP_WORD_16,
102 DAVINCI_MCBSP_WORD_20,
103 DAVINCI_MCBSP_WORD_24,
104 DAVINCI_MCBSP_WORD_32,
107 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
108 [SNDRV_PCM_FORMAT_S8] = 1,
109 [SNDRV_PCM_FORMAT_S16_LE] = 2,
110 [SNDRV_PCM_FORMAT_S32_LE] = 4,
113 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
119 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
124 struct davinci_mcbsp_dev {
125 struct davinci_pcm_dma_params dma_params[2];
133 * Combining both channels into 1 element will at least double the
134 * amount of time between servicing the dma channel, increase
135 * effiency, and reduce the chance of overrun/underrun. But,
136 * it will result in the left & right channels being swapped.
138 * If relabeling the left and right channels is not possible,
139 * you may want to let the codec know to swap them back.
141 * It may allow x10 the amount of time to service dma requests,
142 * if the codec is master and is using an unnecessarily fast bit clock
143 * (ie. tlvaic23b), independent of the sample rate. So, having an
144 * entire frame at once means it can be serviced at the sample rate
145 * instead of the bit clock rate.
147 * In the now unlikely case that an underrun still
148 * occurs, both the left and right samples will be repeated
149 * so that no pops are heard, and the left and right channels
150 * won't end up being swapped because of the underrun.
152 unsigned enable_channel_combine:1;
158 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
161 __raw_writel(val, dev->base + reg);
164 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
166 return __raw_readl(dev->base + reg);
169 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
171 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
172 /* The clock needs to toggle to complete reset.
173 * So, fake it by toggling the clk polarity.
175 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
176 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
179 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
180 struct snd_pcm_substream *substream)
182 struct snd_soc_pcm_runtime *rtd = substream->private_data;
183 struct snd_soc_device *socdev = rtd->socdev;
184 struct snd_soc_platform *platform = socdev->card->platform;
185 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
187 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
188 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
190 /* start off disabled */
191 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
193 toggle_clock(dev, playback);
195 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
196 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
197 /* Start the sample generator */
198 spcr |= DAVINCI_MCBSP_SPCR_GRST;
199 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
203 /* Stop the DMA to avoid data loss */
204 /* while the transmitter is out of reset to handle XSYNCERR */
205 if (platform->pcm_ops->trigger) {
206 int ret = platform->pcm_ops->trigger(substream,
207 SNDRV_PCM_TRIGGER_STOP);
209 printk(KERN_DEBUG "Playback DMA stop failed\n");
212 /* Enable the transmitter */
213 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
214 spcr |= DAVINCI_MCBSP_SPCR_XRST;
215 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
217 /* wait for any unexpected frame sync error to occur */
220 /* Disable the transmitter to clear any outstanding XSYNCERR */
221 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
222 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
223 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
224 toggle_clock(dev, playback);
226 /* Restart the DMA */
227 if (platform->pcm_ops->trigger) {
228 int ret = platform->pcm_ops->trigger(substream,
229 SNDRV_PCM_TRIGGER_START);
231 printk(KERN_DEBUG "Playback DMA start failed\n");
235 /* Enable transmitter or receiver */
236 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
239 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
240 /* Start frame sync */
241 spcr |= DAVINCI_MCBSP_SPCR_FRST;
243 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
246 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
250 /* Reset transmitter/receiver and sample rate/frame sync generators */
251 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
252 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
253 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
254 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
255 toggle_clock(dev, playback);
258 #define DEFAULT_BITPERSAMPLE 16
260 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
263 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
266 /* Attention srgr is updated by hw_params! */
267 srgr = DAVINCI_MCBSP_SRGR_FSGM |
268 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
269 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
272 /* set master/slave audio interface */
273 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
274 case SND_SOC_DAIFMT_CBS_CFS:
276 pcr = DAVINCI_MCBSP_PCR_FSXM |
277 DAVINCI_MCBSP_PCR_FSRM |
278 DAVINCI_MCBSP_PCR_CLKXM |
279 DAVINCI_MCBSP_PCR_CLKRM;
281 case SND_SOC_DAIFMT_CBM_CFS:
282 /* McBSP CLKR pin is the input for the Sample Rate Generator.
283 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
284 pcr = DAVINCI_MCBSP_PCR_SCLKME |
285 DAVINCI_MCBSP_PCR_FSXM |
286 DAVINCI_MCBSP_PCR_FSRM;
288 case SND_SOC_DAIFMT_CBM_CFM:
289 /* codec is master */
293 printk(KERN_ERR "%s:bad master\n", __func__);
297 /* interface format */
298 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
299 case SND_SOC_DAIFMT_I2S:
300 /* Davinci doesn't support TRUE I2S, but some codecs will have
301 * the left and right channels contiguous. This allows
302 * dsp_a mode to be used with an inverted normal frame clk.
303 * If your codec is master and does not have contiguous
304 * channels, then you will have sound on only one channel.
305 * Try using a different mode, or codec as slave.
307 * The TLV320AIC33 is an example of a codec where this works.
308 * It has a variable bit clock frequency allowing it to have
309 * valid data on every bit clock.
311 * The TLV320AIC23 is an example of a codec where this does not
312 * work. It has a fixed bit clock frequency with progressively
313 * more empty bit clock slots between channels as the sample
316 fmt ^= SND_SOC_DAIFMT_NB_IF;
317 case SND_SOC_DAIFMT_DSP_A:
318 dev->mode = MOD_DSP_A;
320 case SND_SOC_DAIFMT_DSP_B:
321 dev->mode = MOD_DSP_B;
324 printk(KERN_ERR "%s:bad format\n", __func__);
328 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
329 case SND_SOC_DAIFMT_NB_NF:
330 /* CLKRP Receive clock polarity,
331 * 1 - sampled on rising edge of CLKR
332 * valid on rising edge
333 * CLKXP Transmit clock polarity,
334 * 1 - clocked on falling edge of CLKX
335 * valid on rising edge
336 * FSRP Receive frame sync pol, 0 - active high
337 * FSXP Transmit frame sync pol, 0 - active high
339 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
341 case SND_SOC_DAIFMT_IB_IF:
342 /* CLKRP Receive clock polarity,
343 * 0 - sampled on falling edge of CLKR
344 * valid on falling edge
345 * CLKXP Transmit clock polarity,
346 * 0 - clocked on rising edge of CLKX
347 * valid on falling edge
348 * FSRP Receive frame sync pol, 1 - active low
349 * FSXP Transmit frame sync pol, 1 - active low
351 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
353 case SND_SOC_DAIFMT_NB_IF:
354 /* CLKRP Receive clock polarity,
355 * 1 - sampled on rising edge of CLKR
356 * valid on rising edge
357 * CLKXP Transmit clock polarity,
358 * 1 - clocked on falling edge of CLKX
359 * valid on rising edge
360 * FSRP Receive frame sync pol, 1 - active low
361 * FSXP Transmit frame sync pol, 1 - active low
363 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
364 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
366 case SND_SOC_DAIFMT_IB_NF:
367 /* CLKRP Receive clock polarity,
368 * 0 - sampled on falling edge of CLKR
369 * valid on falling edge
370 * CLKXP Transmit clock polarity,
371 * 0 - clocked on rising edge of CLKX
372 * valid on falling edge
373 * FSRP Receive frame sync pol, 0 - active high
374 * FSXP Transmit frame sync pol, 0 - active high
380 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
382 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
386 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
389 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
391 if (div_id != DAVINCI_MCBSP_CLKGDV)
398 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
399 struct snd_pcm_hw_params *params,
400 struct snd_soc_dai *dai)
402 struct davinci_mcbsp_dev *dev = dai->private_data;
403 struct davinci_pcm_dma_params *dma_params =
404 &dev->dma_params[substream->stream];
405 struct snd_interval *i = NULL;
406 int mcbsp_word_length, master;
407 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
409 snd_pcm_format_t fmt;
410 unsigned element_cnt = 1;
412 /* general line settings */
413 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
414 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
415 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
416 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
418 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
419 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
422 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
423 fmt = params_format(params);
424 mcbsp_word_length = asp_word_length[fmt];
427 case SND_SOC_DAIFMT_CBS_CFS:
428 freq = clk_get_rate(dev->clk);
429 srgr = DAVINCI_MCBSP_SRGR_FSGM |
430 DAVINCI_MCBSP_SRGR_CLKSM;
431 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
433 /* symmetric waveforms */
434 clk_div = freq / (mcbsp_word_length * 16) /
435 params->rate_num * params->rate_den;
436 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
441 case SND_SOC_DAIFMT_CBM_CFS:
442 srgr = DAVINCI_MCBSP_SRGR_FSGM;
443 clk_div = dev->clk_div - 1;
444 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
445 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
449 case SND_SOC_DAIFMT_CBM_CFM:
450 /* Clock and frame sync given from external sources */
451 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
452 srgr = DAVINCI_MCBSP_SRGR_FSGM;
453 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
454 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
455 __func__, __LINE__, snd_interval_value(i) - 1);
457 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
458 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
463 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
465 rcr = DAVINCI_MCBSP_RCR_RFIG;
466 xcr = DAVINCI_MCBSP_XCR_XFIG;
467 if (dev->mode == MOD_DSP_B) {
468 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
469 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
471 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
472 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
474 /* Determine xfer data type */
475 fmt = params_format(params);
476 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
477 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
481 if (params_channels(params) == 2) {
483 if (double_fmt[fmt] && dev->enable_channel_combine) {
485 fmt = double_fmt[fmt];
488 case SND_SOC_DAIFMT_CBS_CFS:
489 case SND_SOC_DAIFMT_CBS_CFM:
490 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
491 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
492 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
493 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
495 case SND_SOC_DAIFMT_CBM_CFM:
496 case SND_SOC_DAIFMT_CBM_CFS:
497 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
498 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
504 dma_params->acnt = dma_params->data_type = data_type[fmt];
505 dma_params->fifo_level = 0;
506 mcbsp_word_length = asp_word_length[fmt];
509 case SND_SOC_DAIFMT_CBS_CFS:
510 case SND_SOC_DAIFMT_CBS_CFM:
511 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
512 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
514 case SND_SOC_DAIFMT_CBM_CFM:
515 case SND_SOC_DAIFMT_CBM_CFS:
516 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
517 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
523 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
524 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
525 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
526 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
528 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
529 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
531 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
533 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
534 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
535 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
539 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
540 struct snd_soc_dai *dai)
542 struct davinci_mcbsp_dev *dev = dai->private_data;
543 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
544 davinci_mcbsp_stop(dev, playback);
545 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
546 /* codec is master */
547 davinci_mcbsp_start(dev, substream);
552 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
553 struct snd_soc_dai *dai)
555 struct davinci_mcbsp_dev *dev = dai->private_data;
557 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
558 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
559 return 0; /* return if codec is master */
562 case SNDRV_PCM_TRIGGER_START:
563 case SNDRV_PCM_TRIGGER_RESUME:
564 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
565 davinci_mcbsp_start(dev, substream);
567 case SNDRV_PCM_TRIGGER_STOP:
568 case SNDRV_PCM_TRIGGER_SUSPEND:
569 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
570 davinci_mcbsp_stop(dev, playback);
578 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
579 struct snd_soc_dai *dai)
581 struct davinci_mcbsp_dev *dev = dai->private_data;
582 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
583 davinci_mcbsp_stop(dev, playback);
586 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
588 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
589 .shutdown = davinci_i2s_shutdown,
590 .prepare = davinci_i2s_prepare,
591 .trigger = davinci_i2s_trigger,
592 .hw_params = davinci_i2s_hw_params,
593 .set_fmt = davinci_i2s_set_dai_fmt,
594 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
598 struct snd_soc_dai davinci_i2s_dai = {
599 .name = "davinci-i2s",
604 .rates = DAVINCI_I2S_RATES,
605 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
609 .rates = DAVINCI_I2S_RATES,
610 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
611 .ops = &davinci_i2s_dai_ops,
614 EXPORT_SYMBOL_GPL(davinci_i2s_dai);
616 static int davinci_i2s_probe(struct platform_device *pdev)
618 struct snd_platform_data *pdata = pdev->dev.platform_data;
619 struct davinci_mcbsp_dev *dev;
620 struct resource *mem, *ioarea, *res;
623 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
625 dev_err(&pdev->dev, "no mem resource?\n");
629 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
632 dev_err(&pdev->dev, "McBSP region already claimed\n");
636 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
639 goto err_release_region;
642 dev->enable_channel_combine = pdata->enable_channel_combine;
643 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
644 pdata->sram_size_playback;
645 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
646 pdata->sram_size_capture;
648 dev->clk = clk_get(&pdev->dev, NULL);
649 if (IS_ERR(dev->clk)) {
653 clk_enable(dev->clk);
655 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
657 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
658 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
660 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
661 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
663 /* first TX, then RX */
664 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
666 dev_err(&pdev->dev, "no DMA resource\n");
670 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
672 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
674 dev_err(&pdev->dev, "no DMA resource\n");
678 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
680 davinci_i2s_dai.private_data = dev;
681 davinci_i2s_dai.capture.dma_data = dev->dma_params;
682 davinci_i2s_dai.playback.dma_data = dev->dma_params;
683 ret = snd_soc_register_dai(&davinci_i2s_dai);
692 release_mem_region(mem->start, (mem->end - mem->start) + 1);
697 static int davinci_i2s_remove(struct platform_device *pdev)
699 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
700 struct resource *mem;
702 snd_soc_unregister_dai(&davinci_i2s_dai);
703 clk_disable(dev->clk);
707 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 release_mem_region(mem->start, (mem->end - mem->start) + 1);
713 static struct platform_driver davinci_mcbsp_driver = {
714 .probe = davinci_i2s_probe,
715 .remove = davinci_i2s_remove,
717 .name = "davinci-asp",
718 .owner = THIS_MODULE,
722 static int __init davinci_i2s_init(void)
724 return platform_driver_register(&davinci_mcbsp_driver);
726 module_init(davinci_i2s_init);
728 static void __exit davinci_i2s_exit(void)
730 platform_driver_unregister(&davinci_mcbsp_driver);
732 module_exit(davinci_i2s_exit);
734 MODULE_AUTHOR("Vladimir Barinov");
735 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
736 MODULE_LICENSE("GPL");