2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
23 #include <linux/clk.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/initval.h>
29 #include <sound/soc.h>
31 #include "davinci-pcm.h"
32 #include "davinci-mcasp.h"
35 * McASP register definitions
37 #define DAVINCI_MCASP_PID_REG 0x00
38 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
40 #define DAVINCI_MCASP_PFUNC_REG 0x10
41 #define DAVINCI_MCASP_PDIR_REG 0x14
42 #define DAVINCI_MCASP_PDOUT_REG 0x18
43 #define DAVINCI_MCASP_PDSET_REG 0x1c
45 #define DAVINCI_MCASP_PDCLR_REG 0x20
47 #define DAVINCI_MCASP_TLGC_REG 0x30
48 #define DAVINCI_MCASP_TLMR_REG 0x34
50 #define DAVINCI_MCASP_GBLCTL_REG 0x44
51 #define DAVINCI_MCASP_AMUTE_REG 0x48
52 #define DAVINCI_MCASP_LBCTL_REG 0x4c
54 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
56 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
57 #define DAVINCI_MCASP_RXMASK_REG 0x64
58 #define DAVINCI_MCASP_RXFMT_REG 0x68
59 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
61 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
62 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
63 #define DAVINCI_MCASP_RXTDM_REG 0x78
64 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
66 #define DAVINCI_MCASP_RXSTAT_REG 0x80
67 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
68 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
69 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
71 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
72 #define DAVINCI_MCASP_TXMASK_REG 0xa4
73 #define DAVINCI_MCASP_TXFMT_REG 0xa8
74 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
76 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
77 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
78 #define DAVINCI_MCASP_TXTDM_REG 0xb8
79 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
81 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
82 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
83 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
84 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
86 /* Left(even TDM Slot) Channel Status Register File */
87 #define DAVINCI_MCASP_DITCSRA_REG 0x100
88 /* Right(odd TDM slot) Channel Status Register File */
89 #define DAVINCI_MCASP_DITCSRB_REG 0x118
90 /* Left(even TDM slot) User Data Register File */
91 #define DAVINCI_MCASP_DITUDRA_REG 0x130
92 /* Right(odd TDM Slot) User Data Register File */
93 #define DAVINCI_MCASP_DITUDRB_REG 0x148
95 /* Serializer n Control Register */
96 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
97 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
100 /* Transmit Buffer for Serializer n */
101 #define DAVINCI_MCASP_TXBUF_REG 0x200
102 /* Receive Buffer for Serializer n */
103 #define DAVINCI_MCASP_RXBUF_REG 0x280
105 /* McASP FIFO Registers */
106 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
107 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
108 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
109 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
112 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
115 #define MCASP_FREE BIT(0)
116 #define MCASP_SOFT BIT(1)
119 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
121 #define AXR(n) (1<<n)
122 #define PFUNC_AMUTE BIT(25)
123 #define ACLKX BIT(26)
124 #define AHCLKX BIT(27)
126 #define ACLKR BIT(29)
127 #define AHCLKR BIT(30)
131 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
133 #define AXR(n) (1<<n)
134 #define PDIR_AMUTE BIT(25)
135 #define ACLKX BIT(26)
136 #define AHCLKX BIT(27)
138 #define ACLKR BIT(29)
139 #define AHCLKR BIT(30)
143 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
145 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
150 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
152 #define TXROT(val) (val)
154 #define TXSSZ(val) (val<<4)
155 #define TXPBIT(val) (val<<8)
156 #define TXPAD(val) (val<<13)
157 #define TXORD BIT(15)
158 #define FSXDLY(val) (val<<16)
161 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
163 #define RXROT(val) (val)
165 #define RXSSZ(val) (val<<4)
166 #define RXPBIT(val) (val<<8)
167 #define RXPAD(val) (val<<13)
168 #define RXORD BIT(15)
169 #define FSRDLY(val) (val<<16)
172 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
174 #define FSXPOL BIT(0)
176 #define FSXDUR BIT(4)
177 #define FSXMOD(val) (val<<7)
180 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
182 #define FSRPOL BIT(0)
184 #define FSRDUR BIT(4)
185 #define FSRMOD(val) (val<<7)
188 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
190 #define ACLKXDIV(val) (val)
191 #define ACLKXE BIT(5)
192 #define TX_ASYNC BIT(6)
193 #define ACLKXPOL BIT(7)
196 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
198 #define ACLKRDIV(val) (val)
199 #define ACLKRE BIT(5)
200 #define RX_ASYNC BIT(6)
201 #define ACLKRPOL BIT(7)
204 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
207 #define AHCLKXDIV(val) (val)
208 #define AHCLKXPOL BIT(14)
209 #define AHCLKXE BIT(15)
212 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
215 #define AHCLKRDIV(val) (val)
216 #define AHCLKRPOL BIT(14)
217 #define AHCLKRE BIT(15)
220 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
222 #define MODE(val) (val)
223 #define DISMOD (val)(val<<2)
224 #define TXSTATE BIT(4)
225 #define RXSTATE BIT(5)
228 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
232 #define LBGENMODE(val) (val<<2)
235 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
237 #define TXTDMS(n) (1<<n)
240 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
242 #define RXTDMS(n) (1<<n)
245 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
247 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
248 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
249 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
250 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
251 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
252 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
253 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
254 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
255 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
256 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
259 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
261 #define MUTENA(val) (val)
262 #define MUTEINPOL BIT(2)
263 #define MUTEINENA BIT(3)
264 #define MUTEIN BIT(4)
267 #define MUTEFSR BIT(7)
268 #define MUTEFSX BIT(8)
269 #define MUTEBADCLKR BIT(9)
270 #define MUTEBADCLKX BIT(10)
271 #define MUTERXDMAERR BIT(11)
272 #define MUTETXDMAERR BIT(12)
275 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
277 #define RXDATADMADIS BIT(0)
280 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
282 #define TXDATADMADIS BIT(0)
285 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
287 #define FIFO_ENABLE BIT(16)
288 #define NUMEVT_MASK (0xFF << 8)
289 #define NUMDMA_MASK (0xFF)
291 #define DAVINCI_MCASP_NUM_SERIALIZER 16
293 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
295 __raw_writel(__raw_readl(reg) | val, reg);
298 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
300 __raw_writel((__raw_readl(reg) & ~(val)), reg);
303 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
305 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
308 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
310 __raw_writel(val, reg);
313 static inline u32 mcasp_get_reg(void __iomem *reg)
315 return (unsigned int)__raw_readl(reg);
318 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
322 mcasp_set_bits(regs, val);
324 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
325 /* loop count is to avoid the lock-up */
326 for (i = 0; i < 1000; i++) {
327 if ((mcasp_get_reg(regs) & val) == val)
331 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
332 printk(KERN_ERR "GBLCTL write error\n");
335 static void mcasp_start_rx(struct davinci_audio_dev *dev)
337 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
340 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
342 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
344 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
350 static void mcasp_start_tx(struct davinci_audio_dev *dev)
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
362 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
363 for (i = 0; i < dev->num_serializer; i++) {
364 if (dev->serial_dir[i] == TX_MODE) {
370 /* wait for TX ready */
372 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
373 TXSTATE) && (cnt < 100000))
376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
379 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
381 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
382 if (dev->txnumevt) /* enable FIFO */
383 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
387 if (dev->rxnumevt) /* enable FIFO */
388 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
394 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
396 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
397 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
400 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
402 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
406 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
408 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
409 if (dev->txnumevt) /* disable FIFO */
410 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
414 if (dev->rxnumevt) /* disable FIFO */
415 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
421 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
424 struct davinci_audio_dev *dev = cpu_dai->private_data;
425 void __iomem *base = dev->base;
427 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
428 case SND_SOC_DAIFMT_CBS_CFS:
429 /* codec is clock and frame slave */
430 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
431 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
433 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
434 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
436 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
438 case SND_SOC_DAIFMT_CBM_CFS:
439 /* codec is clock master and frame slave */
440 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
441 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
443 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
444 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
446 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
448 case SND_SOC_DAIFMT_CBM_CFM:
449 /* codec is clock and frame master */
450 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
451 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
453 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
454 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
456 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
463 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
464 case SND_SOC_DAIFMT_IB_NF:
465 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
466 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
468 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
469 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
472 case SND_SOC_DAIFMT_NB_IF:
473 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
474 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
476 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
477 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
480 case SND_SOC_DAIFMT_IB_IF:
481 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
482 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
484 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
485 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
488 case SND_SOC_DAIFMT_NB_NF:
489 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
490 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
492 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
493 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
503 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
509 switch (channel_size) {
510 case DAVINCI_AUDIO_WORD_8:
516 case DAVINCI_AUDIO_WORD_12:
522 case DAVINCI_AUDIO_WORD_16:
528 case DAVINCI_AUDIO_WORD_20:
534 case DAVINCI_AUDIO_WORD_24:
540 case DAVINCI_AUDIO_WORD_28:
546 case DAVINCI_AUDIO_WORD_32:
556 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
557 RXSSZ(fmt), RXSSZ(0x0F));
558 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
559 TXSSZ(fmt), TXSSZ(0x0F));
560 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
562 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
564 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
565 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
570 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
576 /* Default configuration */
577 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
579 /* All PINS as McASP */
580 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
582 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
583 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
584 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
587 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
588 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
592 for (i = 0; i < dev->num_serializer; i++) {
593 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
595 if (dev->serial_dir[i] == TX_MODE) {
596 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
599 } else if (dev->serial_dir[i] == RX_MODE) {
600 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
606 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
607 if (dev->txnumevt * tx_ser > 64)
610 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
612 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
613 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
614 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
617 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
618 if (dev->rxnumevt * rx_ser > 64)
621 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
623 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
624 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
625 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
629 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
634 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
635 for (i = 0; i < active_slots; i++)
638 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
640 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
641 /* bit stream is MSB first with no delay */
643 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
645 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
646 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
648 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
649 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
650 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
652 printk(KERN_ERR "playback tdm slot %d not supported\n",
655 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
657 /* bit stream is MSB first with no delay */
659 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
660 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
662 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
664 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
665 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
666 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
668 printk(KERN_ERR "capture tdm slot %d not supported\n",
671 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
676 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
678 /* Set the PDIR for Serialiser as output */
679 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
681 /* TXMASK for 24 bits */
682 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
684 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
686 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
687 TXROT(6) | TXSSZ(15));
689 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
690 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
691 AFSXE | FSXMOD(0x180));
693 /* Set the TX tdm : for all the slots */
694 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
696 /* Set the TX clock controls : div = 1 and internal */
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
700 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
702 /* Only 44100 and 48000 are valid, both have the same setting */
703 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
706 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
709 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
710 struct snd_pcm_hw_params *params,
711 struct snd_soc_dai *cpu_dai)
713 struct davinci_audio_dev *dev = cpu_dai->private_data;
714 struct davinci_pcm_dma_params *dma_params =
715 &dev->dma_params[substream->stream];
719 davinci_hw_common_param(dev, substream->stream);
720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
721 fifo_level = dev->txnumevt;
723 fifo_level = dev->rxnumevt;
725 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
726 davinci_hw_dit_param(dev);
728 davinci_hw_param(dev, substream->stream);
730 switch (params_format(params)) {
731 case SNDRV_PCM_FORMAT_S8:
732 dma_params->data_type = 1;
733 word_length = DAVINCI_AUDIO_WORD_8;
736 case SNDRV_PCM_FORMAT_S16_LE:
737 dma_params->data_type = 2;
738 word_length = DAVINCI_AUDIO_WORD_16;
741 case SNDRV_PCM_FORMAT_S32_LE:
742 dma_params->data_type = 4;
743 word_length = DAVINCI_AUDIO_WORD_32;
747 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
751 if (dev->version == MCASP_VERSION_2 && !fifo_level)
752 dma_params->acnt = 4;
754 dma_params->acnt = dma_params->data_type;
756 dma_params->fifo_level = fifo_level;
757 davinci_config_channel_size(dev, word_length);
762 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
763 int cmd, struct snd_soc_dai *cpu_dai)
765 struct snd_soc_pcm_runtime *rtd = substream->private_data;
766 struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
770 case SNDRV_PCM_TRIGGER_START:
771 case SNDRV_PCM_TRIGGER_RESUME:
772 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
773 davinci_mcasp_start(dev, substream->stream);
776 case SNDRV_PCM_TRIGGER_STOP:
777 case SNDRV_PCM_TRIGGER_SUSPEND:
778 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
779 davinci_mcasp_stop(dev, substream->stream);
789 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
790 .trigger = davinci_mcasp_trigger,
791 .hw_params = davinci_mcasp_hw_params,
792 .set_fmt = davinci_mcasp_set_dai_fmt,
796 struct snd_soc_dai davinci_mcasp_dai[] = {
798 .name = "davinci-i2s",
803 .rates = DAVINCI_MCASP_RATES,
804 .formats = SNDRV_PCM_FMTBIT_S8 |
805 SNDRV_PCM_FMTBIT_S16_LE |
806 SNDRV_PCM_FMTBIT_S32_LE,
811 .rates = DAVINCI_MCASP_RATES,
812 .formats = SNDRV_PCM_FMTBIT_S8 |
813 SNDRV_PCM_FMTBIT_S16_LE |
814 SNDRV_PCM_FMTBIT_S32_LE,
816 .ops = &davinci_mcasp_dai_ops,
820 .name = "davinci-dit",
825 .rates = DAVINCI_MCASP_RATES,
826 .formats = SNDRV_PCM_FMTBIT_S16_LE,
828 .ops = &davinci_mcasp_dai_ops,
832 EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
834 static int davinci_mcasp_probe(struct platform_device *pdev)
836 struct davinci_pcm_dma_params *dma_data;
837 struct resource *mem, *ioarea, *res;
838 struct snd_platform_data *pdata;
839 struct davinci_audio_dev *dev;
842 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
846 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 dev_err(&pdev->dev, "no mem resource?\n");
850 goto err_release_data;
853 ioarea = request_mem_region(mem->start,
854 (mem->end - mem->start) + 1, pdev->name);
856 dev_err(&pdev->dev, "Audio region already claimed\n");
858 goto err_release_data;
861 pdata = pdev->dev.platform_data;
862 dev->clk = clk_get(&pdev->dev, NULL);
863 if (IS_ERR(dev->clk)) {
865 goto err_release_region;
868 clk_enable(dev->clk);
870 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
871 dev->op_mode = pdata->op_mode;
872 dev->tdm_slots = pdata->tdm_slots;
873 dev->num_serializer = pdata->num_serializer;
874 dev->serial_dir = pdata->serial_dir;
875 dev->codec_fmt = pdata->codec_fmt;
876 dev->version = pdata->version;
877 dev->txnumevt = pdata->txnumevt;
878 dev->rxnumevt = pdata->rxnumevt;
880 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
881 dma_data->eventq_no = pdata->eventq_no;
882 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
885 /* first TX, then RX */
886 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
888 dev_err(&pdev->dev, "no DMA resource\n");
889 goto err_release_region;
892 dma_data->channel = res->start;
894 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
895 dma_data->eventq_no = pdata->eventq_no;
896 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
899 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
901 dev_err(&pdev->dev, "no DMA resource\n");
902 goto err_release_region;
905 dma_data->channel = res->start;
906 davinci_mcasp_dai[pdata->op_mode].private_data = dev;
907 davinci_mcasp_dai[pdata->op_mode].dma_data = dev->dma_params;
908 davinci_mcasp_dai[pdata->op_mode].dev = &pdev->dev;
909 ret = snd_soc_register_dai(&davinci_mcasp_dai[pdata->op_mode]);
912 goto err_release_region;
916 release_mem_region(mem->start, (mem->end - mem->start) + 1);
923 static int davinci_mcasp_remove(struct platform_device *pdev)
925 struct snd_platform_data *pdata = pdev->dev.platform_data;
926 struct davinci_audio_dev *dev;
927 struct resource *mem;
929 snd_soc_unregister_dai(&davinci_mcasp_dai[pdata->op_mode]);
930 dev = davinci_mcasp_dai[pdata->op_mode].private_data;
931 clk_disable(dev->clk);
935 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
936 release_mem_region(mem->start, (mem->end - mem->start) + 1);
943 static struct platform_driver davinci_mcasp_driver = {
944 .probe = davinci_mcasp_probe,
945 .remove = davinci_mcasp_remove,
947 .name = "davinci-mcasp",
948 .owner = THIS_MODULE,
952 static int __init davinci_mcasp_init(void)
954 return platform_driver_register(&davinci_mcasp_driver);
956 module_init(davinci_mcasp_init);
958 static void __exit davinci_mcasp_exit(void)
960 platform_driver_unregister(&davinci_mcasp_driver);
962 module_exit(davinci_mcasp_exit);
964 MODULE_AUTHOR("Steve Chen");
965 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
966 MODULE_LICENSE("GPL");