2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/of_platform.h>
27 #include <linux/of_device.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/initval.h>
33 #include <sound/soc.h>
35 #include "davinci-pcm.h"
36 #include "davinci-mcasp.h"
39 * McASP register definitions
41 #define DAVINCI_MCASP_PID_REG 0x00
42 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
44 #define DAVINCI_MCASP_PFUNC_REG 0x10
45 #define DAVINCI_MCASP_PDIR_REG 0x14
46 #define DAVINCI_MCASP_PDOUT_REG 0x18
47 #define DAVINCI_MCASP_PDSET_REG 0x1c
49 #define DAVINCI_MCASP_PDCLR_REG 0x20
51 #define DAVINCI_MCASP_TLGC_REG 0x30
52 #define DAVINCI_MCASP_TLMR_REG 0x34
54 #define DAVINCI_MCASP_GBLCTL_REG 0x44
55 #define DAVINCI_MCASP_AMUTE_REG 0x48
56 #define DAVINCI_MCASP_LBCTL_REG 0x4c
58 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
60 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
61 #define DAVINCI_MCASP_RXMASK_REG 0x64
62 #define DAVINCI_MCASP_RXFMT_REG 0x68
63 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
65 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67 #define DAVINCI_MCASP_RXTDM_REG 0x78
68 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
70 #define DAVINCI_MCASP_RXSTAT_REG 0x80
71 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
75 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76 #define DAVINCI_MCASP_TXMASK_REG 0xa4
77 #define DAVINCI_MCASP_TXFMT_REG 0xa8
78 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
80 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82 #define DAVINCI_MCASP_TXTDM_REG 0xb8
83 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
85 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
86 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
90 /* Left(even TDM Slot) Channel Status Register File */
91 #define DAVINCI_MCASP_DITCSRA_REG 0x100
92 /* Right(odd TDM slot) Channel Status Register File */
93 #define DAVINCI_MCASP_DITCSRB_REG 0x118
94 /* Left(even TDM slot) User Data Register File */
95 #define DAVINCI_MCASP_DITUDRA_REG 0x130
96 /* Right(odd TDM Slot) User Data Register File */
97 #define DAVINCI_MCASP_DITUDRB_REG 0x148
99 /* Serializer n Control Register */
100 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
104 /* Transmit Buffer for Serializer n */
105 #define DAVINCI_MCASP_TXBUF_REG 0x200
106 /* Receive Buffer for Serializer n */
107 #define DAVINCI_MCASP_RXBUF_REG 0x280
109 /* McASP FIFO Registers */
110 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
111 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
112 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
113 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
114 #define MCASP_VER3_WFIFOCTL (0x1000)
115 #define MCASP_VER3_WFIFOSTS (0x1004)
116 #define MCASP_VER3_RFIFOCTL (0x1008)
117 #define MCASP_VER3_RFIFOSTS (0x100C)
120 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
123 #define MCASP_FREE BIT(0)
124 #define MCASP_SOFT BIT(1)
127 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
129 #define AXR(n) (1<<n)
130 #define PFUNC_AMUTE BIT(25)
131 #define ACLKX BIT(26)
132 #define AHCLKX BIT(27)
134 #define ACLKR BIT(29)
135 #define AHCLKR BIT(30)
139 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
141 #define AXR(n) (1<<n)
142 #define PDIR_AMUTE BIT(25)
143 #define ACLKX BIT(26)
144 #define AHCLKX BIT(27)
146 #define ACLKR BIT(29)
147 #define AHCLKR BIT(30)
151 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
153 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
158 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
160 #define TXROT(val) (val)
162 #define TXSSZ(val) (val<<4)
163 #define TXPBIT(val) (val<<8)
164 #define TXPAD(val) (val<<13)
165 #define TXORD BIT(15)
166 #define FSXDLY(val) (val<<16)
169 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
171 #define RXROT(val) (val)
173 #define RXSSZ(val) (val<<4)
174 #define RXPBIT(val) (val<<8)
175 #define RXPAD(val) (val<<13)
176 #define RXORD BIT(15)
177 #define FSRDLY(val) (val<<16)
180 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
182 #define FSXPOL BIT(0)
184 #define FSXDUR BIT(4)
185 #define FSXMOD(val) (val<<7)
188 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
190 #define FSRPOL BIT(0)
192 #define FSRDUR BIT(4)
193 #define FSRMOD(val) (val<<7)
196 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
198 #define ACLKXDIV(val) (val)
199 #define ACLKXE BIT(5)
200 #define TX_ASYNC BIT(6)
201 #define ACLKXPOL BIT(7)
204 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
206 #define ACLKRDIV(val) (val)
207 #define ACLKRE BIT(5)
208 #define RX_ASYNC BIT(6)
209 #define ACLKRPOL BIT(7)
212 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
215 #define AHCLKXDIV(val) (val)
216 #define AHCLKXPOL BIT(14)
217 #define AHCLKXE BIT(15)
220 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
223 #define AHCLKRDIV(val) (val)
224 #define AHCLKRPOL BIT(14)
225 #define AHCLKRE BIT(15)
228 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
230 #define MODE(val) (val)
231 #define DISMOD (val)(val<<2)
232 #define TXSTATE BIT(4)
233 #define RXSTATE BIT(5)
236 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
240 #define LBGENMODE(val) (val<<2)
243 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
245 #define TXTDMS(n) (1<<n)
248 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
250 #define RXTDMS(n) (1<<n)
253 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
255 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
256 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
257 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
258 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
259 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
260 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
261 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
262 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
263 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
264 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
267 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
269 #define MUTENA(val) (val)
270 #define MUTEINPOL BIT(2)
271 #define MUTEINENA BIT(3)
272 #define MUTEIN BIT(4)
275 #define MUTEFSR BIT(7)
276 #define MUTEFSX BIT(8)
277 #define MUTEBADCLKR BIT(9)
278 #define MUTEBADCLKX BIT(10)
279 #define MUTERXDMAERR BIT(11)
280 #define MUTETXDMAERR BIT(12)
283 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
285 #define RXDATADMADIS BIT(0)
288 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
290 #define TXDATADMADIS BIT(0)
293 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
295 #define FIFO_ENABLE BIT(16)
296 #define NUMEVT_MASK (0xFF << 8)
297 #define NUMDMA_MASK (0xFF)
299 #define DAVINCI_MCASP_NUM_SERIALIZER 16
301 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
303 __raw_writel(__raw_readl(reg) | val, reg);
306 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
308 __raw_writel((__raw_readl(reg) & ~(val)), reg);
311 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
313 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
316 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
318 __raw_writel(val, reg);
321 static inline u32 mcasp_get_reg(void __iomem *reg)
323 return (unsigned int)__raw_readl(reg);
326 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
330 mcasp_set_bits(regs, val);
332 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
333 /* loop count is to avoid the lock-up */
334 for (i = 0; i < 1000; i++) {
335 if ((mcasp_get_reg(regs) & val) == val)
339 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
340 printk(KERN_ERR "GBLCTL write error\n");
343 static void mcasp_start_rx(struct davinci_audio_dev *dev)
345 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
348 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
352 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
354 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
358 static void mcasp_start_tx(struct davinci_audio_dev *dev)
363 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
364 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
366 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
368 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
369 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
370 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
371 for (i = 0; i < dev->num_serializer; i++) {
372 if (dev->serial_dir[i] == TX_MODE) {
378 /* wait for TX ready */
380 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
381 TXSTATE) && (cnt < 100000))
384 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
387 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
389 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
390 if (dev->txnumevt) { /* enable FIFO */
391 switch (dev->version) {
392 case MCASP_VERSION_3:
393 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
395 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
399 mcasp_clr_bits(dev->base +
400 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
401 mcasp_set_bits(dev->base +
402 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
407 if (dev->rxnumevt) { /* enable FIFO */
408 switch (dev->version) {
409 case MCASP_VERSION_3:
410 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
412 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
416 mcasp_clr_bits(dev->base +
417 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
418 mcasp_set_bits(dev->base +
419 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
426 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
428 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
429 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
432 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
434 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
435 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
438 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
440 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
441 if (dev->txnumevt) { /* disable FIFO */
442 switch (dev->version) {
443 case MCASP_VERSION_3:
444 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
448 mcasp_clr_bits(dev->base +
449 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
454 if (dev->rxnumevt) { /* disable FIFO */
455 switch (dev->version) {
456 case MCASP_VERSION_3:
457 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
462 mcasp_clr_bits(dev->base +
463 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
470 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
473 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
474 void __iomem *base = dev->base;
476 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
477 case SND_SOC_DAIFMT_CBS_CFS:
478 /* codec is clock and frame slave */
479 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
480 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
482 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
483 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
485 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
486 ACLKX | AHCLKX | AFSX);
488 case SND_SOC_DAIFMT_CBM_CFS:
489 /* codec is clock master and frame slave */
490 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
491 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
493 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
494 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
496 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
498 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
501 case SND_SOC_DAIFMT_CBM_CFM:
502 /* codec is clock and frame master */
503 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
504 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
506 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
507 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
509 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
510 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
517 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
518 case SND_SOC_DAIFMT_IB_NF:
519 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
520 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
522 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
523 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
526 case SND_SOC_DAIFMT_NB_IF:
527 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
528 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
530 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
531 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
534 case SND_SOC_DAIFMT_IB_IF:
535 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
536 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
538 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
539 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
542 case SND_SOC_DAIFMT_NB_NF:
543 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
544 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
546 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
547 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
557 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
563 switch (channel_size) {
564 case DAVINCI_AUDIO_WORD_8:
570 case DAVINCI_AUDIO_WORD_12:
576 case DAVINCI_AUDIO_WORD_16:
582 case DAVINCI_AUDIO_WORD_20:
588 case DAVINCI_AUDIO_WORD_24:
594 case DAVINCI_AUDIO_WORD_28:
600 case DAVINCI_AUDIO_WORD_32:
610 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
611 RXSSZ(fmt), RXSSZ(0x0F));
612 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
613 TXSSZ(fmt), TXSSZ(0x0F));
614 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
616 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
618 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
619 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
624 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
630 /* Default configuration */
631 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
633 /* All PINS as McASP */
634 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
636 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
637 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
638 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
641 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
646 for (i = 0; i < dev->num_serializer; i++) {
647 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
649 if (dev->serial_dir[i] == TX_MODE) {
650 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
653 } else if (dev->serial_dir[i] == RX_MODE) {
654 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
660 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
661 if (dev->txnumevt * tx_ser > 64)
664 switch (dev->version) {
665 case MCASP_VERSION_3:
666 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
668 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
669 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
672 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
673 tx_ser, NUMDMA_MASK);
674 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
675 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
679 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
680 if (dev->rxnumevt * rx_ser > 64)
682 switch (dev->version) {
683 case MCASP_VERSION_3:
684 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
686 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
687 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
690 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
691 rx_ser, NUMDMA_MASK);
692 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
693 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
698 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
703 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
704 for (i = 0; i < active_slots; i++)
707 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
709 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
710 /* bit stream is MSB first with no delay */
712 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
714 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
715 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
717 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
718 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
719 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
721 printk(KERN_ERR "playback tdm slot %d not supported\n",
724 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
726 /* bit stream is MSB first with no delay */
728 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
729 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
731 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
733 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
734 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
735 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
737 printk(KERN_ERR "capture tdm slot %d not supported\n",
740 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
745 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
747 /* Set the PDIR for Serialiser as output */
748 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
750 /* TXMASK for 24 bits */
751 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
753 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
755 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
756 TXROT(6) | TXSSZ(15));
758 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
759 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
760 AFSXE | FSXMOD(0x180));
762 /* Set the TX tdm : for all the slots */
763 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
765 /* Set the TX clock controls : div = 1 and internal */
766 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
769 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
771 /* Only 44100 and 48000 are valid, both have the same setting */
772 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
775 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
778 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
779 struct snd_pcm_hw_params *params,
780 struct snd_soc_dai *cpu_dai)
782 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
783 struct davinci_pcm_dma_params *dma_params =
784 &dev->dma_params[substream->stream];
788 davinci_hw_common_param(dev, substream->stream);
789 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
790 fifo_level = dev->txnumevt;
792 fifo_level = dev->rxnumevt;
794 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
795 davinci_hw_dit_param(dev);
797 davinci_hw_param(dev, substream->stream);
799 switch (params_format(params)) {
800 case SNDRV_PCM_FORMAT_U8:
801 case SNDRV_PCM_FORMAT_S8:
802 dma_params->data_type = 1;
803 word_length = DAVINCI_AUDIO_WORD_8;
806 case SNDRV_PCM_FORMAT_U16_LE:
807 case SNDRV_PCM_FORMAT_S16_LE:
808 dma_params->data_type = 2;
809 word_length = DAVINCI_AUDIO_WORD_16;
812 case SNDRV_PCM_FORMAT_U32_LE:
813 case SNDRV_PCM_FORMAT_S32_LE:
814 dma_params->data_type = 4;
815 word_length = DAVINCI_AUDIO_WORD_32;
819 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
823 if (dev->version == MCASP_VERSION_2 && !fifo_level)
824 dma_params->acnt = 4;
826 dma_params->acnt = dma_params->data_type;
828 dma_params->fifo_level = fifo_level;
829 davinci_config_channel_size(dev, word_length);
834 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
835 int cmd, struct snd_soc_dai *cpu_dai)
837 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
841 case SNDRV_PCM_TRIGGER_RESUME:
842 case SNDRV_PCM_TRIGGER_START:
843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
844 ret = pm_runtime_get_sync(dev->dev);
845 if (IS_ERR_VALUE(ret))
846 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
847 davinci_mcasp_start(dev, substream->stream);
850 case SNDRV_PCM_TRIGGER_SUSPEND:
851 davinci_mcasp_stop(dev, substream->stream);
852 ret = pm_runtime_put_sync(dev->dev);
853 if (IS_ERR_VALUE(ret))
854 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
857 case SNDRV_PCM_TRIGGER_STOP:
858 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
859 davinci_mcasp_stop(dev, substream->stream);
869 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
870 struct snd_soc_dai *dai)
872 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
874 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
878 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
879 .startup = davinci_mcasp_startup,
880 .trigger = davinci_mcasp_trigger,
881 .hw_params = davinci_mcasp_hw_params,
882 .set_fmt = davinci_mcasp_set_dai_fmt,
886 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
887 SNDRV_PCM_FMTBIT_U8 | \
888 SNDRV_PCM_FMTBIT_S16_LE | \
889 SNDRV_PCM_FMTBIT_U16_LE | \
890 SNDRV_PCM_FMTBIT_S32_LE | \
891 SNDRV_PCM_FMTBIT_U32_LE)
893 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
895 .name = "davinci-mcasp.0",
899 .rates = DAVINCI_MCASP_RATES,
900 .formats = DAVINCI_MCASP_PCM_FMTS,
905 .rates = DAVINCI_MCASP_RATES,
906 .formats = DAVINCI_MCASP_PCM_FMTS,
908 .ops = &davinci_mcasp_dai_ops,
916 .rates = DAVINCI_MCASP_RATES,
917 .formats = DAVINCI_MCASP_PCM_FMTS,
919 .ops = &davinci_mcasp_dai_ops,
924 static const struct of_device_id mcasp_dt_ids[] = {
926 .compatible = "ti,dm646x-mcasp-audio",
927 .data = (void *)MCASP_VERSION_1,
930 .compatible = "ti,da830-mcasp-audio",
931 .data = (void *)MCASP_VERSION_2,
934 .compatible = "ti,omap2-mcasp-audio",
935 .data = (void *)MCASP_VERSION_3,
939 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
941 static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
942 struct platform_device *pdev)
944 struct device_node *np = pdev->dev.of_node;
945 struct snd_platform_data *pdata = NULL;
946 const struct of_device_id *match =
947 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
949 const u32 *of_serial_dir32;
954 if (pdev->dev.platform_data) {
955 pdata = pdev->dev.platform_data;
958 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
964 /* control shouldn't reach here. something is wrong */
970 pdata->version = (u8)((int)match->data);
972 ret = of_property_read_u32(np, "op-mode", &val);
974 pdata->op_mode = val;
976 ret = of_property_read_u32(np, "tdm-slots", &val);
978 pdata->tdm_slots = val;
980 ret = of_property_read_u32(np, "num-serializer", &val);
982 pdata->num_serializer = val;
984 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
986 if (val != pdata->num_serializer) {
988 "num-serializer(%d) != serial-dir size(%d)\n",
989 pdata->num_serializer, val);
994 if (of_serial_dir32) {
995 of_serial_dir = devm_kzalloc(&pdev->dev,
996 (sizeof(*of_serial_dir) * val),
998 if (!of_serial_dir) {
1003 for (i = 0; i < pdata->num_serializer; i++)
1004 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1006 pdata->serial_dir = of_serial_dir;
1009 ret = of_property_read_u32(np, "tx-num-evt", &val);
1011 pdata->txnumevt = val;
1013 ret = of_property_read_u32(np, "rx-num-evt", &val);
1015 pdata->rxnumevt = val;
1017 ret = of_property_read_u32(np, "sram-size-playback", &val);
1019 pdata->sram_size_playback = val;
1021 ret = of_property_read_u32(np, "sram-size-capture", &val);
1023 pdata->sram_size_capture = val;
1029 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1036 static int davinci_mcasp_probe(struct platform_device *pdev)
1038 struct davinci_pcm_dma_params *dma_data;
1039 struct resource *mem, *ioarea, *res;
1040 struct snd_platform_data *pdata;
1041 struct davinci_audio_dev *dev;
1044 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1045 dev_err(&pdev->dev, "No platform data supplied\n");
1049 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
1054 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1056 dev_err(&pdev->dev, "no platform data\n");
1060 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1062 dev_err(&pdev->dev, "no mem resource?\n");
1066 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
1067 resource_size(mem), pdev->name);
1069 dev_err(&pdev->dev, "Audio region already claimed\n");
1073 pm_runtime_enable(&pdev->dev);
1075 ret = pm_runtime_get_sync(&pdev->dev);
1076 if (IS_ERR_VALUE(ret)) {
1077 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1081 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1083 dev_err(&pdev->dev, "ioremap failed\n");
1085 goto err_release_clk;
1088 dev->op_mode = pdata->op_mode;
1089 dev->tdm_slots = pdata->tdm_slots;
1090 dev->num_serializer = pdata->num_serializer;
1091 dev->serial_dir = pdata->serial_dir;
1092 dev->codec_fmt = pdata->codec_fmt;
1093 dev->version = pdata->version;
1094 dev->txnumevt = pdata->txnumevt;
1095 dev->rxnumevt = pdata->rxnumevt;
1096 dev->dev = &pdev->dev;
1098 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
1099 dma_data->asp_chan_q = pdata->asp_chan_q;
1100 dma_data->ram_chan_q = pdata->ram_chan_q;
1101 dma_data->sram_size = pdata->sram_size_playback;
1102 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
1105 /* first TX, then RX */
1106 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1108 dev_err(&pdev->dev, "no DMA resource\n");
1110 goto err_release_clk;
1113 dma_data->channel = res->start;
1115 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
1116 dma_data->asp_chan_q = pdata->asp_chan_q;
1117 dma_data->ram_chan_q = pdata->ram_chan_q;
1118 dma_data->sram_size = pdata->sram_size_capture;
1119 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
1122 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1124 dev_err(&pdev->dev, "no DMA resource\n");
1126 goto err_release_clk;
1129 dma_data->channel = res->start;
1130 dev_set_drvdata(&pdev->dev, dev);
1131 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
1134 goto err_release_clk;
1136 ret = davinci_soc_platform_register(&pdev->dev);
1138 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1139 goto err_unregister_dai;
1145 snd_soc_unregister_dai(&pdev->dev);
1147 pm_runtime_put_sync(&pdev->dev);
1148 pm_runtime_disable(&pdev->dev);
1152 static int davinci_mcasp_remove(struct platform_device *pdev)
1155 snd_soc_unregister_dai(&pdev->dev);
1156 davinci_soc_platform_unregister(&pdev->dev);
1158 pm_runtime_put_sync(&pdev->dev);
1159 pm_runtime_disable(&pdev->dev);
1164 static struct platform_driver davinci_mcasp_driver = {
1165 .probe = davinci_mcasp_probe,
1166 .remove = davinci_mcasp_remove,
1168 .name = "davinci-mcasp",
1169 .owner = THIS_MODULE,
1170 .of_match_table = of_match_ptr(mcasp_dt_ids),
1174 module_platform_driver(davinci_mcasp_driver);
1176 MODULE_AUTHOR("Steve Chen");
1177 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1178 MODULE_LICENSE("GPL");