2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
32 #include "davinci-pcm.h"
33 #include "davinci-mcasp.h"
36 * McASP register definitions
38 #define DAVINCI_MCASP_PID_REG 0x00
39 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
41 #define DAVINCI_MCASP_PFUNC_REG 0x10
42 #define DAVINCI_MCASP_PDIR_REG 0x14
43 #define DAVINCI_MCASP_PDOUT_REG 0x18
44 #define DAVINCI_MCASP_PDSET_REG 0x1c
46 #define DAVINCI_MCASP_PDCLR_REG 0x20
48 #define DAVINCI_MCASP_TLGC_REG 0x30
49 #define DAVINCI_MCASP_TLMR_REG 0x34
51 #define DAVINCI_MCASP_GBLCTL_REG 0x44
52 #define DAVINCI_MCASP_AMUTE_REG 0x48
53 #define DAVINCI_MCASP_LBCTL_REG 0x4c
55 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
57 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
58 #define DAVINCI_MCASP_RXMASK_REG 0x64
59 #define DAVINCI_MCASP_RXFMT_REG 0x68
60 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
62 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
63 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
64 #define DAVINCI_MCASP_RXTDM_REG 0x78
65 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
67 #define DAVINCI_MCASP_RXSTAT_REG 0x80
68 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
69 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
70 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
72 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
73 #define DAVINCI_MCASP_TXMASK_REG 0xa4
74 #define DAVINCI_MCASP_TXFMT_REG 0xa8
75 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
77 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
78 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
79 #define DAVINCI_MCASP_TXTDM_REG 0xb8
80 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
82 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
83 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
84 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
85 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
87 /* Left(even TDM Slot) Channel Status Register File */
88 #define DAVINCI_MCASP_DITCSRA_REG 0x100
89 /* Right(odd TDM slot) Channel Status Register File */
90 #define DAVINCI_MCASP_DITCSRB_REG 0x118
91 /* Left(even TDM slot) User Data Register File */
92 #define DAVINCI_MCASP_DITUDRA_REG 0x130
93 /* Right(odd TDM Slot) User Data Register File */
94 #define DAVINCI_MCASP_DITUDRB_REG 0x148
96 /* Serializer n Control Register */
97 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
98 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
101 /* Transmit Buffer for Serializer n */
102 #define DAVINCI_MCASP_TXBUF_REG 0x200
103 /* Receive Buffer for Serializer n */
104 #define DAVINCI_MCASP_RXBUF_REG 0x280
106 /* McASP FIFO Registers */
107 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
108 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
109 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
110 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
113 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
116 #define MCASP_FREE BIT(0)
117 #define MCASP_SOFT BIT(1)
120 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
122 #define AXR(n) (1<<n)
123 #define PFUNC_AMUTE BIT(25)
124 #define ACLKX BIT(26)
125 #define AHCLKX BIT(27)
127 #define ACLKR BIT(29)
128 #define AHCLKR BIT(30)
132 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
134 #define AXR(n) (1<<n)
135 #define PDIR_AMUTE BIT(25)
136 #define ACLKX BIT(26)
137 #define AHCLKX BIT(27)
139 #define ACLKR BIT(29)
140 #define AHCLKR BIT(30)
144 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
146 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
151 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
153 #define TXROT(val) (val)
155 #define TXSSZ(val) (val<<4)
156 #define TXPBIT(val) (val<<8)
157 #define TXPAD(val) (val<<13)
158 #define TXORD BIT(15)
159 #define FSXDLY(val) (val<<16)
162 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
164 #define RXROT(val) (val)
166 #define RXSSZ(val) (val<<4)
167 #define RXPBIT(val) (val<<8)
168 #define RXPAD(val) (val<<13)
169 #define RXORD BIT(15)
170 #define FSRDLY(val) (val<<16)
173 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
175 #define FSXPOL BIT(0)
177 #define FSXDUR BIT(4)
178 #define FSXMOD(val) (val<<7)
181 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
183 #define FSRPOL BIT(0)
185 #define FSRDUR BIT(4)
186 #define FSRMOD(val) (val<<7)
189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
191 #define ACLKXDIV(val) (val)
192 #define ACLKXE BIT(5)
193 #define TX_ASYNC BIT(6)
194 #define ACLKXPOL BIT(7)
197 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
199 #define ACLKRDIV(val) (val)
200 #define ACLKRE BIT(5)
201 #define RX_ASYNC BIT(6)
202 #define ACLKRPOL BIT(7)
205 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
208 #define AHCLKXDIV(val) (val)
209 #define AHCLKXPOL BIT(14)
210 #define AHCLKXE BIT(15)
213 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
216 #define AHCLKRDIV(val) (val)
217 #define AHCLKRPOL BIT(14)
218 #define AHCLKRE BIT(15)
221 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
223 #define MODE(val) (val)
224 #define DISMOD (val)(val<<2)
225 #define TXSTATE BIT(4)
226 #define RXSTATE BIT(5)
229 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
233 #define LBGENMODE(val) (val<<2)
236 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
238 #define TXTDMS(n) (1<<n)
241 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
243 #define RXTDMS(n) (1<<n)
246 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
248 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
249 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
250 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
251 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
252 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
253 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
254 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
255 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
256 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
257 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
260 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
262 #define MUTENA(val) (val)
263 #define MUTEINPOL BIT(2)
264 #define MUTEINENA BIT(3)
265 #define MUTEIN BIT(4)
268 #define MUTEFSR BIT(7)
269 #define MUTEFSX BIT(8)
270 #define MUTEBADCLKR BIT(9)
271 #define MUTEBADCLKX BIT(10)
272 #define MUTERXDMAERR BIT(11)
273 #define MUTETXDMAERR BIT(12)
276 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
278 #define RXDATADMADIS BIT(0)
281 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
283 #define TXDATADMADIS BIT(0)
286 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
288 #define FIFO_ENABLE BIT(16)
289 #define NUMEVT_MASK (0xFF << 8)
290 #define NUMDMA_MASK (0xFF)
292 #define DAVINCI_MCASP_NUM_SERIALIZER 16
294 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
296 __raw_writel(__raw_readl(reg) | val, reg);
299 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
301 __raw_writel((__raw_readl(reg) & ~(val)), reg);
304 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
306 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
309 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
311 __raw_writel(val, reg);
314 static inline u32 mcasp_get_reg(void __iomem *reg)
316 return (unsigned int)__raw_readl(reg);
319 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
323 mcasp_set_bits(regs, val);
325 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
326 /* loop count is to avoid the lock-up */
327 for (i = 0; i < 1000; i++) {
328 if ((mcasp_get_reg(regs) & val) == val)
332 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
333 printk(KERN_ERR "GBLCTL write error\n");
336 static void mcasp_start_rx(struct davinci_audio_dev *dev)
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
340 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
341 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
344 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
345 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
351 static void mcasp_start_tx(struct davinci_audio_dev *dev)
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
359 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
362 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
363 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
364 for (i = 0; i < dev->num_serializer; i++) {
365 if (dev->serial_dir[i] == TX_MODE) {
371 /* wait for TX ready */
373 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
374 TXSTATE) && (cnt < 100000))
377 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
380 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
382 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
383 if (dev->txnumevt) { /* enable FIFO */
384 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
386 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
391 if (dev->rxnumevt) { /* enable FIFO */
392 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
394 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
401 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
407 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
409 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
410 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
413 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
415 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
416 if (dev->txnumevt) /* disable FIFO */
417 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
421 if (dev->rxnumevt) /* disable FIFO */
422 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
428 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
431 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
432 void __iomem *base = dev->base;
434 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
435 case SND_SOC_DAIFMT_CBS_CFS:
436 /* codec is clock and frame slave */
437 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
438 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
440 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
441 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
443 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
444 ACLKX | AHCLKX | AFSX);
446 case SND_SOC_DAIFMT_CBM_CFS:
447 /* codec is clock master and frame slave */
448 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
449 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
452 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
454 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
456 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
459 case SND_SOC_DAIFMT_CBM_CFM:
460 /* codec is clock and frame master */
461 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
462 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
464 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
465 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
467 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
468 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
475 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
476 case SND_SOC_DAIFMT_IB_NF:
477 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
478 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
480 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
481 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
484 case SND_SOC_DAIFMT_NB_IF:
485 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
486 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
488 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
489 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
492 case SND_SOC_DAIFMT_IB_IF:
493 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
494 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
496 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
497 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
500 case SND_SOC_DAIFMT_NB_NF:
501 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
502 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
504 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
505 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
515 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
521 switch (channel_size) {
522 case DAVINCI_AUDIO_WORD_8:
528 case DAVINCI_AUDIO_WORD_12:
534 case DAVINCI_AUDIO_WORD_16:
540 case DAVINCI_AUDIO_WORD_20:
546 case DAVINCI_AUDIO_WORD_24:
552 case DAVINCI_AUDIO_WORD_28:
558 case DAVINCI_AUDIO_WORD_32:
568 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
569 RXSSZ(fmt), RXSSZ(0x0F));
570 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
571 TXSSZ(fmt), TXSSZ(0x0F));
572 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
574 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
576 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
577 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
582 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
588 /* Default configuration */
589 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
591 /* All PINS as McASP */
592 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
594 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
595 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
596 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
599 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
600 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
604 for (i = 0; i < dev->num_serializer; i++) {
605 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
607 if (dev->serial_dir[i] == TX_MODE) {
608 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
611 } else if (dev->serial_dir[i] == RX_MODE) {
612 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
618 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
619 if (dev->txnumevt * tx_ser > 64)
622 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
624 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
625 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
628 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
629 if (dev->rxnumevt * rx_ser > 64)
632 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
634 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
635 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
639 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
644 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
645 for (i = 0; i < active_slots; i++)
648 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
650 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
651 /* bit stream is MSB first with no delay */
653 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
655 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
656 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
658 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
659 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
660 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
662 printk(KERN_ERR "playback tdm slot %d not supported\n",
665 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
667 /* bit stream is MSB first with no delay */
669 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
670 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
672 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
674 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
675 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
676 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
678 printk(KERN_ERR "capture tdm slot %d not supported\n",
681 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
686 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
688 /* Set the PDIR for Serialiser as output */
689 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
691 /* TXMASK for 24 bits */
692 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
694 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
696 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
697 TXROT(6) | TXSSZ(15));
699 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
700 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
701 AFSXE | FSXMOD(0x180));
703 /* Set the TX tdm : for all the slots */
704 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
706 /* Set the TX clock controls : div = 1 and internal */
707 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
710 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
712 /* Only 44100 and 48000 are valid, both have the same setting */
713 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
716 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
719 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
720 struct snd_pcm_hw_params *params,
721 struct snd_soc_dai *cpu_dai)
723 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
724 struct davinci_pcm_dma_params *dma_params =
725 &dev->dma_params[substream->stream];
729 davinci_hw_common_param(dev, substream->stream);
730 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
731 fifo_level = dev->txnumevt;
733 fifo_level = dev->rxnumevt;
735 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
736 davinci_hw_dit_param(dev);
738 davinci_hw_param(dev, substream->stream);
740 switch (params_format(params)) {
741 case SNDRV_PCM_FORMAT_U8:
742 case SNDRV_PCM_FORMAT_S8:
743 dma_params->data_type = 1;
744 word_length = DAVINCI_AUDIO_WORD_8;
747 case SNDRV_PCM_FORMAT_U16_LE:
748 case SNDRV_PCM_FORMAT_S16_LE:
749 dma_params->data_type = 2;
750 word_length = DAVINCI_AUDIO_WORD_16;
753 case SNDRV_PCM_FORMAT_U32_LE:
754 case SNDRV_PCM_FORMAT_S32_LE:
755 dma_params->data_type = 4;
756 word_length = DAVINCI_AUDIO_WORD_32;
760 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
764 if (dev->version == MCASP_VERSION_2 && !fifo_level)
765 dma_params->acnt = 4;
767 dma_params->acnt = dma_params->data_type;
769 dma_params->fifo_level = fifo_level;
770 davinci_config_channel_size(dev, word_length);
775 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
776 int cmd, struct snd_soc_dai *cpu_dai)
778 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
782 case SNDRV_PCM_TRIGGER_RESUME:
783 case SNDRV_PCM_TRIGGER_START:
784 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
785 if (!dev->clk_active) {
786 clk_enable(dev->clk);
789 davinci_mcasp_start(dev, substream->stream);
792 case SNDRV_PCM_TRIGGER_SUSPEND:
793 davinci_mcasp_stop(dev, substream->stream);
794 if (dev->clk_active) {
795 clk_disable(dev->clk);
801 case SNDRV_PCM_TRIGGER_STOP:
802 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
803 davinci_mcasp_stop(dev, substream->stream);
813 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
814 struct snd_soc_dai *dai)
816 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
818 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
822 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
823 .startup = davinci_mcasp_startup,
824 .trigger = davinci_mcasp_trigger,
825 .hw_params = davinci_mcasp_hw_params,
826 .set_fmt = davinci_mcasp_set_dai_fmt,
830 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
831 SNDRV_PCM_FMTBIT_U8 | \
832 SNDRV_PCM_FMTBIT_S16_LE | \
833 SNDRV_PCM_FMTBIT_U16_LE | \
834 SNDRV_PCM_FMTBIT_S32_LE | \
835 SNDRV_PCM_FMTBIT_U32_LE)
837 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
839 .name = "davinci-mcasp.0",
843 .rates = DAVINCI_MCASP_RATES,
844 .formats = DAVINCI_MCASP_PCM_FMTS,
849 .rates = DAVINCI_MCASP_RATES,
850 .formats = DAVINCI_MCASP_PCM_FMTS,
852 .ops = &davinci_mcasp_dai_ops,
860 .rates = DAVINCI_MCASP_RATES,
861 .formats = DAVINCI_MCASP_PCM_FMTS,
863 .ops = &davinci_mcasp_dai_ops,
868 static int davinci_mcasp_probe(struct platform_device *pdev)
870 struct davinci_pcm_dma_params *dma_data;
871 struct resource *mem, *ioarea, *res;
872 struct snd_platform_data *pdata;
873 struct davinci_audio_dev *dev;
876 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
881 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
883 dev_err(&pdev->dev, "no mem resource?\n");
887 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
888 resource_size(mem), pdev->name);
890 dev_err(&pdev->dev, "Audio region already claimed\n");
894 pdata = pdev->dev.platform_data;
895 dev->clk = clk_get(&pdev->dev, NULL);
896 if (IS_ERR(dev->clk))
899 clk_enable(dev->clk);
902 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
904 dev_err(&pdev->dev, "ioremap failed\n");
906 goto err_release_clk;
909 dev->op_mode = pdata->op_mode;
910 dev->tdm_slots = pdata->tdm_slots;
911 dev->num_serializer = pdata->num_serializer;
912 dev->serial_dir = pdata->serial_dir;
913 dev->codec_fmt = pdata->codec_fmt;
914 dev->version = pdata->version;
915 dev->txnumevt = pdata->txnumevt;
916 dev->rxnumevt = pdata->rxnumevt;
918 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
919 dma_data->asp_chan_q = pdata->asp_chan_q;
920 dma_data->ram_chan_q = pdata->ram_chan_q;
921 dma_data->sram_size = pdata->sram_size_playback;
922 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
925 /* first TX, then RX */
926 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
928 dev_err(&pdev->dev, "no DMA resource\n");
930 goto err_release_clk;
933 dma_data->channel = res->start;
935 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
936 dma_data->asp_chan_q = pdata->asp_chan_q;
937 dma_data->ram_chan_q = pdata->ram_chan_q;
938 dma_data->sram_size = pdata->sram_size_capture;
939 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
942 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
944 dev_err(&pdev->dev, "no DMA resource\n");
946 goto err_release_clk;
949 dma_data->channel = res->start;
950 dev_set_drvdata(&pdev->dev, dev);
951 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
954 goto err_release_clk;
958 clk_disable(dev->clk);
963 static int davinci_mcasp_remove(struct platform_device *pdev)
965 struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
967 snd_soc_unregister_dai(&pdev->dev);
968 clk_disable(dev->clk);
975 static struct platform_driver davinci_mcasp_driver = {
976 .probe = davinci_mcasp_probe,
977 .remove = davinci_mcasp_remove,
979 .name = "davinci-mcasp",
980 .owner = THIS_MODULE,
984 module_platform_driver(davinci_mcasp_driver);
986 MODULE_AUTHOR("Steve Chen");
987 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
988 MODULE_LICENSE("GPL");