2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
4 * Multi-channel Audio Serial Port Driver
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
24 #include <linux/clk.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
32 #include "davinci-pcm.h"
33 #include "davinci-mcasp.h"
36 * McASP register definitions
38 #define DAVINCI_MCASP_PID_REG 0x00
39 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
41 #define DAVINCI_MCASP_PFUNC_REG 0x10
42 #define DAVINCI_MCASP_PDIR_REG 0x14
43 #define DAVINCI_MCASP_PDOUT_REG 0x18
44 #define DAVINCI_MCASP_PDSET_REG 0x1c
46 #define DAVINCI_MCASP_PDCLR_REG 0x20
48 #define DAVINCI_MCASP_TLGC_REG 0x30
49 #define DAVINCI_MCASP_TLMR_REG 0x34
51 #define DAVINCI_MCASP_GBLCTL_REG 0x44
52 #define DAVINCI_MCASP_AMUTE_REG 0x48
53 #define DAVINCI_MCASP_LBCTL_REG 0x4c
55 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
57 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
58 #define DAVINCI_MCASP_RXMASK_REG 0x64
59 #define DAVINCI_MCASP_RXFMT_REG 0x68
60 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
62 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
63 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
64 #define DAVINCI_MCASP_RXTDM_REG 0x78
65 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
67 #define DAVINCI_MCASP_RXSTAT_REG 0x80
68 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
69 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
70 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
72 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
73 #define DAVINCI_MCASP_TXMASK_REG 0xa4
74 #define DAVINCI_MCASP_TXFMT_REG 0xa8
75 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
77 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
78 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
79 #define DAVINCI_MCASP_TXTDM_REG 0xb8
80 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
82 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
83 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
84 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
85 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
87 /* Left(even TDM Slot) Channel Status Register File */
88 #define DAVINCI_MCASP_DITCSRA_REG 0x100
89 /* Right(odd TDM slot) Channel Status Register File */
90 #define DAVINCI_MCASP_DITCSRB_REG 0x118
91 /* Left(even TDM slot) User Data Register File */
92 #define DAVINCI_MCASP_DITUDRA_REG 0x130
93 /* Right(odd TDM Slot) User Data Register File */
94 #define DAVINCI_MCASP_DITUDRB_REG 0x148
96 /* Serializer n Control Register */
97 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
98 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
101 /* Transmit Buffer for Serializer n */
102 #define DAVINCI_MCASP_TXBUF_REG 0x200
103 /* Receive Buffer for Serializer n */
104 #define DAVINCI_MCASP_RXBUF_REG 0x280
106 /* McASP FIFO Registers */
107 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
108 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
109 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
110 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
113 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
116 #define MCASP_FREE BIT(0)
117 #define MCASP_SOFT BIT(1)
120 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
122 #define AXR(n) (1<<n)
123 #define PFUNC_AMUTE BIT(25)
124 #define ACLKX BIT(26)
125 #define AHCLKX BIT(27)
127 #define ACLKR BIT(29)
128 #define AHCLKR BIT(30)
132 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
134 #define AXR(n) (1<<n)
135 #define PDIR_AMUTE BIT(25)
136 #define ACLKX BIT(26)
137 #define AHCLKX BIT(27)
139 #define ACLKR BIT(29)
140 #define AHCLKR BIT(30)
144 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
146 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
151 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
153 #define TXROT(val) (val)
155 #define TXSSZ(val) (val<<4)
156 #define TXPBIT(val) (val<<8)
157 #define TXPAD(val) (val<<13)
158 #define TXORD BIT(15)
159 #define FSXDLY(val) (val<<16)
162 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
164 #define RXROT(val) (val)
166 #define RXSSZ(val) (val<<4)
167 #define RXPBIT(val) (val<<8)
168 #define RXPAD(val) (val<<13)
169 #define RXORD BIT(15)
170 #define FSRDLY(val) (val<<16)
173 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
175 #define FSXPOL BIT(0)
177 #define FSXDUR BIT(4)
178 #define FSXMOD(val) (val<<7)
181 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
183 #define FSRPOL BIT(0)
185 #define FSRDUR BIT(4)
186 #define FSRMOD(val) (val<<7)
189 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
191 #define ACLKXDIV(val) (val)
192 #define ACLKXE BIT(5)
193 #define TX_ASYNC BIT(6)
194 #define ACLKXPOL BIT(7)
197 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
199 #define ACLKRDIV(val) (val)
200 #define ACLKRE BIT(5)
201 #define RX_ASYNC BIT(6)
202 #define ACLKRPOL BIT(7)
205 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
208 #define AHCLKXDIV(val) (val)
209 #define AHCLKXPOL BIT(14)
210 #define AHCLKXE BIT(15)
213 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
216 #define AHCLKRDIV(val) (val)
217 #define AHCLKRPOL BIT(14)
218 #define AHCLKRE BIT(15)
221 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
223 #define MODE(val) (val)
224 #define DISMOD (val)(val<<2)
225 #define TXSTATE BIT(4)
226 #define RXSTATE BIT(5)
229 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
233 #define LBGENMODE(val) (val<<2)
236 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
238 #define TXTDMS(n) (1<<n)
241 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
243 #define RXTDMS(n) (1<<n)
246 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
248 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
249 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
250 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
251 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
252 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
253 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
254 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
255 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
256 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
257 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
260 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
262 #define MUTENA(val) (val)
263 #define MUTEINPOL BIT(2)
264 #define MUTEINENA BIT(3)
265 #define MUTEIN BIT(4)
268 #define MUTEFSR BIT(7)
269 #define MUTEFSX BIT(8)
270 #define MUTEBADCLKR BIT(9)
271 #define MUTEBADCLKX BIT(10)
272 #define MUTERXDMAERR BIT(11)
273 #define MUTETXDMAERR BIT(12)
276 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
278 #define RXDATADMADIS BIT(0)
281 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
283 #define TXDATADMADIS BIT(0)
286 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
288 #define FIFO_ENABLE BIT(16)
289 #define NUMEVT_MASK (0xFF << 8)
290 #define NUMDMA_MASK (0xFF)
292 #define DAVINCI_MCASP_NUM_SERIALIZER 16
294 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
296 __raw_writel(__raw_readl(reg) | val, reg);
299 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
301 __raw_writel((__raw_readl(reg) & ~(val)), reg);
304 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
306 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
309 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
311 __raw_writel(val, reg);
314 static inline u32 mcasp_get_reg(void __iomem *reg)
316 return (unsigned int)__raw_readl(reg);
319 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
323 mcasp_set_bits(regs, val);
325 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
326 /* loop count is to avoid the lock-up */
327 for (i = 0; i < 1000; i++) {
328 if ((mcasp_get_reg(regs) & val) == val)
332 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
333 printk(KERN_ERR "GBLCTL write error\n");
336 static void mcasp_start_rx(struct davinci_audio_dev *dev)
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
340 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
341 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
344 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
345 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
351 static void mcasp_start_tx(struct davinci_audio_dev *dev)
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
358 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
359 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
362 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
363 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
364 for (i = 0; i < dev->num_serializer; i++) {
365 if (dev->serial_dir[i] == TX_MODE) {
371 /* wait for TX ready */
373 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
374 TXSTATE) && (cnt < 100000))
377 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
380 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
382 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
383 if (dev->txnumevt) /* enable FIFO */
384 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
388 if (dev->rxnumevt) /* enable FIFO */
389 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
395 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
397 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
398 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
401 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
404 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
407 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
409 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
410 if (dev->txnumevt) /* disable FIFO */
411 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
415 if (dev->rxnumevt) /* disable FIFO */
416 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
422 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
425 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
426 void __iomem *base = dev->base;
428 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
429 case SND_SOC_DAIFMT_CBS_CFS:
430 /* codec is clock and frame slave */
431 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
432 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
434 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
435 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
437 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
438 ACLKX | AHCLKX | AFSX);
440 case SND_SOC_DAIFMT_CBM_CFS:
441 /* codec is clock master and frame slave */
442 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
443 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
445 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
446 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
448 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
450 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
453 case SND_SOC_DAIFMT_CBM_CFM:
454 /* codec is clock and frame master */
455 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
456 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
458 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
459 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
461 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
462 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
469 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
470 case SND_SOC_DAIFMT_IB_NF:
471 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
472 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
474 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
475 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
478 case SND_SOC_DAIFMT_NB_IF:
479 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
480 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
482 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
483 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
486 case SND_SOC_DAIFMT_IB_IF:
487 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
488 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
490 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
491 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
494 case SND_SOC_DAIFMT_NB_NF:
495 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
496 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
498 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
499 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
509 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
515 switch (channel_size) {
516 case DAVINCI_AUDIO_WORD_8:
522 case DAVINCI_AUDIO_WORD_12:
528 case DAVINCI_AUDIO_WORD_16:
534 case DAVINCI_AUDIO_WORD_20:
540 case DAVINCI_AUDIO_WORD_24:
546 case DAVINCI_AUDIO_WORD_28:
552 case DAVINCI_AUDIO_WORD_32:
562 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
563 RXSSZ(fmt), RXSSZ(0x0F));
564 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
565 TXSSZ(fmt), TXSSZ(0x0F));
566 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
568 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
570 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
571 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
576 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
582 /* Default configuration */
583 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
585 /* All PINS as McASP */
586 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
588 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
589 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
590 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
593 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
594 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
598 for (i = 0; i < dev->num_serializer; i++) {
599 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
601 if (dev->serial_dir[i] == TX_MODE) {
602 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
605 } else if (dev->serial_dir[i] == RX_MODE) {
606 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
612 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
613 if (dev->txnumevt * tx_ser > 64)
616 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
618 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
619 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
622 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
623 if (dev->rxnumevt * rx_ser > 64)
626 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
628 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
629 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
633 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
638 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
639 for (i = 0; i < active_slots; i++)
642 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
644 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
645 /* bit stream is MSB first with no delay */
647 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
649 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
650 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
652 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
653 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
654 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
656 printk(KERN_ERR "playback tdm slot %d not supported\n",
659 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
661 /* bit stream is MSB first with no delay */
663 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
664 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
666 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
668 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
669 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
670 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
672 printk(KERN_ERR "capture tdm slot %d not supported\n",
675 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
680 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
682 /* Set the PDIR for Serialiser as output */
683 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
685 /* TXMASK for 24 bits */
686 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
688 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
690 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
691 TXROT(6) | TXSSZ(15));
693 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
694 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
695 AFSXE | FSXMOD(0x180));
697 /* Set the TX tdm : for all the slots */
698 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
700 /* Set the TX clock controls : div = 1 and internal */
701 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
704 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
706 /* Only 44100 and 48000 are valid, both have the same setting */
707 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
710 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
713 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
714 struct snd_pcm_hw_params *params,
715 struct snd_soc_dai *cpu_dai)
717 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
718 struct davinci_pcm_dma_params *dma_params =
719 &dev->dma_params[substream->stream];
723 davinci_hw_common_param(dev, substream->stream);
724 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
725 fifo_level = dev->txnumevt;
727 fifo_level = dev->rxnumevt;
729 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
730 davinci_hw_dit_param(dev);
732 davinci_hw_param(dev, substream->stream);
734 switch (params_format(params)) {
735 case SNDRV_PCM_FORMAT_S8:
736 dma_params->data_type = 1;
737 word_length = DAVINCI_AUDIO_WORD_8;
740 case SNDRV_PCM_FORMAT_S16_LE:
741 dma_params->data_type = 2;
742 word_length = DAVINCI_AUDIO_WORD_16;
745 case SNDRV_PCM_FORMAT_S32_LE:
746 dma_params->data_type = 4;
747 word_length = DAVINCI_AUDIO_WORD_32;
751 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
755 if (dev->version == MCASP_VERSION_2 && !fifo_level)
756 dma_params->acnt = 4;
758 dma_params->acnt = dma_params->data_type;
760 dma_params->fifo_level = fifo_level;
761 davinci_config_channel_size(dev, word_length);
766 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
767 int cmd, struct snd_soc_dai *cpu_dai)
769 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
773 case SNDRV_PCM_TRIGGER_RESUME:
774 case SNDRV_PCM_TRIGGER_START:
775 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
776 if (!dev->clk_active) {
777 clk_enable(dev->clk);
780 davinci_mcasp_start(dev, substream->stream);
783 case SNDRV_PCM_TRIGGER_SUSPEND:
784 davinci_mcasp_stop(dev, substream->stream);
785 if (dev->clk_active) {
786 clk_disable(dev->clk);
792 case SNDRV_PCM_TRIGGER_STOP:
793 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
794 davinci_mcasp_stop(dev, substream->stream);
804 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
805 struct snd_soc_dai *dai)
807 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
809 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
813 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
814 .startup = davinci_mcasp_startup,
815 .trigger = davinci_mcasp_trigger,
816 .hw_params = davinci_mcasp_hw_params,
817 .set_fmt = davinci_mcasp_set_dai_fmt,
821 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
823 .name = "davinci-mcasp.0",
827 .rates = DAVINCI_MCASP_RATES,
828 .formats = SNDRV_PCM_FMTBIT_S8 |
829 SNDRV_PCM_FMTBIT_S16_LE |
830 SNDRV_PCM_FMTBIT_S32_LE,
835 .rates = DAVINCI_MCASP_RATES,
836 .formats = SNDRV_PCM_FMTBIT_S8 |
837 SNDRV_PCM_FMTBIT_S16_LE |
838 SNDRV_PCM_FMTBIT_S32_LE,
840 .ops = &davinci_mcasp_dai_ops,
848 .rates = DAVINCI_MCASP_RATES,
849 .formats = SNDRV_PCM_FMTBIT_S16_LE,
851 .ops = &davinci_mcasp_dai_ops,
856 static int davinci_mcasp_probe(struct platform_device *pdev)
858 struct davinci_pcm_dma_params *dma_data;
859 struct resource *mem, *ioarea, *res;
860 struct snd_platform_data *pdata;
861 struct davinci_audio_dev *dev;
864 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
868 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
870 dev_err(&pdev->dev, "no mem resource?\n");
872 goto err_release_data;
875 ioarea = request_mem_region(mem->start,
876 resource_size(mem), pdev->name);
878 dev_err(&pdev->dev, "Audio region already claimed\n");
880 goto err_release_data;
883 pdata = pdev->dev.platform_data;
884 dev->clk = clk_get(&pdev->dev, NULL);
885 if (IS_ERR(dev->clk)) {
887 goto err_release_region;
890 clk_enable(dev->clk);
893 dev->base = ioremap(mem->start, resource_size(mem));
895 dev_err(&pdev->dev, "ioremap failed\n");
897 goto err_release_clk;
900 dev->op_mode = pdata->op_mode;
901 dev->tdm_slots = pdata->tdm_slots;
902 dev->num_serializer = pdata->num_serializer;
903 dev->serial_dir = pdata->serial_dir;
904 dev->codec_fmt = pdata->codec_fmt;
905 dev->version = pdata->version;
906 dev->txnumevt = pdata->txnumevt;
907 dev->rxnumevt = pdata->rxnumevt;
909 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
910 dma_data->asp_chan_q = pdata->asp_chan_q;
911 dma_data->ram_chan_q = pdata->ram_chan_q;
912 dma_data->sram_size = pdata->sram_size_playback;
913 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
916 /* first TX, then RX */
917 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
919 dev_err(&pdev->dev, "no DMA resource\n");
924 dma_data->channel = res->start;
926 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
927 dma_data->asp_chan_q = pdata->asp_chan_q;
928 dma_data->ram_chan_q = pdata->ram_chan_q;
929 dma_data->sram_size = pdata->sram_size_capture;
930 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
933 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
935 dev_err(&pdev->dev, "no DMA resource\n");
940 dma_data->channel = res->start;
941 dev_set_drvdata(&pdev->dev, dev);
942 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
951 clk_disable(dev->clk);
954 release_mem_region(mem->start, resource_size(mem));
961 static int davinci_mcasp_remove(struct platform_device *pdev)
963 struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
964 struct resource *mem;
966 snd_soc_unregister_dai(&pdev->dev);
967 clk_disable(dev->clk);
971 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
972 release_mem_region(mem->start, resource_size(mem));
979 static struct platform_driver davinci_mcasp_driver = {
980 .probe = davinci_mcasp_probe,
981 .remove = davinci_mcasp_remove,
983 .name = "davinci-mcasp",
984 .owner = THIS_MODULE,
988 static int __init davinci_mcasp_init(void)
990 return platform_driver_register(&davinci_mcasp_driver);
992 module_init(davinci_mcasp_init);
994 static void __exit davinci_mcasp_exit(void)
996 platform_driver_unregister(&davinci_mcasp_driver);
998 module_exit(davinci_mcasp_exit);
1000 MODULE_AUTHOR("Steve Chen");
1001 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1002 MODULE_LICENSE("GPL");