2 * linux/sound/soc/ep93xx-i2s.c
5 * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
7 * Based on the original driver by:
8 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/slab.h>
20 #include <linux/clk.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/initval.h>
27 #include <sound/soc.h>
29 #include <mach/hardware.h>
30 #include <mach/ep93xx-regs.h>
33 #include "ep93xx-pcm.h"
35 #define EP93XX_I2S_TXCLKCFG 0x00
36 #define EP93XX_I2S_RXCLKCFG 0x04
37 #define EP93XX_I2S_GLCTRL 0x0C
39 #define EP93XX_I2S_TXLINCTRLDATA 0x28
40 #define EP93XX_I2S_TXCTRL 0x2C
41 #define EP93XX_I2S_TXWRDLEN 0x30
42 #define EP93XX_I2S_TX0EN 0x34
44 #define EP93XX_I2S_RXLINCTRLDATA 0x58
45 #define EP93XX_I2S_RXCTRL 0x5C
46 #define EP93XX_I2S_RXWRDLEN 0x60
47 #define EP93XX_I2S_RX0EN 0x64
49 #define EP93XX_I2S_WRDLEN_16 (0 << 0)
50 #define EP93XX_I2S_WRDLEN_24 (1 << 0)
51 #define EP93XX_I2S_WRDLEN_32 (2 << 0)
53 #define EP93XX_I2S_LINCTRLDATA_R_JUST (1 << 2) /* Right justify */
55 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
56 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
57 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
58 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
59 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
61 struct ep93xx_i2s_info {
65 struct ep93xx_pcm_dma_params *dma_params;
70 struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
71 [SNDRV_PCM_STREAM_PLAYBACK] = {
72 .name = "i2s-pcm-out",
73 .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
75 [SNDRV_PCM_STREAM_CAPTURE] = {
77 .dma_port = EP93XX_DMA_M2P_PORT_I2S1,
81 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
82 unsigned reg, unsigned val)
84 __raw_writel(val, info->regs + reg);
87 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
90 return __raw_readl(info->regs + reg);
93 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
98 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
99 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
101 clk_enable(info->mclk);
102 clk_enable(info->sclk);
103 clk_enable(info->lrclk);
106 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
110 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
111 base_reg = EP93XX_I2S_TX0EN;
113 base_reg = EP93XX_I2S_RX0EN;
114 for (i = 0; i < 3; i++)
115 ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
118 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
124 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
125 base_reg = EP93XX_I2S_TX0EN;
127 base_reg = EP93XX_I2S_RX0EN;
128 for (i = 0; i < 3; i++)
129 ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
131 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
132 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
134 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
137 clk_disable(info->lrclk);
138 clk_disable(info->sclk);
139 clk_disable(info->mclk);
143 static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
144 struct snd_soc_dai *dai)
146 struct snd_soc_pcm_runtime *rtd = substream->private_data;
147 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
148 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
150 snd_soc_dai_set_dma_data(cpu_dai, substream,
151 &info->dma_params[substream->stream]);
155 static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
156 struct snd_soc_dai *dai)
158 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
160 ep93xx_i2s_disable(info, substream->stream);
163 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
166 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
167 unsigned int clk_cfg, lin_ctrl;
169 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
170 lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
172 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
173 case SND_SOC_DAIFMT_I2S:
174 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
175 lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
178 case SND_SOC_DAIFMT_LEFT_J:
179 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
180 lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
183 case SND_SOC_DAIFMT_RIGHT_J:
184 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
185 lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
192 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
193 case SND_SOC_DAIFMT_CBS_CFS:
195 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
198 case SND_SOC_DAIFMT_CBM_CFM:
199 /* Codec is master */
200 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
207 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
208 case SND_SOC_DAIFMT_NB_NF:
209 /* Negative bit clock, lrclk low on left word */
210 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
213 case SND_SOC_DAIFMT_NB_IF:
214 /* Negative bit clock, lrclk low on right word */
215 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
216 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
219 case SND_SOC_DAIFMT_IB_NF:
220 /* Positive bit clock, lrclk low on left word */
221 clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
222 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
225 case SND_SOC_DAIFMT_IB_IF:
226 /* Positive bit clock, lrclk low on right word */
227 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
231 /* Write new register values */
232 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
233 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
234 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
235 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
239 static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
240 struct snd_pcm_hw_params *params,
241 struct snd_soc_dai *dai)
243 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
244 unsigned word_len, div, sdiv, lrdiv;
247 switch (params_format(params)) {
248 case SNDRV_PCM_FORMAT_S16_LE:
249 word_len = EP93XX_I2S_WRDLEN_16;
252 case SNDRV_PCM_FORMAT_S24_LE:
253 word_len = EP93XX_I2S_WRDLEN_24;
256 case SNDRV_PCM_FORMAT_S32_LE:
257 word_len = EP93XX_I2S_WRDLEN_32;
264 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
265 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
267 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
270 * Calculate the sdiv (bit clock) and lrdiv (left/right clock) values.
271 * If the lrclk is pulse length is larger than the word size, then the
272 * bit clock will be gated for the unused bits.
274 div = (clk_get_rate(info->mclk) / params_rate(params)) *
275 params_channels(params);
276 for (sdiv = 2; sdiv <= 4; sdiv += 2)
277 for (lrdiv = 32; lrdiv <= 128; lrdiv <<= 1)
278 if (sdiv * lrdiv == div) {
286 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
290 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
294 ep93xx_i2s_enable(info, substream->stream);
298 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
299 unsigned int freq, int dir)
301 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
303 if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
306 return clk_set_rate(info->mclk, freq);
310 static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
312 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
317 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
318 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
321 static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
323 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
328 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
329 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
332 #define ep93xx_i2s_suspend NULL
333 #define ep93xx_i2s_resume NULL
336 static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
337 .startup = ep93xx_i2s_startup,
338 .shutdown = ep93xx_i2s_shutdown,
339 .hw_params = ep93xx_i2s_hw_params,
340 .set_sysclk = ep93xx_i2s_set_sysclk,
341 .set_fmt = ep93xx_i2s_set_dai_fmt,
344 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
345 SNDRV_PCM_FMTBIT_S24_LE | \
346 SNDRV_PCM_FMTBIT_S32_LE)
348 static struct snd_soc_dai_driver ep93xx_i2s_dai = {
350 .suspend = ep93xx_i2s_suspend,
351 .resume = ep93xx_i2s_resume,
355 .rates = SNDRV_PCM_RATE_8000_96000,
356 .formats = EP93XX_I2S_FORMATS,
361 .rates = SNDRV_PCM_RATE_8000_96000,
362 .formats = EP93XX_I2S_FORMATS,
364 .ops = &ep93xx_i2s_dai_ops,
367 static int ep93xx_i2s_probe(struct platform_device *pdev)
369 struct ep93xx_i2s_info *info;
370 struct resource *res;
373 info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
379 dev_set_drvdata(&pdev->dev, info);
380 info->dma_params = ep93xx_i2s_dma_params;
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
388 info->mem = request_mem_region(res->start, resource_size(res),
395 info->regs = ioremap(info->mem->start, resource_size(info->mem));
398 goto fail_release_mem;
401 info->mclk = clk_get(&pdev->dev, "mclk");
402 if (IS_ERR(info->mclk)) {
403 err = PTR_ERR(info->mclk);
407 info->sclk = clk_get(&pdev->dev, "sclk");
408 if (IS_ERR(info->sclk)) {
409 err = PTR_ERR(info->sclk);
413 info->lrclk = clk_get(&pdev->dev, "lrclk");
414 if (IS_ERR(info->lrclk)) {
415 err = PTR_ERR(info->lrclk);
419 err = snd_soc_register_dai(&pdev->dev, &ep93xx_i2s_dai);
426 clk_put(info->lrclk);
434 release_mem_region(info->mem->start, resource_size(info->mem));
440 static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
442 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
444 snd_soc_unregister_dai(&pdev->dev);
445 clk_put(info->lrclk);
449 release_mem_region(info->mem->start, resource_size(info->mem));
454 static struct platform_driver ep93xx_i2s_driver = {
455 .probe = ep93xx_i2s_probe,
456 .remove = __devexit_p(ep93xx_i2s_remove),
458 .name = "ep93xx-i2s",
459 .owner = THIS_MODULE,
463 static int __init ep93xx_i2s_init(void)
465 return platform_driver_register(&ep93xx_i2s_driver);
468 static void __exit ep93xx_i2s_exit(void)
470 platform_driver_unregister(&ep93xx_i2s_driver);
473 module_init(ep93xx_i2s_init);
474 module_exit(ep93xx_i2s_exit);
476 MODULE_ALIAS("platform:ep93xx-i2s");
477 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com>");
478 MODULE_DESCRIPTION("EP93XX I2S driver");
479 MODULE_LICENSE("GPL");