2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
21 #include "fsl_utils.h"
23 #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
24 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
25 SNDRV_PCM_FMTBIT_S16_LE | \
26 SNDRV_PCM_FMTBIT_S20_3LE | \
27 SNDRV_PCM_FMTBIT_S24_LE)
30 * fsl_esai: ESAI private data
32 * @dma_params_rx: DMA parameters for receive channel
33 * @dma_params_tx: DMA parameters for transmit channel
34 * @pdev: platform device pointer
35 * @regmap: regmap handler
36 * @coreclk: clock source to access register
37 * @extalclk: esai clock source to derive HCK, SCK and FS
38 * @fsysclk: system clock source to derive HCK, SCK and FS
39 * @fifo_depth: depth of tx/rx FIFO
40 * @slot_width: width of each DAI slot
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_div: if using PSR/PM dividers for SCKx clock
43 * @slave_mode: if fully using DAI slave mode
44 * @synchronous: if using tx/rx synchronous mode
48 struct snd_dmaengine_dai_dma_data dma_params_rx;
49 struct snd_dmaengine_dai_dma_data dma_params_tx;
50 struct platform_device *pdev;
51 struct regmap *regmap;
64 static irqreturn_t esai_isr(int irq, void *devid)
66 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
67 struct platform_device *pdev = esai_priv->pdev;
70 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
72 if (esr & ESAI_ESR_TINIT_MASK)
73 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
75 if (esr & ESAI_ESR_RFF_MASK)
76 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
78 if (esr & ESAI_ESR_TFE_MASK)
79 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
81 if (esr & ESAI_ESR_TLS_MASK)
82 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
84 if (esr & ESAI_ESR_TDE_MASK)
85 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
87 if (esr & ESAI_ESR_TED_MASK)
88 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
90 if (esr & ESAI_ESR_TD_MASK)
91 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
93 if (esr & ESAI_ESR_RLS_MASK)
94 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
96 if (esr & ESAI_ESR_RDE_MASK)
97 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
99 if (esr & ESAI_ESR_RED_MASK)
100 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
102 if (esr & ESAI_ESR_RD_MASK)
103 dev_dbg(&pdev->dev, "isr: Receiving data\n");
109 * This function is used to calculate the divisors of psr, pm, fp and it is
110 * supposed to be called in set_dai_sysclk() and set_bclk().
112 * @ratio: desired overall ratio for the paticipating dividers
113 * @usefp: for HCK setting, there is no need to set fp divider
114 * @fp: bypass other dividers by setting fp directly if fp != 0
115 * @tx: current setting is for playback or capture
117 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
120 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
121 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
123 maxfp = usefp ? 16 : 1;
128 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
129 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
130 2 * 8 * 256 * maxfp);
132 } else if (ratio % 2) {
133 dev_err(dai->dev, "the raio must be even if using upper divider\n");
139 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
141 /* Set the max fluctuation -- 0.1% of the max devisor */
142 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
144 /* Find the best value for PM */
145 for (i = 1; i <= 256; i++) {
146 for (j = 1; j <= maxfp; j++) {
147 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
148 prod = (psr ? 1 : 8) * i * j;
152 else if (prod / ratio == 1)
154 else if (ratio / prod == 1)
159 /* Calculate the fraction */
160 sub = sub * 1000 / ratio;
174 dev_err(dai->dev, "failed to calculate proper divisors\n");
179 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
180 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
181 psr | ESAI_xCCR_xPM(pm));
184 /* Bypass fp if not being required */
188 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
189 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
195 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
198 * clk_id: The clock source of HCKT/HCKR
199 * (Input from outside; output from inside, FSYS or EXTAL)
200 * freq: The required clock rate of HCKT/HCKR
201 * dir: The clock direction of HCKT/HCKR
203 * Note: If the direction is input, we do not care about clk_id.
205 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
206 unsigned int freq, int dir)
208 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
209 struct clk *clksrc = esai_priv->extalclk;
210 bool tx = clk_id <= ESAI_HCKT_EXTAL;
211 bool in = dir == SND_SOC_CLOCK_IN;
212 u32 ret, ratio, ecr = 0;
213 unsigned long clk_rate;
215 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
216 esai_priv->sck_div[tx] = true;
218 /* Set the direction of HCKT/HCKR pins */
219 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
220 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
228 clksrc = esai_priv->fsysclk;
230 case ESAI_HCKT_EXTAL:
232 case ESAI_HCKR_EXTAL:
239 if (IS_ERR(clksrc)) {
240 dev_err(dai->dev, "no assigned %s clock\n",
241 clk_id % 2 ? "extal" : "fsys");
242 return PTR_ERR(clksrc);
244 clk_rate = clk_get_rate(clksrc);
246 ratio = clk_rate / freq;
247 if (ratio * freq > clk_rate)
248 ret = ratio * freq - clk_rate;
249 else if (ratio * freq < clk_rate)
250 ret = clk_rate - ratio * freq;
254 /* Block if clock source can not be divided into the required rate */
255 if (ret != 0 && clk_rate / ret < 1000) {
256 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
261 /* Only EXTAL source can be output directly without using PSR and PM */
262 if (ratio == 1 && clksrc == esai_priv->extalclk) {
263 /* Bypass all the dividers if not being needed */
264 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
266 } else if (ratio < 2) {
267 /* The ratio should be no less than 2 if using other sources */
268 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
273 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
277 esai_priv->sck_div[tx] = false;
280 esai_priv->hck_rate[tx] = freq;
282 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
283 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
284 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
290 * This function configures the related dividers according to the bclk rate
292 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
294 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
295 u32 hck_rate = esai_priv->hck_rate[tx];
296 u32 sub, ratio = hck_rate / freq;
298 /* Don't apply for fully slave mode*/
299 if (esai_priv->slave_mode)
302 if (ratio * freq > hck_rate)
303 sub = ratio * freq - hck_rate;
304 else if (ratio * freq < hck_rate)
305 sub = hck_rate - ratio * freq;
309 /* Block if clock source can not be divided into the required rate */
310 if (sub != 0 && hck_rate / sub < 1000) {
311 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
316 /* The ratio should be contented by FP alone if bypassing PM and PSR */
317 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
318 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
322 return fsl_esai_divisor_cal(dai, tx, ratio, true,
323 esai_priv->sck_div[tx] ? 0 : ratio);
326 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
327 u32 rx_mask, int slots, int slot_width)
329 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
331 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
332 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
334 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
335 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
336 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
337 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
339 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
340 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
342 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
343 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
344 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
345 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
347 esai_priv->slot_width = slot_width;
352 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
354 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
355 u32 xcr = 0, xccr = 0, mask;
358 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
359 case SND_SOC_DAIFMT_I2S:
360 /* Data on rising edge of bclk, frame low, 1clk before data */
361 xcr |= ESAI_xCR_xFSR;
362 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
364 case SND_SOC_DAIFMT_LEFT_J:
365 /* Data on rising edge of bclk, frame high */
366 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
368 case SND_SOC_DAIFMT_RIGHT_J:
369 /* Data on rising edge of bclk, frame high, right aligned */
370 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
372 case SND_SOC_DAIFMT_DSP_A:
373 /* Data on rising edge of bclk, frame high, 1clk before data */
374 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
375 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
377 case SND_SOC_DAIFMT_DSP_B:
378 /* Data on rising edge of bclk, frame high */
379 xcr |= ESAI_xCR_xFSL;
380 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
386 /* DAI clock inversion */
387 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
388 case SND_SOC_DAIFMT_NB_NF:
389 /* Nothing to do for both normal cases */
391 case SND_SOC_DAIFMT_IB_NF:
392 /* Invert bit clock */
393 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
395 case SND_SOC_DAIFMT_NB_IF:
396 /* Invert frame clock */
397 xccr ^= ESAI_xCCR_xFSP;
399 case SND_SOC_DAIFMT_IB_IF:
400 /* Invert both clocks */
401 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
407 esai_priv->slave_mode = false;
409 /* DAI clock master masks */
410 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
411 case SND_SOC_DAIFMT_CBM_CFM:
412 esai_priv->slave_mode = true;
414 case SND_SOC_DAIFMT_CBS_CFM:
415 xccr |= ESAI_xCCR_xCKD;
417 case SND_SOC_DAIFMT_CBM_CFS:
418 xccr |= ESAI_xCCR_xFSD;
420 case SND_SOC_DAIFMT_CBS_CFS:
421 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
427 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
428 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
429 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
431 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
432 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
433 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
434 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
439 static int fsl_esai_startup(struct snd_pcm_substream *substream,
440 struct snd_soc_dai *dai)
443 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
446 * Some platforms might use the same bit to gate all three or two of
447 * clocks, so keep all clocks open/close at the same time for safety
449 ret = clk_prepare_enable(esai_priv->coreclk);
452 if (!IS_ERR(esai_priv->extalclk)) {
453 ret = clk_prepare_enable(esai_priv->extalclk);
457 if (!IS_ERR(esai_priv->fsysclk)) {
458 ret = clk_prepare_enable(esai_priv->fsysclk);
464 /* Set synchronous mode */
465 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
466 ESAI_SAICR_SYNC, esai_priv->synchronous ?
467 ESAI_SAICR_SYNC : 0);
469 /* Set a default slot number -- 2 */
470 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
471 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
472 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
473 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
479 if (!IS_ERR(esai_priv->extalclk))
480 clk_disable_unprepare(esai_priv->extalclk);
482 clk_disable_unprepare(esai_priv->coreclk);
487 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
488 struct snd_pcm_hw_params *params,
489 struct snd_soc_dai *dai)
491 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
492 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
493 u32 width = snd_pcm_format_width(params_format(params));
494 u32 channels = params_channels(params);
495 u32 bclk, mask, val, ret;
497 bclk = params_rate(params) * esai_priv->slot_width * 2;
499 ret = fsl_esai_set_bclk(dai, tx, bclk);
503 /* Use Normal mode to support monaural audio */
504 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
505 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
506 ESAI_xCR_xMOD_NETWORK : 0);
508 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
509 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
511 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
512 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
513 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
514 (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels));
516 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
518 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
519 val = ESAI_xCR_xSWS(esai_priv->slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
521 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
523 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
524 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
525 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
526 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
527 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
531 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
532 struct snd_soc_dai *dai)
534 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
536 if (!IS_ERR(esai_priv->fsysclk))
537 clk_disable_unprepare(esai_priv->fsysclk);
538 if (!IS_ERR(esai_priv->extalclk))
539 clk_disable_unprepare(esai_priv->extalclk);
540 clk_disable_unprepare(esai_priv->coreclk);
543 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
544 struct snd_soc_dai *dai)
546 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
547 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
548 u8 i, channels = substream->runtime->channels;
551 case SNDRV_PCM_TRIGGER_START:
552 case SNDRV_PCM_TRIGGER_RESUME:
553 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
554 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
555 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
557 /* Write initial words reqiured by ESAI as normal procedure */
558 for (i = 0; tx && i < channels; i++)
559 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
561 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
562 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
563 tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels));
565 case SNDRV_PCM_TRIGGER_SUSPEND:
566 case SNDRV_PCM_TRIGGER_STOP:
567 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
568 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
569 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
571 /* Disable and reset FIFO */
572 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
573 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
574 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
584 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
585 .startup = fsl_esai_startup,
586 .shutdown = fsl_esai_shutdown,
587 .trigger = fsl_esai_trigger,
588 .hw_params = fsl_esai_hw_params,
589 .set_sysclk = fsl_esai_set_dai_sysclk,
590 .set_fmt = fsl_esai_set_dai_fmt,
591 .xlate_tdm_slot_mask = fsl_asoc_xlate_tdm_slot_mask,
592 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
595 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
597 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
599 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
600 &esai_priv->dma_params_rx);
605 static struct snd_soc_dai_driver fsl_esai_dai = {
606 .probe = fsl_esai_dai_probe,
610 .rates = FSL_ESAI_RATES,
611 .formats = FSL_ESAI_FORMATS,
616 .rates = FSL_ESAI_RATES,
617 .formats = FSL_ESAI_FORMATS,
619 .ops = &fsl_esai_dai_ops,
622 static const struct snd_soc_component_driver fsl_esai_component = {
626 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
658 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
689 static struct regmap_config fsl_esai_regmap_config = {
694 .max_register = REG_ESAI_PCRC,
695 .readable_reg = fsl_esai_readable_reg,
696 .writeable_reg = fsl_esai_writeable_reg,
699 static int fsl_esai_probe(struct platform_device *pdev)
701 struct device_node *np = pdev->dev.of_node;
702 struct fsl_esai *esai_priv;
703 struct resource *res;
704 const uint32_t *iprop;
708 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
712 esai_priv->pdev = pdev;
713 strcpy(esai_priv->name, np->name);
715 if (of_property_read_bool(np, "big-endian"))
716 fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
718 /* Get the addresses and IRQ */
719 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
720 regs = devm_ioremap_resource(&pdev->dev, res);
722 return PTR_ERR(regs);
724 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
725 "core", regs, &fsl_esai_regmap_config);
726 if (IS_ERR(esai_priv->regmap)) {
727 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
728 PTR_ERR(esai_priv->regmap));
729 return PTR_ERR(esai_priv->regmap);
732 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
733 if (IS_ERR(esai_priv->coreclk)) {
734 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
735 PTR_ERR(esai_priv->coreclk));
736 return PTR_ERR(esai_priv->coreclk);
739 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
740 if (IS_ERR(esai_priv->extalclk))
741 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
742 PTR_ERR(esai_priv->extalclk));
744 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
745 if (IS_ERR(esai_priv->fsysclk))
746 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
747 PTR_ERR(esai_priv->fsysclk));
749 irq = platform_get_irq(pdev, 0);
751 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
755 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
756 esai_priv->name, esai_priv);
758 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
762 /* Set a default slot size */
763 esai_priv->slot_width = 32;
765 /* Set a default master/slave state */
766 esai_priv->slave_mode = true;
768 /* Determine the FIFO depth */
769 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
771 esai_priv->fifo_depth = be32_to_cpup(iprop);
773 esai_priv->fifo_depth = 64;
775 esai_priv->dma_params_tx.maxburst = 16;
776 esai_priv->dma_params_rx.maxburst = 16;
777 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
778 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
780 esai_priv->synchronous =
781 of_property_read_bool(np, "fsl,esai-synchronous");
783 /* Implement full symmetry for synchronous mode */
784 if (esai_priv->synchronous) {
785 fsl_esai_dai.symmetric_rates = 1;
786 fsl_esai_dai.symmetric_channels = 1;
787 fsl_esai_dai.symmetric_samplebits = 1;
790 dev_set_drvdata(&pdev->dev, esai_priv);
792 /* Reset ESAI unit */
793 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
795 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
800 * We need to enable ESAI so as to access some of its registers.
801 * Otherwise, we would fail to dump regmap from user space.
803 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
805 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
809 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
812 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
816 ret = imx_pcm_dma_init(pdev);
818 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
823 static const struct of_device_id fsl_esai_dt_ids[] = {
824 { .compatible = "fsl,imx35-esai", },
827 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
829 static struct platform_driver fsl_esai_driver = {
830 .probe = fsl_esai_probe,
832 .name = "fsl-esai-dai",
833 .owner = THIS_MODULE,
834 .of_match_table = fsl_esai_dt_ids,
838 module_platform_driver(fsl_esai_driver);
840 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
841 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
842 MODULE_LICENSE("GPL v2");
843 MODULE_ALIAS("platform:fsl-esai-dai");