2 * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/clk.h>
12 #include <linux/dmaengine.h>
13 #include <linux/module.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <sound/dmaengine_pcm.h>
17 #include <sound/pcm_params.h>
22 #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000
23 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
24 SNDRV_PCM_FMTBIT_S16_LE | \
25 SNDRV_PCM_FMTBIT_S20_3LE | \
26 SNDRV_PCM_FMTBIT_S24_LE)
29 * fsl_esai: ESAI private data
31 * @dma_params_rx: DMA parameters for receive channel
32 * @dma_params_tx: DMA parameters for transmit channel
33 * @pdev: platform device pointer
34 * @regmap: regmap handler
35 * @coreclk: clock source to access register
36 * @extalclk: esai clock source to derive HCK, SCK and FS
37 * @fsysclk: system clock source to derive HCK, SCK and FS
38 * @fifo_depth: depth of tx/rx FIFO
39 * @slot_width: width of each DAI slot
40 * @slots: number of slots
41 * @hck_rate: clock rate of desired HCKx clock
42 * @sck_rate: clock rate of desired SCKx clock
43 * @hck_dir: the direction of HCKx pads
44 * @sck_div: if using PSR/PM dividers for SCKx clock
45 * @slave_mode: if fully using DAI slave mode
46 * @synchronous: if using tx/rx synchronous mode
50 struct snd_dmaengine_dai_dma_data dma_params_rx;
51 struct snd_dmaengine_dai_dma_data dma_params_tx;
52 struct platform_device *pdev;
53 struct regmap *regmap;
69 static irqreturn_t esai_isr(int irq, void *devid)
71 struct fsl_esai *esai_priv = (struct fsl_esai *)devid;
72 struct platform_device *pdev = esai_priv->pdev;
75 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr);
77 if (esr & ESAI_ESR_TINIT_MASK)
78 dev_dbg(&pdev->dev, "isr: Transmition Initialized\n");
80 if (esr & ESAI_ESR_RFF_MASK)
81 dev_warn(&pdev->dev, "isr: Receiving overrun\n");
83 if (esr & ESAI_ESR_TFE_MASK)
84 dev_warn(&pdev->dev, "isr: Transmition underrun\n");
86 if (esr & ESAI_ESR_TLS_MASK)
87 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n");
89 if (esr & ESAI_ESR_TDE_MASK)
90 dev_dbg(&pdev->dev, "isr: Transmition data exception\n");
92 if (esr & ESAI_ESR_TED_MASK)
93 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n");
95 if (esr & ESAI_ESR_TD_MASK)
96 dev_dbg(&pdev->dev, "isr: Transmitting data\n");
98 if (esr & ESAI_ESR_RLS_MASK)
99 dev_dbg(&pdev->dev, "isr: Just received the last slot\n");
101 if (esr & ESAI_ESR_RDE_MASK)
102 dev_dbg(&pdev->dev, "isr: Receiving data exception\n");
104 if (esr & ESAI_ESR_RED_MASK)
105 dev_dbg(&pdev->dev, "isr: Receiving even slots\n");
107 if (esr & ESAI_ESR_RD_MASK)
108 dev_dbg(&pdev->dev, "isr: Receiving data\n");
114 * This function is used to calculate the divisors of psr, pm, fp and it is
115 * supposed to be called in set_dai_sysclk() and set_bclk().
117 * @ratio: desired overall ratio for the paticipating dividers
118 * @usefp: for HCK setting, there is no need to set fp divider
119 * @fp: bypass other dividers by setting fp directly if fp != 0
120 * @tx: current setting is for playback or capture
122 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
125 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
126 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;
128 maxfp = usefp ? 16 : 1;
133 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) {
134 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n",
135 2 * 8 * 256 * maxfp);
137 } else if (ratio % 2) {
138 dev_err(dai->dev, "the raio must be even if using upper divider\n");
144 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;
146 /* Set the max fluctuation -- 0.1% of the max devisor */
147 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;
149 /* Find the best value for PM */
150 for (i = 1; i <= 256; i++) {
151 for (j = 1; j <= maxfp; j++) {
152 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */
153 prod = (psr ? 1 : 8) * i * j;
157 else if (prod / ratio == 1)
159 else if (ratio / prod == 1)
164 /* Calculate the fraction */
165 sub = sub * 1000 / ratio;
179 dev_err(dai->dev, "failed to calculate proper divisors\n");
184 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
185 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK,
186 psr | ESAI_xCCR_xPM(pm));
189 /* Bypass fp if not being required */
193 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
194 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp));
200 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
203 * clk_id: The clock source of HCKT/HCKR
204 * (Input from outside; output from inside, FSYS or EXTAL)
205 * freq: The required clock rate of HCKT/HCKR
206 * dir: The clock direction of HCKT/HCKR
208 * Note: If the direction is input, we do not care about clk_id.
210 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
211 unsigned int freq, int dir)
213 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
214 struct clk *clksrc = esai_priv->extalclk;
215 bool tx = clk_id <= ESAI_HCKT_EXTAL;
216 bool in = dir == SND_SOC_CLOCK_IN;
218 unsigned long clk_rate;
221 /* Bypass divider settings if the requirement doesn't change */
222 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
225 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
226 esai_priv->sck_div[tx] = true;
228 /* Set the direction of HCKT/HCKR pins */
229 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx),
230 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD);
238 clksrc = esai_priv->fsysclk;
240 case ESAI_HCKT_EXTAL:
242 case ESAI_HCKR_EXTAL:
249 if (IS_ERR(clksrc)) {
250 dev_err(dai->dev, "no assigned %s clock\n",
251 clk_id % 2 ? "extal" : "fsys");
252 return PTR_ERR(clksrc);
254 clk_rate = clk_get_rate(clksrc);
256 ratio = clk_rate / freq;
257 if (ratio * freq > clk_rate)
258 ret = ratio * freq - clk_rate;
259 else if (ratio * freq < clk_rate)
260 ret = clk_rate - ratio * freq;
264 /* Block if clock source can not be divided into the required rate */
265 if (ret != 0 && clk_rate / ret < 1000) {
266 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
271 /* Only EXTAL source can be output directly without using PSR and PM */
272 if (ratio == 1 && clksrc == esai_priv->extalclk) {
273 /* Bypass all the dividers if not being needed */
274 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
276 } else if (ratio < 2) {
277 /* The ratio should be no less than 2 if using other sources */
278 dev_err(dai->dev, "failed to derive required HCK%c rate\n",
283 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
287 esai_priv->sck_div[tx] = false;
290 esai_priv->hck_dir[tx] = dir;
291 esai_priv->hck_rate[tx] = freq;
293 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
294 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO :
295 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr);
301 * This function configures the related dividers according to the bclk rate
303 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
305 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
306 u32 hck_rate = esai_priv->hck_rate[tx];
307 u32 sub, ratio = hck_rate / freq;
310 /* Don't apply for fully slave mode or unchanged bclk */
311 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
314 if (ratio * freq > hck_rate)
315 sub = ratio * freq - hck_rate;
316 else if (ratio * freq < hck_rate)
317 sub = hck_rate - ratio * freq;
321 /* Block if clock source can not be divided into the required rate */
322 if (sub != 0 && hck_rate / sub < 1000) {
323 dev_err(dai->dev, "failed to derive required SCK%c rate\n",
328 /* The ratio should be contented by FP alone if bypassing PM and PSR */
329 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
330 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
334 ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
335 esai_priv->sck_div[tx] ? 0 : ratio);
339 /* Save current bclk rate */
340 esai_priv->sck_rate[tx] = freq;
345 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
346 u32 rx_mask, int slots, int slot_width)
348 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
350 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
351 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
353 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
354 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
355 regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
356 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
358 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
359 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
361 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
362 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
363 regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
364 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
366 esai_priv->slot_width = slot_width;
367 esai_priv->slots = slots;
372 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
374 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
375 u32 xcr = 0, xccr = 0, mask;
378 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
379 case SND_SOC_DAIFMT_I2S:
380 /* Data on rising edge of bclk, frame low, 1clk before data */
381 xcr |= ESAI_xCR_xFSR;
382 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
384 case SND_SOC_DAIFMT_LEFT_J:
385 /* Data on rising edge of bclk, frame high */
386 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
388 case SND_SOC_DAIFMT_RIGHT_J:
389 /* Data on rising edge of bclk, frame high, right aligned */
390 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA;
392 case SND_SOC_DAIFMT_DSP_A:
393 /* Data on rising edge of bclk, frame high, 1clk before data */
394 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR;
395 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
397 case SND_SOC_DAIFMT_DSP_B:
398 /* Data on rising edge of bclk, frame high */
399 xcr |= ESAI_xCR_xFSL;
400 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
406 /* DAI clock inversion */
407 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
408 case SND_SOC_DAIFMT_NB_NF:
409 /* Nothing to do for both normal cases */
411 case SND_SOC_DAIFMT_IB_NF:
412 /* Invert bit clock */
413 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP;
415 case SND_SOC_DAIFMT_NB_IF:
416 /* Invert frame clock */
417 xccr ^= ESAI_xCCR_xFSP;
419 case SND_SOC_DAIFMT_IB_IF:
420 /* Invert both clocks */
421 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP;
427 esai_priv->slave_mode = false;
429 /* DAI clock master masks */
430 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
431 case SND_SOC_DAIFMT_CBM_CFM:
432 esai_priv->slave_mode = true;
434 case SND_SOC_DAIFMT_CBS_CFM:
435 xccr |= ESAI_xCCR_xCKD;
437 case SND_SOC_DAIFMT_CBM_CFS:
438 xccr |= ESAI_xCCR_xFSD;
440 case SND_SOC_DAIFMT_CBS_CFS:
441 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD;
447 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR;
448 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr);
449 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr);
451 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP |
452 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA;
453 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr);
454 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr);
459 static int fsl_esai_startup(struct snd_pcm_substream *substream,
460 struct snd_soc_dai *dai)
462 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
466 * Some platforms might use the same bit to gate all three or two of
467 * clocks, so keep all clocks open/close at the same time for safety
469 ret = clk_prepare_enable(esai_priv->coreclk);
472 if (!IS_ERR(esai_priv->extalclk)) {
473 ret = clk_prepare_enable(esai_priv->extalclk);
477 if (!IS_ERR(esai_priv->fsysclk)) {
478 ret = clk_prepare_enable(esai_priv->fsysclk);
484 /* Set synchronous mode */
485 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
486 ESAI_SAICR_SYNC, esai_priv->synchronous ?
487 ESAI_SAICR_SYNC : 0);
489 /* Set a default slot number -- 2 */
490 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
491 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
492 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
493 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
499 if (!IS_ERR(esai_priv->extalclk))
500 clk_disable_unprepare(esai_priv->extalclk);
502 clk_disable_unprepare(esai_priv->coreclk);
507 static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
508 struct snd_pcm_hw_params *params,
509 struct snd_soc_dai *dai)
511 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
512 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
513 u32 width = snd_pcm_format_width(params_format(params));
514 u32 channels = params_channels(params);
515 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
516 u32 slot_width = width;
520 /* Override slot_width if being specifically set */
521 if (esai_priv->slot_width)
522 slot_width = esai_priv->slot_width;
524 bclk = params_rate(params) * slot_width * esai_priv->slots;
526 ret = fsl_esai_set_bclk(dai, tx, bclk);
530 /* Use Normal mode to support monaural audio */
531 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
532 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
533 ESAI_xCR_xMOD_NETWORK : 0);
535 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
536 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
538 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
539 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
540 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
541 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
543 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
545 mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0);
546 val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0);
548 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
550 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
551 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
552 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
553 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
554 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
558 static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
559 struct snd_soc_dai *dai)
561 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
563 if (!IS_ERR(esai_priv->fsysclk))
564 clk_disable_unprepare(esai_priv->fsysclk);
565 if (!IS_ERR(esai_priv->extalclk))
566 clk_disable_unprepare(esai_priv->extalclk);
567 clk_disable_unprepare(esai_priv->coreclk);
570 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
571 struct snd_soc_dai *dai)
573 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
574 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
575 u8 i, channels = substream->runtime->channels;
576 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
579 case SNDRV_PCM_TRIGGER_START:
580 case SNDRV_PCM_TRIGGER_RESUME:
581 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
582 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
583 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN);
585 /* Write initial words reqiured by ESAI as normal procedure */
586 for (i = 0; tx && i < channels; i++)
587 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0);
589 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
590 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
591 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
593 case SNDRV_PCM_TRIGGER_SUSPEND:
594 case SNDRV_PCM_TRIGGER_STOP:
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
596 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
597 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
599 /* Disable and reset FIFO */
600 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
601 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR);
602 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
612 static struct snd_soc_dai_ops fsl_esai_dai_ops = {
613 .startup = fsl_esai_startup,
614 .shutdown = fsl_esai_shutdown,
615 .trigger = fsl_esai_trigger,
616 .hw_params = fsl_esai_hw_params,
617 .set_sysclk = fsl_esai_set_dai_sysclk,
618 .set_fmt = fsl_esai_set_dai_fmt,
619 .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
622 static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
624 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
626 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx,
627 &esai_priv->dma_params_rx);
632 static struct snd_soc_dai_driver fsl_esai_dai = {
633 .probe = fsl_esai_dai_probe,
635 .stream_name = "CPU-Playback",
638 .rates = FSL_ESAI_RATES,
639 .formats = FSL_ESAI_FORMATS,
642 .stream_name = "CPU-Capture",
645 .rates = FSL_ESAI_RATES,
646 .formats = FSL_ESAI_FORMATS,
648 .ops = &fsl_esai_dai_ops,
651 static const struct snd_soc_component_driver fsl_esai_component = {
655 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg)
687 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
718 static const struct regmap_config fsl_esai_regmap_config = {
723 .max_register = REG_ESAI_PCRC,
724 .readable_reg = fsl_esai_readable_reg,
725 .writeable_reg = fsl_esai_writeable_reg,
728 static int fsl_esai_probe(struct platform_device *pdev)
730 struct device_node *np = pdev->dev.of_node;
731 struct fsl_esai *esai_priv;
732 struct resource *res;
733 const uint32_t *iprop;
737 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL);
741 esai_priv->pdev = pdev;
742 strncpy(esai_priv->name, np->name, sizeof(esai_priv->name) - 1);
744 /* Get the addresses and IRQ */
745 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
746 regs = devm_ioremap_resource(&pdev->dev, res);
748 return PTR_ERR(regs);
750 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
751 "core", regs, &fsl_esai_regmap_config);
752 if (IS_ERR(esai_priv->regmap)) {
753 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
754 PTR_ERR(esai_priv->regmap));
755 return PTR_ERR(esai_priv->regmap);
758 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core");
759 if (IS_ERR(esai_priv->coreclk)) {
760 dev_err(&pdev->dev, "failed to get core clock: %ld\n",
761 PTR_ERR(esai_priv->coreclk));
762 return PTR_ERR(esai_priv->coreclk);
765 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal");
766 if (IS_ERR(esai_priv->extalclk))
767 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n",
768 PTR_ERR(esai_priv->extalclk));
770 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys");
771 if (IS_ERR(esai_priv->fsysclk))
772 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
773 PTR_ERR(esai_priv->fsysclk));
775 irq = platform_get_irq(pdev, 0);
777 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
781 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0,
782 esai_priv->name, esai_priv);
784 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
788 /* Set a default slot number */
789 esai_priv->slots = 2;
791 /* Set a default master/slave state */
792 esai_priv->slave_mode = true;
794 /* Determine the FIFO depth */
795 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
797 esai_priv->fifo_depth = be32_to_cpup(iprop);
799 esai_priv->fifo_depth = 64;
801 esai_priv->dma_params_tx.maxburst = 16;
802 esai_priv->dma_params_rx.maxburst = 16;
803 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
804 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
806 esai_priv->synchronous =
807 of_property_read_bool(np, "fsl,esai-synchronous");
809 /* Implement full symmetry for synchronous mode */
810 if (esai_priv->synchronous) {
811 fsl_esai_dai.symmetric_rates = 1;
812 fsl_esai_dai.symmetric_channels = 1;
813 fsl_esai_dai.symmetric_samplebits = 1;
816 dev_set_drvdata(&pdev->dev, esai_priv);
818 /* Reset ESAI unit */
819 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST);
821 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret);
826 * We need to enable ESAI so as to access some of its registers.
827 * Otherwise, we would fail to dump regmap from user space.
829 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN);
831 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret);
835 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component,
838 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
842 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
844 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
849 static const struct of_device_id fsl_esai_dt_ids[] = {
850 { .compatible = "fsl,imx35-esai", },
851 { .compatible = "fsl,vf610-esai", },
854 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
856 static struct platform_driver fsl_esai_driver = {
857 .probe = fsl_esai_probe,
859 .name = "fsl-esai-dai",
860 .of_match_table = fsl_esai_dt_ids,
864 module_platform_driver(fsl_esai_driver);
866 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
867 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver");
868 MODULE_LICENSE("GPL v2");
869 MODULE_ALIAS("platform:fsl-esai-dai");