2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
26 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
27 int clk_id, unsigned int freq, int fsl_dir)
29 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
32 if (fsl_dir == FSL_FMT_TRANSMITTER)
33 reg_cr2 = FSL_SAI_TCR2;
35 reg_cr2 = FSL_SAI_RCR2;
37 regmap_read(sai->regmap, reg_cr2, &val_cr2);
39 val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
43 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
45 case FSL_SAI_CLK_MAST1:
46 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
48 case FSL_SAI_CLK_MAST2:
49 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
51 case FSL_SAI_CLK_MAST3:
52 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
58 regmap_write(sai->regmap, reg_cr2, val_cr2);
63 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
64 int clk_id, unsigned int freq, int dir)
68 if (dir == SND_SOC_CLOCK_IN)
71 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
74 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
78 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
81 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
86 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
87 unsigned int fmt, int fsl_dir)
89 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
90 u32 val_cr2, val_cr4, reg_cr2, reg_cr4;
92 if (fsl_dir == FSL_FMT_TRANSMITTER) {
93 reg_cr2 = FSL_SAI_TCR2;
94 reg_cr4 = FSL_SAI_TCR4;
96 reg_cr2 = FSL_SAI_RCR2;
97 reg_cr4 = FSL_SAI_RCR4;
100 regmap_read(sai->regmap, reg_cr2, &val_cr2);
101 regmap_read(sai->regmap, reg_cr4, &val_cr4);
103 if (sai->big_endian_data)
104 val_cr4 &= ~FSL_SAI_CR4_MF;
106 val_cr4 |= FSL_SAI_CR4_MF;
109 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
110 case SND_SOC_DAIFMT_I2S:
112 * Frame low, 1clk before data, one word length for frame sync,
113 * frame sync starts one serial clock cycle earlier,
114 * that is, together with the last bit of the previous
117 val_cr2 &= ~FSL_SAI_CR2_BCP;
118 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
120 case SND_SOC_DAIFMT_LEFT_J:
122 * Frame high, one word length for frame sync,
123 * frame sync asserts with the first bit of the frame.
125 val_cr2 &= ~FSL_SAI_CR2_BCP;
126 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
128 case SND_SOC_DAIFMT_DSP_A:
130 * Frame high, 1clk before data, one bit for frame sync,
131 * frame sync starts one serial clock cycle earlier,
132 * that is, together with the last bit of the previous
135 val_cr2 &= ~FSL_SAI_CR2_BCP;
136 val_cr4 &= ~FSL_SAI_CR4_FSP;
137 val_cr4 |= FSL_SAI_CR4_FSE;
138 sai->is_dsp_mode = true;
140 case SND_SOC_DAIFMT_DSP_B:
142 * Frame high, one bit for frame sync,
143 * frame sync asserts with the first bit of the frame.
145 val_cr2 &= ~FSL_SAI_CR2_BCP;
146 val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
147 sai->is_dsp_mode = true;
149 case SND_SOC_DAIFMT_RIGHT_J:
155 /* DAI clock inversion */
156 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
157 case SND_SOC_DAIFMT_IB_IF:
158 /* Invert both clocks */
159 val_cr2 ^= FSL_SAI_CR2_BCP;
160 val_cr4 ^= FSL_SAI_CR4_FSP;
162 case SND_SOC_DAIFMT_IB_NF:
163 /* Invert bit clock */
164 val_cr2 ^= FSL_SAI_CR2_BCP;
166 case SND_SOC_DAIFMT_NB_IF:
167 /* Invert frame clock */
168 val_cr4 ^= FSL_SAI_CR4_FSP;
170 case SND_SOC_DAIFMT_NB_NF:
171 /* Nothing to do for both normal cases */
177 /* DAI clock master masks */
178 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
179 case SND_SOC_DAIFMT_CBS_CFS:
180 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
181 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
183 case SND_SOC_DAIFMT_CBM_CFM:
184 val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
185 val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
187 case SND_SOC_DAIFMT_CBS_CFM:
188 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
189 val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
191 case SND_SOC_DAIFMT_CBM_CFS:
192 val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
193 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
199 regmap_write(sai->regmap, reg_cr2, val_cr2);
200 regmap_write(sai->regmap, reg_cr4, val_cr4);
205 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
209 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
211 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
215 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
217 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
222 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
223 struct snd_pcm_hw_params *params,
224 struct snd_soc_dai *cpu_dai)
226 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
227 u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr;
228 unsigned int channels = params_channels(params);
229 u32 word_width = snd_pcm_format_width(params_format(params));
231 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
232 reg_cr4 = FSL_SAI_TCR4;
233 reg_cr5 = FSL_SAI_TCR5;
234 reg_mr = FSL_SAI_TMR;
236 reg_cr4 = FSL_SAI_RCR4;
237 reg_cr5 = FSL_SAI_RCR5;
238 reg_mr = FSL_SAI_RMR;
241 regmap_read(sai->regmap, reg_cr4, &val_cr4);
242 regmap_read(sai->regmap, reg_cr4, &val_cr5);
244 val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
245 val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;
247 val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
248 val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
249 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
251 if (!sai->is_dsp_mode)
252 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
254 val_cr5 |= FSL_SAI_CR5_WNW(word_width);
255 val_cr5 |= FSL_SAI_CR5_W0W(word_width);
257 val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
258 if (sai->big_endian_data)
259 val_cr5 |= FSL_SAI_CR5_FBT(0);
261 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
263 val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
264 val_mr = ~0UL - ((1 << channels) - 1);
266 regmap_write(sai->regmap, reg_cr4, val_cr4);
267 regmap_write(sai->regmap, reg_cr5, val_cr5);
268 regmap_write(sai->regmap, reg_mr, val_mr);
273 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
274 struct snd_soc_dai *cpu_dai)
276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
280 * The transmitter bit clock and frame sync are to be
281 * used by both the transmitter and receiver.
283 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
285 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
288 regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
289 regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);
291 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
292 tcsr |= FSL_SAI_CSR_FRDE;
293 rcsr &= ~FSL_SAI_CSR_FRDE;
295 rcsr |= FSL_SAI_CSR_FRDE;
296 tcsr &= ~FSL_SAI_CSR_FRDE;
300 * It is recommended that the transmitter is the last enabled
301 * and the first disabled.
304 case SNDRV_PCM_TRIGGER_START:
305 case SNDRV_PCM_TRIGGER_RESUME:
306 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
307 tcsr |= FSL_SAI_CSR_TERE;
308 rcsr |= FSL_SAI_CSR_TERE;
310 regmap_write(sai->regmap, FSL_SAI_RCSR, rcsr);
311 regmap_write(sai->regmap, FSL_SAI_TCSR, tcsr);
313 case SNDRV_PCM_TRIGGER_STOP:
314 case SNDRV_PCM_TRIGGER_SUSPEND:
315 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
316 if (!(cpu_dai->playback_active || cpu_dai->capture_active)) {
317 tcsr &= ~FSL_SAI_CSR_TERE;
318 rcsr &= ~FSL_SAI_CSR_TERE;
321 regmap_write(sai->regmap, FSL_SAI_TCSR, tcsr);
322 regmap_write(sai->regmap, FSL_SAI_RCSR, rcsr);
331 static int fsl_sai_startup(struct snd_pcm_substream *substream,
332 struct snd_soc_dai *cpu_dai)
334 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
337 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
342 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
348 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
349 struct snd_soc_dai *cpu_dai)
351 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
359 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
363 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
364 .set_sysclk = fsl_sai_set_dai_sysclk,
365 .set_fmt = fsl_sai_set_dai_fmt,
366 .hw_params = fsl_sai_hw_params,
367 .trigger = fsl_sai_trigger,
368 .startup = fsl_sai_startup,
369 .shutdown = fsl_sai_shutdown,
372 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
374 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
376 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
377 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
378 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
379 FSL_SAI_MAXBURST_TX * 2);
380 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
381 FSL_SAI_MAXBURST_RX - 1);
383 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
384 &sai->dma_params_rx);
386 snd_soc_dai_set_drvdata(cpu_dai, sai);
391 static struct snd_soc_dai_driver fsl_sai_dai = {
392 .probe = fsl_sai_dai_probe,
396 .rates = SNDRV_PCM_RATE_8000_96000,
397 .formats = FSL_SAI_FORMATS,
402 .rates = SNDRV_PCM_RATE_8000_96000,
403 .formats = FSL_SAI_FORMATS,
405 .ops = &fsl_sai_pcm_dai_ops,
408 static const struct snd_soc_component_driver fsl_component = {
412 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
438 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
452 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
476 static struct regmap_config fsl_sai_regmap_config = {
481 .max_register = FSL_SAI_RMR,
482 .readable_reg = fsl_sai_readable_reg,
483 .volatile_reg = fsl_sai_volatile_reg,
484 .writeable_reg = fsl_sai_writeable_reg,
487 static int fsl_sai_probe(struct platform_device *pdev)
489 struct device_node *np = pdev->dev.of_node;
491 struct resource *res;
495 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
499 sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
500 if (sai->big_endian_regs)
501 fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
503 sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
506 base = devm_ioremap_resource(&pdev->dev, res);
508 return PTR_ERR(base);
510 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
511 "sai", base, &fsl_sai_regmap_config);
512 if (IS_ERR(sai->regmap)) {
513 dev_err(&pdev->dev, "regmap init failed\n");
514 return PTR_ERR(sai->regmap);
517 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
518 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
519 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
520 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
522 platform_set_drvdata(pdev, sai);
524 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
529 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
530 SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
533 static const struct of_device_id fsl_sai_ids[] = {
534 { .compatible = "fsl,vf610-sai", },
538 static struct platform_driver fsl_sai_driver = {
539 .probe = fsl_sai_probe,
542 .owner = THIS_MODULE,
543 .of_match_table = fsl_sai_ids,
546 module_platform_driver(fsl_sai_driver);
548 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
549 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
550 MODULE_ALIAS("platform:fsl-sai");
551 MODULE_LICENSE("GPL");