2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright (C) 2007-2014 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <linux/busfreq-imx6.h>
14 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/clk.h>
19 #include <linux/device.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/pm_runtime.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
32 #include <sound/dmaengine_pcm.h>
38 #define read_ssi(addr) in_be32(addr)
39 #define write_ssi(val, addr) out_be32(addr, val)
40 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
42 #define read_ssi(addr) readl(addr)
43 #define write_ssi(val, addr) writel(val, addr)
45 * FIXME: Proper locking should be added at write_ssi_mask caller level
46 * to ensure this register read/modify/write sequence is race free.
48 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
50 u32 val = readl(addr);
51 val = (val & ~clear) | set;
57 #define NUM_OF_SSI_REG (sizeof(struct ccsr_ssi) / sizeof(__be32))
59 void dump_reg(struct ccsr_ssi __iomem *ssi)
63 for (i = 0; i < NUM_OF_SSI_REG; i++) {
64 if (&ssi->stx0 + i == NULL)
66 val = read_ssi(&ssi->stx0 + i);
67 pr_debug("REG %x = %x\n", (u32)(&ssi->stx0 + i) & 0xff, val);
71 void dump_reg(struct ccsr_ssi __iomem *ssi) {}
75 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * This driver currently only supports the SSI running in I2S slave mode,
78 * which means the codec determines the sample rate. Therefore, we tell
79 * ALSA that we support all rates and let the codec driver decide what rates
80 * are really supported.
82 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 /* SIER bitflag of interrupts to enable */
110 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TIE | \
111 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TUE1_EN | \
112 CCSR_SSI_SIER_RFRC_EN | CCSR_SSI_SIER_RIE | \
113 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
116 * fsl_ssi_private: per-SSI private data
118 * @ssi: pointer to the SSI's registers
119 * @ssi_phys: physical address of the SSI registers
120 * @irq: IRQ of this SSI
121 * @playback: the number of playback streams opened
122 * @capture: the number of capture streams opened
123 * @cpu_dai: the CPU DAI for this device
124 * @dev_attr: the sysfs device attribute structure
125 * @stats: SSI statistics
126 * @name: name for this device
128 struct fsl_ssi_private {
129 struct ccsr_ssi __iomem *ssi;
132 unsigned int fifo_depth;
133 struct snd_soc_dai_driver cpu_dai_drv;
134 struct device_attribute dev_attr;
135 struct platform_device *pdev;
137 unsigned long sysrate;
144 struct snd_dmaengine_dai_dma_data dma_params_tx;
145 struct snd_dmaengine_dai_dma_data dma_params_rx;
175 * fsl_ssi_isr: SSI interrupt handler
177 * Although it's possible to use the interrupt handler to send and receive
178 * data to/from the SSI, we use the DMA instead. Programming is more
179 * complicated, but the performance is much better.
181 * This interrupt handler is used only to gather statistics.
183 * @irq: IRQ of the SSI device
184 * @dev_id: pointer to the ssi_private structure for this SSI device
186 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
188 struct fsl_ssi_private *ssi_private = dev_id;
189 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
190 irqreturn_t ret = IRQ_NONE;
194 /* We got an interrupt, so read the status register to see what we
195 were interrupted for. We mask it with the Interrupt Enable register
196 so that we only check for events that we're interested in.
198 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
200 if (sisr & CCSR_SSI_SISR_RFRC) {
201 ssi_private->stats.rfrc++;
202 sisr2 |= CCSR_SSI_SISR_RFRC;
206 if (sisr & CCSR_SSI_SISR_TFRC) {
207 ssi_private->stats.tfrc++;
208 sisr2 |= CCSR_SSI_SISR_TFRC;
212 if (sisr & CCSR_SSI_SISR_CMDAU) {
213 ssi_private->stats.cmdau++;
217 if (sisr & CCSR_SSI_SISR_CMDDU) {
218 ssi_private->stats.cmddu++;
222 if (sisr & CCSR_SSI_SISR_RXT) {
223 ssi_private->stats.rxt++;
227 if (sisr & CCSR_SSI_SISR_RDR1) {
228 ssi_private->stats.rdr1++;
232 if (sisr & CCSR_SSI_SISR_RDR0) {
233 ssi_private->stats.rdr0++;
237 if (sisr & CCSR_SSI_SISR_TDE1) {
238 ssi_private->stats.tde1++;
242 if (sisr & CCSR_SSI_SISR_TDE0) {
243 ssi_private->stats.tde0++;
247 if (sisr & CCSR_SSI_SISR_ROE1) {
248 ssi_private->stats.roe1++;
249 sisr2 |= CCSR_SSI_SISR_ROE1;
253 if (sisr & CCSR_SSI_SISR_ROE0) {
254 ssi_private->stats.roe0++;
255 sisr2 |= CCSR_SSI_SISR_ROE0;
259 if (sisr & CCSR_SSI_SISR_TUE1) {
260 ssi_private->stats.tue1++;
261 sisr2 |= CCSR_SSI_SISR_TUE1;
265 if (sisr & CCSR_SSI_SISR_TUE0) {
266 ssi_private->stats.tue0++;
267 sisr2 |= CCSR_SSI_SISR_TUE0;
271 if (sisr & CCSR_SSI_SISR_TFS) {
272 ssi_private->stats.tfs++;
276 if (sisr & CCSR_SSI_SISR_RFS) {
277 ssi_private->stats.rfs++;
281 if (sisr & CCSR_SSI_SISR_TLS) {
282 ssi_private->stats.tls++;
286 if (sisr & CCSR_SSI_SISR_RLS) {
287 ssi_private->stats.rls++;
291 if (sisr & CCSR_SSI_SISR_RFF1) {
292 ssi_private->stats.rff1++;
296 if (sisr & CCSR_SSI_SISR_RFF0) {
297 ssi_private->stats.rff0++;
301 if (sisr & CCSR_SSI_SISR_TFE1) {
302 ssi_private->stats.tfe1++;
306 if (sisr & CCSR_SSI_SISR_TFE0) {
307 ssi_private->stats.tfe0++;
311 /* Clear the bits that we set */
313 write_ssi(sisr2, &ssi->sisr);
319 * fsl_ssi_startup: create a new substream
321 * This is the first function called when a stream is opened.
323 * If this is the first stream open, then grab the IRQ and program most of
326 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
327 struct snd_soc_dai *dai)
329 struct snd_soc_pcm_runtime *rtd = substream->private_data;
330 struct fsl_ssi_private *ssi_private =
331 snd_soc_dai_get_drvdata(rtd->cpu_dai);
332 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
334 if (ssi_private->ssi_on_imx) {
335 pm_runtime_get_sync(dai->dev);
337 clk_prepare_enable(ssi_private->coreclk);
338 clk_prepare_enable(ssi_private->clk);
340 /* When using dual fifo mode, it would be safer if we ensure
341 * its period size to be an even number. If appearing to an
342 * odd number, the 2nd fifo might be neglected by SDMA sciprt
343 * at the end of each period.
345 if (ssi_private->use_dual_fifo)
346 snd_pcm_hw_constraint_step(substream->runtime, 0,
347 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
351 * If this is the first stream opened, then request the IRQ
352 * and initialize the SSI registers.
355 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
358 * Section 16.5 of the MPC8610 reference manual says that the
359 * SSI needs to be disabled before updating the registers we set
362 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
365 * Program the SSI into I2S Slave Non-Network Synchronous mode.
366 * Also enable the transmit and receive FIFO.
368 * FIXME: Little-endian samples require a different shift dir
370 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
371 write_ssi_mask(&ssi->scr,
372 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
373 CCSR_SSI_SCR_TFR_CLK_DIS | ssi_private->i2s_mode
374 | (synchronous ? CCSR_SSI_SCR_SYN : 0));
376 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
377 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
378 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
380 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
381 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
382 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
385 * The DC and PM bits are only used if the SSI is the clock
389 /* Enable the interrupts and DMA requests */
390 write_ssi(SIER_FLAGS, &ssi->sier);
393 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We
394 * don't use FIFO 1. We program the transmit water to signal a
395 * DMA transfer if there are only two (or fewer) elements left
396 * in the FIFO. Two elements equals one frame (left channel,
397 * right channel). This value, however, depends on the depth of
398 * the transmit buffer.
400 * We program the receive FIFO to notify us if at least two
401 * elements (one frame) have been written to the FIFO. We could
402 * make this value larger (and maybe we should), but this way
403 * data will be written to memory as soon as it's available.
405 write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
406 CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2) |
407 CCSR_SSI_SFCSR_TFWM1(ssi_private->fifo_depth - 2) |
408 CCSR_SSI_SFCSR_RFWM1(ssi_private->fifo_depth - 2),
411 /* Select Single/Dual fifo mode */
412 if (ssi_private->use_dual_fifo) {
413 write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
414 write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
415 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
417 write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, 0);
418 write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, 0);
419 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, 0);
423 * We keep the SSI disabled because if we enable it, then the
424 * DMA controller will start. It's not supposed to start until
425 * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The
426 * DMA controller will transfer one "BWC" of data (i.e. the
427 * amount of data that the MR.BWC bits are set to). The reason
428 * this is bad is because at this point, the PCM driver has not
429 * finished initializing the DMA controller.
437 * fsl_ssi_hw_params - program the sample size
439 * Most of the SSI registers have been programmed in the startup function,
440 * but the word length must be programmed here. Unfortunately, programming
441 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
442 * cause a problem with supporting simultaneous playback and capture. If
443 * the SSI is already playing a stream, then that stream may be temporarily
444 * stopped when you start capture.
446 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
449 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
450 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
452 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
453 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
454 unsigned int sample_size =
455 snd_pcm_format_width(params_format(hw_params));
456 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
457 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
458 unsigned int channels = params_channels(hw_params);
462 * If we're in synchronous mode, and the SSI is already enabled,
463 * then STCCR is already set properly.
465 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
468 if (ssi_private->sysrate) {
469 ret = clk_set_rate(ssi_private->clk, ssi_private->sysrate);
471 dev_err(cpu_dai->dev, "failed to set clock rate\n");
477 * FIXME: The documentation says that SxCCR[WL] should not be
478 * modified while the SSI is enabled. The only time this can
479 * happen is if we're trying to do simultaneous playback and
480 * capture in asynchronous mode. Unfortunately, I have been enable
481 * to get that to work at all on the P1022DS. Therefore, we don't
482 * bother to disable/enable the SSI when setting SxCCR[WL], because
483 * the SSI will stop anyway. Maybe one day, this will get fixed.
486 /* In synchronous mode, the SSI uses STCCR for capture */
487 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
488 ssi_private->cpu_dai_drv.symmetric_rates)
489 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
491 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
493 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
494 channels == 1 ? 0 : ssi_private->i2s_mode);
500 * fsl_ssi_trigger: start and stop the DMA transfer.
502 * This function is called by ALSA to start, stop, pause, and resume the DMA
505 * The DMA channel is in external master start and pause mode, which
506 * means the SSI completely controls the flow of data.
508 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
509 struct snd_soc_dai *dai)
511 struct snd_soc_pcm_runtime *rtd = substream->private_data;
512 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
513 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
516 case SNDRV_PCM_TRIGGER_START:
517 case SNDRV_PCM_TRIGGER_RESUME:
518 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
519 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
520 write_ssi_mask(&ssi->scr, 0,
521 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
522 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TDMAE);
524 write_ssi_mask(&ssi->scr, 0,
525 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
526 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RDMAE);
531 case SNDRV_PCM_TRIGGER_STOP:
532 case SNDRV_PCM_TRIGGER_SUSPEND:
533 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
534 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
535 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
536 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TDMAE, 0);
538 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
539 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RDMAE, 0);
541 if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
542 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
552 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
554 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
555 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
556 u32 strcr = 0, stcr, srcr, scr, mask;
558 scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_NET);
560 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR
561 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL
562 | CCSR_SSI_STCR_TEFS;
563 stcr = read_ssi(&ssi->stcr) & ~mask;
564 srcr = read_ssi(&ssi->srcr) & ~mask;
567 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
568 case SND_SOC_DAIFMT_I2S:
569 scr |= CCSR_SSI_SCR_NET;
571 /* Pre-set SSI I2S mode */
572 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
573 case SND_SOC_DAIFMT_CBS_CFS:
574 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
576 case SND_SOC_DAIFMT_CBM_CFM:
577 ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
580 dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_MASTER: %d",
581 fmt & SND_SOC_DAIFMT_MASTER_MASK);
584 scr &= ~CCSR_SSI_SCR_I2S_MODE_MASK;
585 scr |= ssi_private->i2s_mode;
587 /* Data on rising edge of bclk, frame low, 1clk before data */
588 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP
589 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
591 case SND_SOC_DAIFMT_LEFT_J:
592 /* Data on rising edge of bclk, frame high */
593 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
595 case SND_SOC_DAIFMT_DSP_A:
596 /* Data on rising edge of bclk, frame high, 1clk before data */
597 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP
598 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
600 case SND_SOC_DAIFMT_DSP_B:
601 /* Data on rising edge of bclk, frame high */
602 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP
603 | CCSR_SSI_STCR_TXBIT0;
606 dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT: %d",
607 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
611 /* DAI clock inversion */
612 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
613 case SND_SOC_DAIFMT_NB_NF:
614 /* Nothing to do for both normal cases */
616 case SND_SOC_DAIFMT_IB_NF:
617 /* Invert bit clock */
618 strcr ^= CCSR_SSI_STCR_TSCKP;
620 case SND_SOC_DAIFMT_NB_IF:
621 /* Invert frame clock */
622 strcr ^= CCSR_SSI_STCR_TFSI;
624 case SND_SOC_DAIFMT_IB_IF:
625 /* Invert both clocks */
626 strcr ^= CCSR_SSI_STCR_TSCKP;
627 strcr ^= CCSR_SSI_STCR_TFSI;
630 dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_INV: %d",
631 fmt & SND_SOC_DAIFMT_INV_MASK);
635 /* DAI clock master masks */
636 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
637 case SND_SOC_DAIFMT_CBS_CFS:
638 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
639 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
641 case SND_SOC_DAIFMT_CBM_CFM:
642 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
645 dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_MASTER: %d",
646 fmt & SND_SOC_DAIFMT_MASTER_MASK);
653 if (ssi_private->cpu_dai_drv.symmetric_rates) {
654 scr |= CCSR_SSI_SCR_SYN;
656 /* Need to clear RXDIR when using SYNC mode */
657 srcr &= ~CCSR_SSI_SRCR_RXDIR;
660 write_ssi(stcr, &ssi->stcr);
661 write_ssi(srcr, &ssi->srcr);
662 write_ssi(scr, &ssi->scr);
667 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
668 int clk_id, unsigned int freq, int dir)
670 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
671 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
672 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
673 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
674 unsigned long clkrate, sysrate = 0;
675 u64 sub, savesub = 100000;
678 * It should be already enough to divide clock by setting pm.
679 * So we here keep psr and div2 to 0.
684 factor = (div2 + 1) * (7 * psr + 1) * 2;
686 for (i = 0; i < 255; i++) {
687 /* The bclk rate must be smaller than 1/5 sysclk rate */
688 if (factor * (i + 1) < 5)
691 sysrate = freq * factor * (i + 2);
692 clkrate = clk_round_rate(ssi_private->clk, sysrate);
694 do_div(clkrate, factor);
695 afreq = (u32)clkrate / (i + 1);
699 else if (freq / afreq == 1)
701 else if (afreq / freq == 1)
706 /* Calculate the fraction */
711 ssi_private->sysrate = sysrate;
721 /* No proper pm found if it is still remaining the initial value */
723 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
727 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0)
728 | (psr ? CCSR_SSI_SxCCR_PSR : 0);
729 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2_MASK
730 | CCSR_SSI_SxCCR_PSR_MASK;
732 if (dir == SND_SOC_CLOCK_OUT || synchronous)
733 write_ssi_mask(&ssi->stccr, mask, stccr);
735 write_ssi_mask(&ssi->srccr, mask, stccr);
740 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
741 u32 rx_mask, int slots, int slot_width)
743 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
744 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
746 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
747 CCSR_SSI_SxCCR_DC(slots));
748 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
749 CCSR_SSI_SxCCR_DC(slots));
751 /* The register SxMSKs need SSI to provide essential clock due to
752 * hardware design. So we here temporarily enable SSI to set them.
754 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
755 write_ssi(tx_mask, &ssi->stmsk);
756 write_ssi(rx_mask, &ssi->srmsk);
757 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
763 * fsl_ssi_shutdown: shutdown the SSI
765 * Shutdown the SSI if there are no other substreams open.
767 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
768 struct snd_soc_dai *dai)
770 struct snd_soc_pcm_runtime *rtd = substream->private_data;
771 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
773 /* If this is the last active substream, disable the interrupts. */
775 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
777 write_ssi_mask(&ssi->sier, SIER_FLAGS, 0);
779 ssi_private->sysrate = 0;
782 if (ssi_private->ssi_on_imx) {
783 clk_disable_unprepare(ssi_private->clk);
784 clk_disable_unprepare(ssi_private->coreclk);
786 pm_runtime_put_sync(dai->dev);
790 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
792 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
794 if (ssi_private->ssi_on_imx) {
795 dai->playback_dma_data = &ssi_private->dma_params_tx;
796 dai->capture_dma_data = &ssi_private->dma_params_rx;
802 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
803 .startup = fsl_ssi_startup,
804 .hw_params = fsl_ssi_hw_params,
805 .set_fmt = fsl_ssi_set_dai_fmt,
806 .set_sysclk = fsl_ssi_set_dai_sysclk,
807 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
808 .shutdown = fsl_ssi_shutdown,
809 .trigger = fsl_ssi_trigger,
812 /* Template for the CPU dai driver structure */
813 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
814 .probe = fsl_ssi_dai_probe,
818 .rates = FSLSSI_I2S_RATES,
819 .formats = FSLSSI_I2S_FORMATS,
824 .rates = FSLSSI_I2S_RATES,
825 .formats = FSLSSI_I2S_FORMATS,
827 .ops = &fsl_ssi_dai_ops,
830 static const struct snd_soc_component_driver fsl_ssi_component = {
834 /* Show the statistics of a flag only if its interrupt is enabled. The
835 * compiler will optimze this code to a no-op if the interrupt is not
838 #define SIER_SHOW(flag, name) \
840 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
841 length += sprintf(buf + length, #name "=%u\n", \
842 ssi_private->stats.name); \
847 * fsl_sysfs_ssi_show: display SSI statistics
849 * Display the statistics for the current SSI device. To avoid confusion,
850 * we only show those counts that are enabled.
852 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
853 struct device_attribute *attr, char *buf)
855 struct fsl_ssi_private *ssi_private =
856 container_of(attr, struct fsl_ssi_private, dev_attr);
859 SIER_SHOW(RFRC_EN, rfrc);
860 SIER_SHOW(TFRC_EN, tfrc);
861 SIER_SHOW(CMDAU_EN, cmdau);
862 SIER_SHOW(CMDDU_EN, cmddu);
863 SIER_SHOW(RXT_EN, rxt);
864 SIER_SHOW(RDR1_EN, rdr1);
865 SIER_SHOW(RDR0_EN, rdr0);
866 SIER_SHOW(TDE1_EN, tde1);
867 SIER_SHOW(TDE0_EN, tde0);
868 SIER_SHOW(ROE1_EN, roe1);
869 SIER_SHOW(ROE0_EN, roe0);
870 SIER_SHOW(TUE1_EN, tue1);
871 SIER_SHOW(TUE0_EN, tue0);
872 SIER_SHOW(TFS_EN, tfs);
873 SIER_SHOW(RFS_EN, rfs);
874 SIER_SHOW(TLS_EN, tls);
875 SIER_SHOW(RLS_EN, rls);
876 SIER_SHOW(RFF1_EN, rff1);
877 SIER_SHOW(RFF0_EN, rff0);
878 SIER_SHOW(TFE1_EN, tfe1);
879 SIER_SHOW(TFE0_EN, tfe0);
885 * Make every character in a string lower-case
887 static void make_lowercase(char *s)
893 if ((c >= 'A') && (c <= 'Z'))
894 *p = c + ('a' - 'A');
899 static int fsl_ssi_probe(struct platform_device *pdev)
901 struct fsl_ssi_private *ssi_private;
903 struct device_attribute *dev_attr = NULL;
904 struct device_node *np = pdev->dev.of_node;
905 const char *p, *sprop;
906 const uint32_t *iprop;
910 /* SSIs that are not connected on the board should have a
911 * status = "disabled"
912 * property in their device tree nodes.
914 if (!of_device_is_available(np))
917 /* The DAI name is the last part of the full name of the node. */
918 p = strrchr(np->full_name, '/') + 1;
919 ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p),
922 dev_err(&pdev->dev, "could not allocate DAI object\n");
926 strcpy(ssi_private->name, p);
928 /* Initialize this copy of the CPU DAI driver structure */
929 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
930 sizeof(fsl_ssi_dai_template));
931 ssi_private->cpu_dai_drv.name = ssi_private->name;
933 /* Get the addresses and IRQ */
934 ret = of_address_to_resource(np, 0, &res);
936 dev_err(&pdev->dev, "could not determine device resources\n");
939 ssi_private->ssi = of_iomap(np, 0);
940 if (!ssi_private->ssi) {
941 dev_err(&pdev->dev, "could not map device resources\n");
945 ssi_private->ssi_phys = res.start;
947 ssi_private->irq = irq_of_parse_and_map(np, 0);
948 if (ssi_private->irq == NO_IRQ) {
949 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
954 /* The 'name' should not have any slashes in it. */
955 ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, ssi_private->name,
958 dev_err(&pdev->dev, "could not claim irq %u\n", ssi_private->irq);
962 /* Are the RX and the TX clocks locked? */
963 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
964 ssi_private->cpu_dai_drv.symmetric_rates = 1;
965 ssi_private->cpu_dai_drv.symmetric_channels = 1;
966 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
969 /* Determine the FIFO depth. */
970 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
972 ssi_private->fifo_depth = be32_to_cpup(iprop);
974 /* Older 8610 DTs didn't have the fifo-depth property */
975 ssi_private->fifo_depth = 8;
977 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
978 ssi_private->ssi_on_imx = true;
980 ssi_private->coreclk = devm_clk_get(&pdev->dev, "ipg");
981 if (IS_ERR(ssi_private->coreclk)) {
982 ret = PTR_ERR(ssi_private->coreclk);
983 dev_err(&pdev->dev, "could not get ipg clock: %d\n", ret);
986 ssi_private->clk = devm_clk_get(&pdev->dev, "baud");
987 if (IS_ERR(ssi_private->clk)) {
988 ret = PTR_ERR(ssi_private->clk);
989 dev_err(&pdev->dev, "could not get baud clock: %d\n", ret);
994 * We have burstsize be "fifo_depth - 2" to match the SSI
995 * watermark setting in fsl_ssi_startup().
997 ssi_private->dma_params_tx.maxburst =
998 ssi_private->fifo_depth - 2;
999 ssi_private->dma_params_rx.maxburst =
1000 ssi_private->fifo_depth - 2;
1001 ssi_private->dma_params_tx.addr =
1002 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
1003 ssi_private->dma_params_rx.addr =
1004 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
1007 ssi_private->sysrate = 0;
1009 /* Initialize the the device_attribute structure */
1010 dev_attr = &ssi_private->dev_attr;
1011 sysfs_attr_init(&dev_attr->attr);
1012 dev_attr->attr.name = "statistics";
1013 dev_attr->attr.mode = S_IRUGO;
1014 dev_attr->show = fsl_sysfs_ssi_show;
1016 ret = device_create_file(&pdev->dev, dev_attr);
1018 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1019 ssi_private->dev_attr.attr.name);
1023 pm_runtime_enable(&pdev->dev);
1025 /* Register with ASoC */
1026 dev_set_drvdata(&pdev->dev, ssi_private);
1028 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1029 &ssi_private->cpu_dai_drv, 1);
1031 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1035 if (ssi_private->ssi_on_imx) {
1036 ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE,
1037 IMX_SSI_DMABUF_SIZE);
1042 /* Enable dual fifo feature as default */
1043 ssi_private->use_dual_fifo = true;
1046 * If codec-handle property is missing from SSI node, we assume
1047 * that the machine driver uses new binding which does not require
1048 * SSI driver to trigger machine driver's probe.
1050 if (!of_get_property(np, "codec-handle", NULL)) {
1051 ssi_private->new_binding = true;
1055 /* Trigger the machine driver's probe function. The platform driver
1056 * name of the machine driver is taken from /compatible property of the
1057 * device tree. We also pass the address of the CPU DAI driver
1060 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1061 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1062 p = strrchr(sprop, ',');
1065 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1066 make_lowercase(name);
1069 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1070 if (IS_ERR(ssi_private->pdev)) {
1071 ret = PTR_ERR(ssi_private->pdev);
1072 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1080 if (ssi_private->ssi_on_imx)
1081 imx_pcm_dma_exit(pdev);
1082 snd_soc_unregister_component(&pdev->dev);
1085 dev_set_drvdata(&pdev->dev, NULL);
1086 device_remove_file(&pdev->dev, dev_attr);
1089 free_irq(ssi_private->irq, ssi_private);
1092 irq_dispose_mapping(ssi_private->irq);
1095 iounmap(ssi_private->ssi);
1103 static int fsl_ssi_remove(struct platform_device *pdev)
1105 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1107 if (!ssi_private->new_binding)
1108 platform_device_unregister(ssi_private->pdev);
1109 if (ssi_private->ssi_on_imx)
1110 imx_pcm_dma_exit(pdev);
1112 snd_soc_unregister_component(&pdev->dev);
1113 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1115 free_irq(ssi_private->irq, ssi_private);
1116 irq_dispose_mapping(ssi_private->irq);
1119 dev_set_drvdata(&pdev->dev, NULL);
1124 #ifdef CONFIG_PM_RUNTIME
1125 static int fsl_ssi_runtime_resume(struct device *dev)
1127 request_bus_freq(BUS_FREQ_AUDIO);
1131 static int fsl_ssi_runtime_suspend(struct device *dev)
1133 release_bus_freq(BUS_FREQ_AUDIO);
1138 static const struct dev_pm_ops fsl_ssi_pm = {
1139 SET_RUNTIME_PM_OPS(fsl_ssi_runtime_suspend,
1140 fsl_ssi_runtime_resume,
1144 static const struct of_device_id fsl_ssi_ids[] = {
1145 { .compatible = "fsl,mpc8610-ssi", },
1146 { .compatible = "fsl,imx21-ssi", },
1149 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1151 static struct platform_driver fsl_ssi_driver = {
1153 .name = "fsl-ssi-dai",
1154 .owner = THIS_MODULE,
1155 .of_match_table = fsl_ssi_ids,
1158 .probe = fsl_ssi_probe,
1159 .remove = fsl_ssi_remove,
1162 module_platform_driver(fsl_ssi_driver);
1164 MODULE_ALIAS("platform:fsl-ssi-dai");
1165 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1166 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1167 MODULE_LICENSE("GPL v2");