2 * imx-ssi.c -- ALSA Soc Audio Layer
4 * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
6 * This code is based on code copyrighted by Freescale,
7 * Liam Girdwood, Javier Martin and probably others.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developped with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/init.h>
39 #include <linux/interrupt.h>
40 #include <linux/module.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
44 #include <sound/core.h>
45 #include <sound/initval.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/soc.h>
51 #include <mach/hardware.h>
55 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
58 * SSI Network Mode or TDM slots configuration.
59 * Should only be called when port is inactive (i.e. SSIEN = 0).
61 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
62 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
64 struct imx_ssi *ssi = cpu_dai->private_data;
67 sccr = readl(ssi->base + SSI_STCCR);
68 sccr &= ~SSI_STCCR_DC_MASK;
69 sccr |= SSI_STCCR_DC(slots - 1);
70 writel(sccr, ssi->base + SSI_STCCR);
72 sccr = readl(ssi->base + SSI_SRCCR);
73 sccr &= ~SSI_STCCR_DC_MASK;
74 sccr |= SSI_STCCR_DC(slots - 1);
75 writel(sccr, ssi->base + SSI_SRCCR);
77 writel(tx_mask, ssi->base + SSI_STMSK);
78 writel(rx_mask, ssi->base + SSI_SRMSK);
84 * SSI DAI format configuration.
85 * Should only be called when port is inactive (i.e. SSIEN = 0).
87 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
89 struct imx_ssi *ssi = cpu_dai->private_data;
92 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
95 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
96 case SND_SOC_DAIFMT_I2S:
97 /* data on rising edge of bclk, frame low 1clk before data */
98 strcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0;
100 if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
101 scr &= ~SSI_I2S_MODE_MASK;
102 scr |= SSI_SCR_I2S_MODE_SLAVE;
105 case SND_SOC_DAIFMT_LEFT_J:
106 /* data on rising edge of bclk, frame high with data */
107 strcr |= SSI_STCR_TXBIT0;
109 case SND_SOC_DAIFMT_DSP_B:
110 /* data on rising edge of bclk, frame high with data */
111 strcr |= SSI_STCR_TFSL;
113 case SND_SOC_DAIFMT_DSP_A:
114 /* data on rising edge of bclk, frame high 1clk before data */
115 strcr |= SSI_STCR_TFSL | SSI_STCR_TEFS;
119 /* DAI clock inversion */
120 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
121 case SND_SOC_DAIFMT_IB_IF:
122 strcr |= SSI_STCR_TFSI;
123 strcr &= ~SSI_STCR_TSCKP;
125 case SND_SOC_DAIFMT_IB_NF:
126 strcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI);
128 case SND_SOC_DAIFMT_NB_IF:
129 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP;
131 case SND_SOC_DAIFMT_NB_NF:
132 strcr &= ~SSI_STCR_TFSI;
133 strcr |= SSI_STCR_TSCKP;
137 /* DAI clock master masks */
138 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
139 case SND_SOC_DAIFMT_CBM_CFM:
142 /* Master mode not implemented, needs handling of clocks. */
146 strcr |= SSI_STCR_TFEN0;
148 if (ssi->flags & IMX_SSI_NET)
150 if (ssi->flags & IMX_SSI_SYN)
153 writel(strcr, ssi->base + SSI_STCR);
154 writel(strcr, ssi->base + SSI_SRCR);
155 writel(scr, ssi->base + SSI_SCR);
161 * SSI system clock configuration.
162 * Should only be called when port is inactive (i.e. SSIEN = 0).
164 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
165 int clk_id, unsigned int freq, int dir)
167 struct imx_ssi *ssi = cpu_dai->private_data;
170 scr = readl(ssi->base + SSI_SCR);
173 case IMX_SSP_SYS_CLK:
174 if (dir == SND_SOC_CLOCK_OUT)
175 scr |= SSI_SCR_SYS_CLK_EN;
177 scr &= ~SSI_SCR_SYS_CLK_EN;
183 writel(scr, ssi->base + SSI_SCR);
190 * Should only be called when port is inactive (i.e. SSIEN = 0).
192 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
195 struct imx_ssi *ssi = cpu_dai->private_data;
198 stccr = readl(ssi->base + SSI_STCCR);
199 srccr = readl(ssi->base + SSI_SRCCR);
202 case IMX_SSI_TX_DIV_2:
203 stccr &= ~SSI_STCCR_DIV2;
206 case IMX_SSI_TX_DIV_PSR:
207 stccr &= ~SSI_STCCR_PSR;
210 case IMX_SSI_TX_DIV_PM:
212 stccr |= SSI_STCCR_PM(div);
214 case IMX_SSI_RX_DIV_2:
215 stccr &= ~SSI_STCCR_DIV2;
218 case IMX_SSI_RX_DIV_PSR:
219 stccr &= ~SSI_STCCR_PSR;
222 case IMX_SSI_RX_DIV_PM:
224 stccr |= SSI_STCCR_PM(div);
230 writel(stccr, ssi->base + SSI_STCCR);
231 writel(srccr, ssi->base + SSI_SRCCR);
237 * Should only be called when port is inactive (i.e. SSIEN = 0),
238 * although can be called multiple times by upper layers.
240 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
241 struct snd_pcm_hw_params *params,
242 struct snd_soc_dai *cpu_dai)
244 struct imx_ssi *ssi = cpu_dai->private_data;
245 struct imx_pcm_dma_params *dma_data;
249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
251 dma_data = &ssi->dma_params_tx;
254 dma_data = &ssi->dma_params_rx;
257 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
259 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
261 /* DAI data (word) size */
262 switch (params_format(params)) {
263 case SNDRV_PCM_FORMAT_S16_LE:
264 sccr |= SSI_SRCCR_WL(16);
266 case SNDRV_PCM_FORMAT_S20_3LE:
267 sccr |= SSI_SRCCR_WL(20);
269 case SNDRV_PCM_FORMAT_S24_LE:
270 sccr |= SSI_SRCCR_WL(24);
274 writel(sccr, ssi->base + reg);
279 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
280 struct snd_soc_dai *dai)
282 struct snd_soc_pcm_runtime *rtd = substream->private_data;
283 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
284 struct imx_ssi *ssi = cpu_dai->private_data;
285 unsigned int sier_bits, sier;
288 scr = readl(ssi->base + SSI_SCR);
289 sier = readl(ssi->base + SSI_SIER);
291 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
292 if (ssi->flags & IMX_SSI_DMA)
293 sier_bits = SSI_SIER_TDMAE;
295 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
297 if (ssi->flags & IMX_SSI_DMA)
298 sier_bits = SSI_SIER_RDMAE;
300 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
304 case SNDRV_PCM_TRIGGER_START:
305 case SNDRV_PCM_TRIGGER_RESUME:
306 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
313 if (++ssi->enabled == 1)
314 scr |= SSI_SCR_SSIEN;
318 case SNDRV_PCM_TRIGGER_STOP:
319 case SNDRV_PCM_TRIGGER_SUSPEND:
320 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
321 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
327 if (--ssi->enabled == 0)
328 scr &= ~SSI_SCR_SSIEN;
335 if (!(ssi->flags & IMX_SSI_USE_AC97))
336 /* rx/tx are always enabled to access ac97 registers */
337 writel(scr, ssi->base + SSI_SCR);
339 writel(sier, ssi->base + SSI_SIER);
344 static struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
345 .hw_params = imx_ssi_hw_params,
346 .set_fmt = imx_ssi_set_dai_fmt,
347 .set_clkdiv = imx_ssi_set_dai_clkdiv,
348 .set_sysclk = imx_ssi_set_dai_sysclk,
349 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
350 .trigger = imx_ssi_trigger,
353 static struct snd_soc_dai imx_ssi_dai = {
357 .rates = SNDRV_PCM_RATE_8000_96000,
358 .formats = SNDRV_PCM_FMTBIT_S16_LE,
363 .rates = SNDRV_PCM_RATE_8000_96000,
364 .formats = SNDRV_PCM_FMTBIT_S16_LE,
366 .ops = &imx_ssi_pcm_dai_ops,
369 int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
370 struct vm_area_struct *vma)
372 struct snd_pcm_runtime *runtime = substream->runtime;
375 ret = dma_mmap_coherent(NULL, vma, runtime->dma_area,
376 runtime->dma_addr, runtime->dma_bytes);
378 pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
385 static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
387 struct snd_pcm_substream *substream = pcm->streams[stream].substream;
388 struct snd_dma_buffer *buf = &substream->dma_buffer;
389 size_t size = IMX_SSI_DMABUF_SIZE;
391 buf->dev.type = SNDRV_DMA_TYPE_DEV;
392 buf->dev.dev = pcm->card->dev;
393 buf->private_data = NULL;
394 buf->area = dma_alloc_writecombine(pcm->card->dev, size,
395 &buf->addr, GFP_KERNEL);
403 static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
405 int imx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
411 if (!card->dev->dma_mask)
412 card->dev->dma_mask = &imx_pcm_dmamask;
413 if (!card->dev->coherent_dma_mask)
414 card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
415 if (dai->playback.channels_min) {
416 ret = imx_pcm_preallocate_dma_buffer(pcm,
417 SNDRV_PCM_STREAM_PLAYBACK);
422 if (dai->capture.channels_min) {
423 ret = imx_pcm_preallocate_dma_buffer(pcm,
424 SNDRV_PCM_STREAM_CAPTURE);
433 void imx_pcm_free(struct snd_pcm *pcm)
435 struct snd_pcm_substream *substream;
436 struct snd_dma_buffer *buf;
439 for (stream = 0; stream < 2; stream++) {
440 substream = pcm->streams[stream].substream;
444 buf = &substream->dma_buffer;
448 dma_free_writecombine(pcm->card->dev, buf->bytes,
449 buf->area, buf->addr);
454 struct snd_soc_platform imx_soc_platform = {
457 EXPORT_SYMBOL_GPL(imx_soc_platform);
459 static struct snd_soc_dai imx_ac97_dai = {
463 .stream_name = "AC97 Playback",
466 .rates = SNDRV_PCM_RATE_48000,
467 .formats = SNDRV_PCM_FMTBIT_S16_LE,
470 .stream_name = "AC97 Capture",
473 .rates = SNDRV_PCM_RATE_48000,
474 .formats = SNDRV_PCM_FMTBIT_S16_LE,
476 .ops = &imx_ssi_pcm_dai_ops,
479 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
481 void __iomem *base = imx_ssi->base;
483 writel(0x0, base + SSI_SCR);
484 writel(0x0, base + SSI_STCR);
485 writel(0x0, base + SSI_SRCR);
487 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
489 writel(SSI_SFCSR_RFWM0(8) |
492 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
494 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
495 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
497 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
498 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
500 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
501 SSI_SCR_TE | SSI_SCR_RE,
504 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
505 writel(0xff, base + SSI_SACCDIS);
506 writel(0x300, base + SSI_SACCEN);
509 static struct imx_ssi *ac97_ssi;
511 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
514 struct imx_ssi *imx_ssi = ac97_ssi;
515 void __iomem *base = imx_ssi->base;
522 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
525 writel(lreg, base + SSI_SACADD);
528 writel(lval , base + SSI_SACDAT);
530 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
534 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
537 struct imx_ssi *imx_ssi = ac97_ssi;
538 void __iomem *base = imx_ssi->base;
540 unsigned short val = -1;
543 lreg = (reg & 0x7f) << 12 ;
544 writel(lreg, base + SSI_SACADD);
545 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
549 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
551 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
556 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
558 struct imx_ssi *imx_ssi = ac97_ssi;
560 if (imx_ssi->ac97_reset)
561 imx_ssi->ac97_reset(ac97);
564 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
566 struct imx_ssi *imx_ssi = ac97_ssi;
568 if (imx_ssi->ac97_warm_reset)
569 imx_ssi->ac97_warm_reset(ac97);
572 struct snd_ac97_bus_ops soc_ac97_ops = {
573 .read = imx_ssi_ac97_read,
574 .write = imx_ssi_ac97_write,
575 .reset = imx_ssi_ac97_reset,
576 .warm_reset = imx_ssi_ac97_warm_reset
578 EXPORT_SYMBOL_GPL(soc_ac97_ops);
580 struct snd_soc_dai imx_ssi_pcm_dai[2];
581 EXPORT_SYMBOL_GPL(imx_ssi_pcm_dai);
583 static int imx_ssi_probe(struct platform_device *pdev)
585 struct resource *res;
587 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
588 struct snd_soc_platform *platform;
591 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
593 if (dai->id >= ARRAY_SIZE(imx_ssi_pcm_dai))
596 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
601 ssi->ac97_reset = pdata->ac97_reset;
602 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
603 ssi->flags = pdata->flags;
606 ssi->irq = platform_get_irq(pdev, 0);
608 ssi->clk = clk_get(&pdev->dev, NULL);
609 if (IS_ERR(ssi->clk)) {
610 ret = PTR_ERR(ssi->clk);
611 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
615 clk_enable(ssi->clk);
617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
620 goto failed_get_resource;
623 if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
624 dev_err(&pdev->dev, "request_mem_region failed\n");
626 goto failed_get_resource;
629 ssi->base = ioremap(res->start, resource_size(res));
631 dev_err(&pdev->dev, "ioremap failed\n");
636 if (ssi->flags & IMX_SSI_USE_AC97) {
642 setup_channel_to_ac97(ssi);
643 memcpy(dai, &imx_ac97_dai, sizeof(imx_ac97_dai));
645 memcpy(dai, &imx_ssi_dai, sizeof(imx_ssi_dai));
647 writel(0x0, ssi->base + SSI_SIER);
649 ssi->dma_params_rx.dma_addr = res->start + SSI_SRX0;
650 ssi->dma_params_tx.dma_addr = res->start + SSI_STX0;
652 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
654 ssi->dma_params_tx.dma = res->start;
656 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
658 ssi->dma_params_rx.dma = res->start;
661 dai->dev = &pdev->dev;
662 dai->name = kasprintf(GFP_KERNEL, "imx-ssi.%d", pdev->id);
663 dai->private_data = ssi;
665 if ((cpu_is_mx27() || cpu_is_mx21()) &&
666 !(ssi->flags & IMX_SSI_USE_AC97) &&
667 (ssi->flags & IMX_SSI_DMA)) {
668 ssi->flags |= IMX_SSI_DMA;
669 platform = imx_ssi_dma_mx2_init(pdev, ssi);
671 platform = imx_ssi_fiq_init(pdev, ssi);
673 imx_soc_platform.pcm_ops = platform->pcm_ops;
674 imx_soc_platform.pcm_new = platform->pcm_new;
675 imx_soc_platform.pcm_free = platform->pcm_free;
677 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.burstsize) |
678 SSI_SFCSR_RFWM0(ssi->dma_params_rx.burstsize);
679 writel(val, ssi->base + SSI_SFCSR);
681 ret = snd_soc_register_dai(dai);
683 dev_err(&pdev->dev, "register DAI failed\n");
684 goto failed_register;
687 platform_set_drvdata(pdev, ssi);
695 release_mem_region(res->start, resource_size(res));
697 clk_disable(ssi->clk);
705 static int __devexit imx_ssi_remove(struct platform_device *pdev)
707 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
708 struct imx_ssi *ssi = platform_get_drvdata(pdev);
709 struct snd_soc_dai *dai = &imx_ssi_pcm_dai[pdev->id];
711 snd_soc_unregister_dai(dai);
713 if (ssi->flags & IMX_SSI_USE_AC97)
716 if (!(ssi->flags & IMX_SSI_DMA))
717 imx_ssi_fiq_exit(pdev, ssi);
720 release_mem_region(res->start, resource_size(res));
721 clk_disable(ssi->clk);
728 static struct platform_driver imx_ssi_driver = {
729 .probe = imx_ssi_probe,
730 .remove = __devexit_p(imx_ssi_remove),
734 .owner = THIS_MODULE,
738 static int __init imx_ssi_init(void)
742 ret = snd_soc_register_platform(&imx_soc_platform);
744 pr_err("failed to register soc platform: %d\n", ret);
748 ret = platform_driver_register(&imx_ssi_driver);
750 snd_soc_unregister_platform(&imx_soc_platform);
757 static void __exit imx_ssi_exit(void)
759 platform_driver_unregister(&imx_ssi_driver);
760 snd_soc_unregister_platform(&imx_soc_platform);
763 module_init(imx_ssi_init);
764 module_exit(imx_ssi_exit);
766 /* Module information */
767 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
768 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
769 MODULE_LICENSE("GPL");