2 * sst_acpi.c - SST (LPE) driver init file for ACPI enumeration.
4 * Copyright (c) 2013, Intel Corporation.
6 * Authors: Ramesh Babu K V <Ramesh.Babu@intel.com>
7 * Authors: Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 #include <linux/module.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
26 #include <linux/miscdevice.h>
27 #include <linux/platform_device.h>
28 #include <linux/firmware.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pm_qos.h>
31 #include <linux/dmi.h>
32 #include <linux/acpi.h>
33 #include <asm/platform_sst_audio.h>
34 #include <sound/core.h>
35 #include <sound/soc.h>
36 #include <sound/compress_driver.h>
37 #include <acpi/acbuffer.h>
38 #include <acpi/platform/acenv.h>
39 #include <acpi/platform/aclinux.h>
40 #include <acpi/actypes.h>
41 #include <acpi/acpi_bus.h>
42 #include <asm/cpu_device_id.h>
43 #include <asm/iosf_mbi.h>
44 #include "../sst-mfld-platform.h"
45 #include "../../common/sst-dsp.h"
46 #include "../../common/sst-acpi.h"
49 /* LPE viewpoint addresses */
50 #define SST_BYT_IRAM_PHY_START 0xff2c0000
51 #define SST_BYT_IRAM_PHY_END 0xff2d4000
52 #define SST_BYT_DRAM_PHY_START 0xff300000
53 #define SST_BYT_DRAM_PHY_END 0xff320000
54 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
55 #define SST_BYT_IMR_VIRT_END 0xc01fffff
56 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
57 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
58 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
59 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
60 #define SST_BYT_SSP0_PHY_ADDR 0xff2a0000
61 #define SST_BYT_SSP2_PHY_ADDR 0xff2a2000
63 #define BYT_FW_MOD_TABLE_OFFSET 0x80000
64 #define BYT_FW_MOD_TABLE_SIZE 0x100
65 #define BYT_FW_MOD_OFFSET (BYT_FW_MOD_TABLE_OFFSET + BYT_FW_MOD_TABLE_SIZE)
67 static const struct sst_info byt_fwparse_info = {
70 .iram_start = SST_BYT_IRAM_PHY_START,
71 .iram_end = SST_BYT_IRAM_PHY_END,
73 .dram_start = SST_BYT_DRAM_PHY_START,
74 .dram_end = SST_BYT_DRAM_PHY_END,
76 .imr_start = SST_BYT_IMR_VIRT_START,
77 .imr_end = SST_BYT_IMR_VIRT_END,
79 .mailbox_start = SST_BYT_MBOX_PHY_ADDR,
81 .lpe_viewpt_rqd = true,
84 static const struct sst_ipc_info byt_ipc_info = {
86 .mbox_recv_off = 0x400,
89 static const struct sst_lib_dnld_info byt_lib_dnld_info = {
90 .mod_base = SST_BYT_IMR_VIRT_START,
91 .mod_end = SST_BYT_IMR_VIRT_END,
92 .mod_table_offset = BYT_FW_MOD_TABLE_OFFSET,
93 .mod_table_size = BYT_FW_MOD_TABLE_SIZE,
94 .mod_ddr_dnld = false,
97 static const struct sst_res_info byt_rvp_res_info = {
98 .shim_offset = 0x140000,
99 .shim_size = 0x000100,
100 .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
101 .ssp0_offset = 0xa0000,
103 .dma0_offset = 0x98000,
105 .dma1_offset = 0x9c000,
107 .iram_offset = 0x0c0000,
108 .iram_size = 0x14000,
109 .dram_offset = 0x100000,
110 .dram_size = 0x28000,
111 .mbox_offset = 0x144000,
113 .acpi_lpe_res_index = 0,
115 .acpi_ipc_irq_index = 5,
118 /* BYTCR has different BIOS from BYT */
119 static const struct sst_res_info bytcr_res_info = {
120 .shim_offset = 0x140000,
121 .shim_size = 0x000100,
122 .shim_phy_addr = SST_BYT_SHIM_PHY_ADDR,
123 .ssp0_offset = 0xa0000,
125 .dma0_offset = 0x98000,
127 .dma1_offset = 0x9c000,
129 .iram_offset = 0x0c0000,
130 .iram_size = 0x14000,
131 .dram_offset = 0x100000,
132 .dram_size = 0x28000,
133 .mbox_offset = 0x144000,
135 .acpi_lpe_res_index = 0,
137 .acpi_ipc_irq_index = 0
140 static struct sst_platform_info byt_rvp_platform_data = {
141 .probe_data = &byt_fwparse_info,
142 .ipc_info = &byt_ipc_info,
143 .lib_info = &byt_lib_dnld_info,
144 .res_info = &byt_rvp_res_info,
145 .platform = "sst-mfld-platform",
148 /* Cherryview (Cherrytrail and Braswell) uses same mrfld dpcm fw as Baytrail,
149 * so pdata is same as Baytrail.
151 static struct sst_platform_info chv_platform_data = {
152 .probe_data = &byt_fwparse_info,
153 .ipc_info = &byt_ipc_info,
154 .lib_info = &byt_lib_dnld_info,
155 .res_info = &byt_rvp_res_info,
156 .platform = "sst-mfld-platform",
159 static int sst_platform_get_resources(struct intel_sst_drv *ctx)
161 struct resource *rsrc;
162 struct platform_device *pdev = to_platform_device(ctx->dev);
164 /* All ACPI resource request here */
166 rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
167 ctx->pdata->res_info->acpi_lpe_res_index);
169 dev_err(ctx->dev, "Invalid SHIM base from IFWI\n");
172 dev_info(ctx->dev, "LPE base: %#x size:%#x", (unsigned int) rsrc->start,
173 (unsigned int)resource_size(rsrc));
175 ctx->iram_base = rsrc->start + ctx->pdata->res_info->iram_offset;
176 ctx->iram_end = ctx->iram_base + ctx->pdata->res_info->iram_size - 1;
177 dev_info(ctx->dev, "IRAM base: %#x", ctx->iram_base);
178 ctx->iram = devm_ioremap_nocache(ctx->dev, ctx->iram_base,
179 ctx->pdata->res_info->iram_size);
181 dev_err(ctx->dev, "unable to map IRAM\n");
185 ctx->dram_base = rsrc->start + ctx->pdata->res_info->dram_offset;
186 ctx->dram_end = ctx->dram_base + ctx->pdata->res_info->dram_size - 1;
187 dev_info(ctx->dev, "DRAM base: %#x", ctx->dram_base);
188 ctx->dram = devm_ioremap_nocache(ctx->dev, ctx->dram_base,
189 ctx->pdata->res_info->dram_size);
191 dev_err(ctx->dev, "unable to map DRAM\n");
195 ctx->shim_phy_add = rsrc->start + ctx->pdata->res_info->shim_offset;
196 dev_info(ctx->dev, "SHIM base: %#x", ctx->shim_phy_add);
197 ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add,
198 ctx->pdata->res_info->shim_size);
200 dev_err(ctx->dev, "unable to map SHIM\n");
204 /* reassign physical address to LPE viewpoint address */
205 ctx->shim_phy_add = ctx->pdata->res_info->shim_phy_addr;
207 /* Get mailbox addr */
208 ctx->mailbox_add = rsrc->start + ctx->pdata->res_info->mbox_offset;
209 dev_info(ctx->dev, "Mailbox base: %#x", ctx->mailbox_add);
210 ctx->mailbox = devm_ioremap_nocache(ctx->dev, ctx->mailbox_add,
211 ctx->pdata->res_info->mbox_size);
213 dev_err(ctx->dev, "unable to map mailbox\n");
217 /* reassign physical address to LPE viewpoint address */
218 ctx->mailbox_add = ctx->info.mailbox_start;
220 rsrc = platform_get_resource(pdev, IORESOURCE_MEM,
221 ctx->pdata->res_info->acpi_ddr_index);
223 dev_err(ctx->dev, "Invalid DDR base from IFWI\n");
226 ctx->ddr_base = rsrc->start;
227 ctx->ddr_end = rsrc->end;
228 dev_info(ctx->dev, "DDR base: %#x", ctx->ddr_base);
229 ctx->ddr = devm_ioremap_nocache(ctx->dev, ctx->ddr_base,
230 resource_size(rsrc));
232 dev_err(ctx->dev, "unable to map DDR\n");
237 ctx->irq_num = platform_get_irq(pdev,
238 ctx->pdata->res_info->acpi_ipc_irq_index);
243 static int is_byt_cr(struct device *dev, bool *bytcr)
247 if (IS_ENABLED(CONFIG_IOSF_MBI)) {
248 static const struct x86_cpu_id cpu_ids[] = {
249 { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
254 if (!x86_match_cpu(cpu_ids) || !iosf_mbi_available()) {
259 status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
260 MBI_REG_READ, /* 0x10 */
261 0x006, /* BIOS_CONFIG */
265 dev_err(dev, "could not read PUNIT BIOS_CONFIG\n");
267 /* bits 26:27 mirror PMIC options */
268 bios_status = (bios_status >> 26) & 3;
270 if ((bios_status == 1) || (bios_status == 3))
273 dev_info(dev, "BYT-CR not detected\n");
276 dev_info(dev, "IOSF_MBI not enabled, no BYT-CR detection\n");
282 static int sst_acpi_probe(struct platform_device *pdev)
284 struct device *dev = &pdev->dev;
286 struct intel_sst_drv *ctx;
287 const struct acpi_device_id *id;
288 struct sst_acpi_mach *mach;
289 struct platform_device *mdev;
290 struct platform_device *plat_dev;
291 struct sst_platform_info *pdata;
295 id = acpi_match_device(dev->driver->acpi_match_table, dev);
298 dev_dbg(dev, "for %s\n", id->id);
300 mach = (struct sst_acpi_mach *)id->driver_data;
301 mach = sst_acpi_find_machine(mach);
303 dev_err(dev, "No matching machine driver found\n");
306 if (mach->machine_quirk)
307 mach = mach->machine_quirk(mach);
311 ret = kstrtouint(id->id, 16, &dev_id);
313 dev_err(dev, "Unique device id conversion error: %d\n", ret);
317 dev_dbg(dev, "ACPI device id: %x\n", dev_id);
319 ret = sst_alloc_drv_context(&ctx, dev, dev_id);
323 ret = is_byt_cr(dev, &bytcr);
324 if (!((ret < 0) || (bytcr == false))) {
325 dev_info(dev, "Detected Baytrail-CR platform\n");
327 /* override resource info */
328 byt_rvp_platform_data.res_info = &bytcr_res_info;
331 plat_dev = platform_device_register_data(dev, pdata->platform, -1,
333 if (IS_ERR(plat_dev)) {
334 dev_err(dev, "Failed to create machine device: %s\n",
336 return PTR_ERR(plat_dev);
340 * Create platform device for sst machine driver,
341 * pass machine info as pdata
343 mdev = platform_device_register_data(dev, mach->drv_name, -1,
344 (const void *)mach, sizeof(*mach));
346 dev_err(dev, "Failed to create machine device: %s\n",
348 return PTR_ERR(mdev);
351 /* Fill sst platform data */
353 strcpy(ctx->firmware_name, mach->fw_filename);
355 ret = sst_platform_get_resources(ctx);
359 ret = sst_context_init(ctx);
363 /* need to save shim registers in BYT */
364 ctx->shim_regs64 = devm_kzalloc(ctx->dev, sizeof(*ctx->shim_regs64),
366 if (!ctx->shim_regs64) {
371 sst_configure_runtime_pm(ctx);
372 platform_set_drvdata(pdev, ctx);
376 sst_context_cleanup(ctx);
377 platform_set_drvdata(pdev, NULL);
378 dev_err(ctx->dev, "failed with %d\n", ret);
383 * intel_sst_remove - remove function
385 * @pdev: platform device structure
387 * This function is called by OS when a device is unloaded
388 * This frees the interrupt etc
390 static int sst_acpi_remove(struct platform_device *pdev)
392 struct intel_sst_drv *ctx;
394 ctx = platform_get_drvdata(pdev);
395 sst_context_cleanup(ctx);
396 platform_set_drvdata(pdev, NULL);
400 static unsigned long cht_machine_id;
402 #define CHT_SURFACE_MACH 1
403 #define BYT_THINKPAD_10 2
405 static int cht_surface_quirk_cb(const struct dmi_system_id *id)
407 cht_machine_id = CHT_SURFACE_MACH;
411 static int byt_thinkpad10_quirk_cb(const struct dmi_system_id *id)
413 cht_machine_id = BYT_THINKPAD_10;
418 static const struct dmi_system_id byt_table[] = {
420 .callback = byt_thinkpad10_quirk_cb,
422 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
423 DMI_MATCH(DMI_PRODUCT_NAME, "20C3001VHH"),
429 static const struct dmi_system_id cht_table[] = {
431 .callback = cht_surface_quirk_cb,
433 DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
434 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
441 static struct sst_acpi_mach cht_surface_mach = {
442 "10EC5640", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
443 &chv_platform_data };
445 static struct sst_acpi_mach byt_thinkpad_10 = {
446 "10EC5640", "cht-bsw-rt5672", "intel/fw_sst_0f28.bin", "cht-bsw", NULL,
447 &byt_rvp_platform_data };
449 static struct sst_acpi_mach *cht_quirk(void *arg)
451 struct sst_acpi_mach *mach = arg;
453 dmi_check_system(cht_table);
455 if (cht_machine_id == CHT_SURFACE_MACH)
456 return &cht_surface_mach;
461 static struct sst_acpi_mach *byt_quirk(void *arg)
463 struct sst_acpi_mach *mach = arg;
465 dmi_check_system(byt_table);
467 if (cht_machine_id == BYT_THINKPAD_10)
468 return &byt_thinkpad_10;
474 static struct sst_acpi_mach sst_acpi_bytcr[] = {
475 {"10EC5640", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", byt_quirk,
476 &byt_rvp_platform_data },
477 {"10EC5642", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
478 &byt_rvp_platform_data },
479 {"INTCCFFD", "bytcr_rt5640", "intel/fw_sst_0f28.bin", "bytcr_rt5640", NULL,
480 &byt_rvp_platform_data },
481 {"10EC5651", "bytcr_rt5651", "intel/fw_sst_0f28.bin", "bytcr_rt5651", NULL,
482 &byt_rvp_platform_data },
483 /* some Baytrail platforms rely on RT5645, use CHT machine driver */
484 {"10EC5645", "cht-bsw-rt5645", "intel/fw_sst_0f28.bin", "cht-bsw", NULL,
485 &byt_rvp_platform_data },
486 {"10EC5648", "cht-bsw-rt5645", "intel/fw_sst_0f28.bin", "cht-bsw", NULL,
487 &byt_rvp_platform_data },
492 /* Cherryview-based platforms: CherryTrail and Braswell */
493 static struct sst_acpi_mach sst_acpi_chv[] = {
494 {"10EC5670", "cht-bsw-rt5672", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
495 &chv_platform_data },
496 {"10EC5672", "cht-bsw-rt5672", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
497 &chv_platform_data },
498 {"10EC5645", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
499 &chv_platform_data },
500 {"10EC5650", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
501 &chv_platform_data },
502 {"10EC3270", "cht-bsw-rt5645", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
503 &chv_platform_data },
505 {"193C9890", "cht-bsw-max98090", "intel/fw_sst_22a8.bin", "cht-bsw", NULL,
506 &chv_platform_data },
507 /* some CHT-T platforms rely on RT5640, use Baytrail machine driver */
508 {"10EC5640", "bytcr_rt5640", "intel/fw_sst_22a8.bin", "bytcr_rt5640", cht_quirk,
509 &chv_platform_data },
510 {"10EC3276", "bytcr_rt5640", "intel/fw_sst_22a8.bin", "bytcr_rt5640", NULL,
511 &chv_platform_data },
512 /* some CHT-T platforms rely on RT5651, use Baytrail machine driver */
513 {"10EC5651", "bytcr_rt5651", "intel/fw_sst_22a8.bin", "bytcr_rt5651", NULL,
514 &chv_platform_data },
518 static const struct acpi_device_id sst_acpi_ids[] = {
519 { "80860F28", (unsigned long)&sst_acpi_bytcr},
520 { "808622A8", (unsigned long) &sst_acpi_chv},
524 MODULE_DEVICE_TABLE(acpi, sst_acpi_ids);
526 static struct platform_driver sst_acpi_driver = {
528 .name = "intel_sst_acpi",
529 .acpi_match_table = ACPI_PTR(sst_acpi_ids),
532 .probe = sst_acpi_probe,
533 .remove = sst_acpi_remove,
536 module_platform_driver(sst_acpi_driver);
538 MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine ACPI Driver");
539 MODULE_AUTHOR("Ramesh Babu K V");
540 MODULE_AUTHOR("Omair Mohammed Abdullah");
541 MODULE_LICENSE("GPL v2");