2 * skl.h - HD Audio skylake defintions.
4 * Copyright (C) 2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
21 #ifndef __SOUND_SOC_SKL_H
22 #define __SOUND_SOC_SKL_H
24 #include <sound/hda_register.h>
25 #include <sound/hdaudio_ext.h>
28 #define SKL_SUSPEND_DELAY 2000
30 /* Vendor Specific Registers */
31 #define AZX_REG_VS_EM1 0x1000
32 #define AZX_REG_VS_INRC 0x1004
33 #define AZX_REG_VS_OUTRC 0x1008
34 #define AZX_REG_VS_FIFOTRK 0x100C
35 #define AZX_REG_VS_FIFOTRK2 0x1010
36 #define AZX_REG_VS_EM2 0x1030
37 #define AZX_REG_VS_EM3L 0x1038
38 #define AZX_REG_VS_EM3U 0x103C
39 #define AZX_REG_VS_EM4L 0x1040
40 #define AZX_REG_VS_EM4U 0x1044
41 #define AZX_REG_VS_LTRC 0x1048
42 #define AZX_REG_VS_D0I3C 0x104A
43 #define AZX_REG_VS_PCE 0x104B
44 #define AZX_REG_VS_L2MAGC 0x1050
45 #define AZX_REG_VS_L2LAHPT 0x1054
46 #define AZX_REG_VS_SDXDPIB_XBASE 0x1084
47 #define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
48 #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
49 #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
51 #define AZX_PCIREG_PGCTL 0x44
52 #define AZX_PGCTL_LSRMD_MASK (1 << 4)
53 #define AZX_PCIREG_CGCTL 0x48
54 #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
55 /* D0I3C Register fields */
56 #define AZX_REG_VS_D0I3C_CIP 0x1 /* Command in progress */
57 #define AZX_REG_VS_D0I3C_I3 0x4 /* D0i3 enable */
59 struct skl_dsp_resource {
67 struct hdac_ext_bus ebus;
70 unsigned int init_failed:1; /* delayed init failed */
71 struct platform_device *dmic_dev;
72 struct platform_device *i2s_dev;
73 struct snd_soc_platform *platform;
75 struct nhlt_acpi_table *nhlt; /* nhlt ptr */
76 struct skl_sst *skl_sst; /* sst skl ctx */
78 struct skl_dsp_resource resource;
79 struct list_head ppl_list;
80 struct list_head bind_list;
84 unsigned short pci_id;
85 const struct firmware *tplg;
90 #define skl_to_ebus(s) (&(s)->ebus)
91 #define ebus_to_skl(sbus) \
92 container_of(sbus, struct skl, sbus)
94 /* to pass dai dma data */
95 struct skl_dma_params {
100 /* to pass dmic data */
101 struct skl_machine_pdata {
107 struct skl_dsp_loader_ops (*loader_ops)(void);
108 int (*init)(struct device *dev, void __iomem *mmio_base,
109 int irq, const char *fw_name,
110 struct skl_dsp_loader_ops loader_ops,
111 struct skl_sst **skl_sst);
112 int (*init_fw)(struct device *dev, struct skl_sst *ctx);
113 void (*cleanup)(struct device *dev, struct skl_sst *ctx);
116 int skl_platform_unregister(struct device *dev);
117 int skl_platform_register(struct device *dev);
119 struct nhlt_acpi_table *skl_nhlt_init(struct device *dev);
120 void skl_nhlt_free(struct nhlt_acpi_table *addr);
121 struct nhlt_specific_cfg *skl_get_ep_blob(struct skl *skl, u32 instance,
122 u8 link_type, u8 s_fmt, u8 no_ch,
123 u32 s_rate, u8 dirn, u8 dev_type);
125 int skl_get_dmic_geo(struct skl *skl);
126 int skl_nhlt_update_topology_bin(struct skl *skl);
127 int skl_init_dsp(struct skl *skl);
128 int skl_free_dsp(struct skl *skl);
129 int skl_suspend_late_dsp(struct skl *skl);
130 int skl_suspend_dsp(struct skl *skl);
131 int skl_resume_dsp(struct skl *skl);
132 void skl_cleanup_resources(struct skl *skl);
133 const struct skl_dsp_ops *skl_get_dsp_ops(int pci_id);
134 void skl_update_d0i3c(struct device *dev, bool enable);
135 int skl_nhlt_create_sysfs(struct skl *skl);
136 void skl_nhlt_remove_sysfs(struct skl *skl);
138 #endif /* __SOUND_SOC_SKL_H */