2 * Intel Smart Sound Technology (SST) Core
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __SOUND_SOC_SST_DSP_H
18 #define __SOUND_SOC_SST_DSP_H
20 #include <linux/kernel.h>
21 #include <linux/types.h>
22 #include <linux/interrupt.h>
25 #define SST_DEV_ID_LYNX_POINT 0x33C8
26 #define SST_DEV_ID_WILDCAT_POINT 0x3438
27 #define SST_DEV_ID_BYT 0x0F28
29 /* Supported SST DMA Devices */
30 #define SST_DMA_TYPE_DW 1
31 #define SST_DMA_TYPE_MID 2
33 /* autosuspend delay 5s*/
34 #define SST_RUNTIME_SUSPEND_DELAY (5 * 1000)
36 /* SST Shim register map
37 * The register naming can differ between products. Some products also
38 * contain extra functionality.
47 #define SST_IPCX 0x38 /* IPC IA -> SST */
48 #define SST_IPCD 0x40 /* IPC SST -> IA */
49 #define SST_ISRSC 0x48
50 #define SST_ISRLPESC 0x50
51 #define SST_IMRSC 0x58
52 #define SST_IMRLPESC 0x60
53 #define SST_IPCSC 0x68
54 #define SST_IPCLPESC 0x70
55 #define SST_CLKCTL 0x78
60 #define SST_SHIM_BEGIN SST_CSR
61 #define SST_SHIM_END SST_HDMC
65 #define SST_SHIM_SIZE 0x100
66 #define SST_PWMCTRL 0x1000
68 /* SST Shim Register bits
69 * The register bit naming can differ between products. Some products also
70 * contain extra functionality.
74 #define SST_CSR_RST (0x1 << 1)
75 #define SST_CSR_SBCS0 (0x1 << 2)
76 #define SST_CSR_SBCS1 (0x1 << 3)
77 #define SST_CSR_DCS(x) (x << 4)
78 #define SST_CSR_DCS_MASK (0x7 << 4)
79 #define SST_CSR_STALL (0x1 << 10)
80 #define SST_CSR_S0IOCS (0x1 << 21)
81 #define SST_CSR_S1IOCS (0x1 << 23)
82 #define SST_CSR_LPCS (0x1 << 31)
83 #define SST_CSR_24MHZ_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1 | SST_CSR_LPCS)
84 #define SST_CSR_24MHZ_NO_LPCS (SST_CSR_SBCS0 | SST_CSR_SBCS1)
85 #define SST_BYT_CSR_RST (0x1 << 0)
86 #define SST_BYT_CSR_VECTOR_SEL (0x1 << 1)
87 #define SST_BYT_CSR_STALL (0x1 << 2)
88 #define SST_BYT_CSR_PWAITMODE (0x1 << 3)
91 #define SST_ISRX_BUSY (0x1 << 1)
92 #define SST_ISRX_DONE (0x1 << 0)
93 #define SST_BYT_ISRX_REQUEST (0x1 << 1)
96 #define SST_ISRD_BUSY (0x1 << 1)
97 #define SST_ISRD_DONE (0x1 << 0)
100 #define SST_IMRX_BUSY (0x1 << 1)
101 #define SST_IMRX_DONE (0x1 << 0)
102 #define SST_BYT_IMRX_REQUEST (0x1 << 1)
105 #define SST_IMRD_DONE (0x1 << 0)
106 #define SST_IMRD_BUSY (0x1 << 1)
107 #define SST_IMRD_SSP0 (0x1 << 16)
108 #define SST_IMRD_DMAC0 (0x1 << 21)
109 #define SST_IMRD_DMAC1 (0x1 << 22)
110 #define SST_IMRD_DMAC (SST_IMRD_DMAC0 | SST_IMRD_DMAC1)
113 #define SST_IPCX_DONE (0x1 << 30)
114 #define SST_IPCX_BUSY (0x1 << 31)
115 #define SST_BYT_IPCX_DONE ((u64)0x1 << 62)
116 #define SST_BYT_IPCX_BUSY ((u64)0x1 << 63)
119 #define SST_IPCD_DONE (0x1 << 30)
120 #define SST_IPCD_BUSY (0x1 << 31)
121 #define SST_BYT_IPCD_DONE ((u64)0x1 << 62)
122 #define SST_BYT_IPCD_BUSY ((u64)0x1 << 63)
125 #define SST_CLKCTL_SMOS(x) (x << 24)
126 #define SST_CLKCTL_MASK (3 << 24)
127 #define SST_CLKCTL_DCPLCG (1 << 18)
128 #define SST_CLKCTL_SCOE1 (1 << 17)
129 #define SST_CLKCTL_SCOE0 (1 << 16)
132 #define SST_CSR2_SDFD_SSP0 (1 << 1)
133 #define SST_CSR2_SDFD_SSP1 (1 << 2)
136 #define SST_LTRC_VAL(x) (x << 0)
139 #define SST_HMDC_HDDA0(x) (x << 0)
140 #define SST_HMDC_HDDA1(x) (x << 7)
141 #define SST_HMDC_HDDA_E0_CH0 1
142 #define SST_HMDC_HDDA_E0_CH1 2
143 #define SST_HMDC_HDDA_E0_CH2 4
144 #define SST_HMDC_HDDA_E0_CH3 8
145 #define SST_HMDC_HDDA_E1_CH0 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH0)
146 #define SST_HMDC_HDDA_E1_CH1 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH1)
147 #define SST_HMDC_HDDA_E1_CH2 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH2)
148 #define SST_HMDC_HDDA_E1_CH3 SST_HMDC_HDDA1(SST_HMDC_HDDA_E0_CH3)
149 #define SST_HMDC_HDDA_E0_ALLCH (SST_HMDC_HDDA_E0_CH0 | SST_HMDC_HDDA_E0_CH1 | \
150 SST_HMDC_HDDA_E0_CH2 | SST_HMDC_HDDA_E0_CH3)
151 #define SST_HMDC_HDDA_E1_ALLCH (SST_HMDC_HDDA_E1_CH0 | SST_HMDC_HDDA_E1_CH1 | \
152 SST_HMDC_HDDA_E1_CH2 | SST_HMDC_HDDA_E1_CH3)
155 /* SST Vendor Defined Registers and bits */
156 #define SST_VDRTCTL0 0xa0
157 #define SST_VDRTCTL1 0xa4
158 #define SST_VDRTCTL2 0xa8
159 #define SST_VDRTCTL3 0xaC
162 #define SST_VDRTCL0_D3PGD (1 << 0)
163 #define SST_VDRTCL0_D3SRAMPGD (1 << 1)
164 #define SST_VDRTCL0_DSRAMPGE_SHIFT 12
165 #define SST_VDRTCL0_DSRAMPGE_MASK (0xfffff << SST_VDRTCL0_DSRAMPGE_SHIFT)
166 #define SST_VDRTCL0_ISRAMPGE_SHIFT 2
167 #define SST_VDRTCL0_ISRAMPGE_MASK (0x3ff << SST_VDRTCL0_ISRAMPGE_SHIFT)
170 #define SST_VDRTCL2_DCLCGE (1 << 1)
171 #define SST_VDRTCL2_DTCGE (1 << 10)
172 #define SST_VDRTCL2_APLLSE_MASK (1 << 31)
175 #define SST_PMCS 0x84
176 #define SST_PMCS_PS_MASK 0x3
183 * This structure is populated by the SST core driver.
185 struct sst_dsp_device {
186 /* Mandatory fields */
188 irqreturn_t (*thread)(int irq, void *context);
189 void *thread_context;
206 const struct firmware *fw;
212 struct device *dma_dev;
220 struct sst_dsp *sst_dsp_new(struct device *dev,
221 struct sst_dsp_device *sst_dev, struct sst_pdata *pdata);
222 void sst_dsp_free(struct sst_dsp *sst);
224 /* SHIM Read / Write */
225 void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
226 u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
227 int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
228 u32 mask, u32 value);
229 void sst_dsp_shim_write64(struct sst_dsp *sst, u32 offset, u64 value);
230 u64 sst_dsp_shim_read64(struct sst_dsp *sst, u32 offset);
231 int sst_dsp_shim_update_bits64(struct sst_dsp *sst, u32 offset,
232 u64 mask, u64 value);
234 /* SHIM Read / Write Unlocked for callers already holding sst lock */
235 void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
236 u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
237 int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
238 u32 mask, u32 value);
239 void sst_dsp_shim_write64_unlocked(struct sst_dsp *sst, u32 offset, u64 value);
240 u64 sst_dsp_shim_read64_unlocked(struct sst_dsp *sst, u32 offset);
241 int sst_dsp_shim_update_bits64_unlocked(struct sst_dsp *sst, u32 offset,
242 u64 mask, u64 value);
244 /* Internal generic low-level SST IO functions - can be overidden */
245 void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
246 u32 sst_shim32_read(void __iomem *addr, u32 offset);
247 void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
248 u64 sst_shim32_read64(void __iomem *addr, u32 offset);
249 void sst_memcpy_toio_32(struct sst_dsp *sst,
250 void __iomem *dest, void *src, size_t bytes);
251 void sst_memcpy_fromio_32(struct sst_dsp *sst,
252 void *dest, void __iomem *src, size_t bytes);
254 /* DSP reset & boot */
255 void sst_dsp_reset(struct sst_dsp *sst);
256 int sst_dsp_boot(struct sst_dsp *sst);
257 int sst_dsp_wake(struct sst_dsp *sst);
258 void sst_dsp_sleep(struct sst_dsp *sst);
259 void sst_dsp_stall(struct sst_dsp *sst);
262 int sst_dsp_dma_get_channel(struct sst_dsp *dsp, int chan_id);
263 void sst_dsp_dma_put_channel(struct sst_dsp *dsp);
264 int sst_dsp_dma_copyfrom(struct sst_dsp *sst, dma_addr_t dest_addr,
265 dma_addr_t src_addr, size_t size);
266 int sst_dsp_dma_copyto(struct sst_dsp *sst, dma_addr_t dest_addr,
267 dma_addr_t src_addr, size_t size);
270 void sst_dsp_ipc_msg_tx(struct sst_dsp *dsp, u32 msg);
271 u32 sst_dsp_ipc_msg_rx(struct sst_dsp *dsp);
273 /* Mailbox management */
274 int sst_dsp_mailbox_init(struct sst_dsp *dsp, u32 inbox_offset,
275 size_t inbox_size, u32 outbox_offset, size_t outbox_size);
276 void sst_dsp_inbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
277 void sst_dsp_inbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
278 void sst_dsp_outbox_write(struct sst_dsp *dsp, void *message, size_t bytes);
279 void sst_dsp_outbox_read(struct sst_dsp *dsp, void *message, size_t bytes);
280 void sst_dsp_mailbox_dump(struct sst_dsp *dsp, size_t bytes);
283 void sst_dsp_dump(struct sst_dsp *sst);