2 * Intel SST Haswell/Broadwell IPC Support
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/device.h>
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/platform_device.h>
29 #include <linux/kthread.h>
30 #include <linux/firmware.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/debugfs.h>
33 #include <linux/pm_runtime.h>
34 #include <sound/asound.h>
36 #include "sst-haswell-ipc.h"
38 #include "sst-dsp-priv.h"
40 /* Global Message - Generic */
41 #define IPC_GLB_TYPE_SHIFT 24
42 #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
43 #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
45 /* Global Message - Reply */
46 #define IPC_GLB_REPLY_SHIFT 0
47 #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
48 #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
50 /* Stream Message - Generic */
51 #define IPC_STR_TYPE_SHIFT 20
52 #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
53 #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
54 #define IPC_STR_ID_SHIFT 16
55 #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
56 #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
58 /* Stream Message - Reply */
59 #define IPC_STR_REPLY_SHIFT 0
60 #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
62 /* Stream Stage Message - Generic */
63 #define IPC_STG_TYPE_SHIFT 12
64 #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
65 #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
66 #define IPC_STG_ID_SHIFT 10
67 #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
68 #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
70 /* Stream Stage Message - Reply */
71 #define IPC_STG_REPLY_SHIFT 0
72 #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
74 /* Debug Log Message - Generic */
75 #define IPC_LOG_OP_SHIFT 20
76 #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
77 #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
78 #define IPC_LOG_ID_SHIFT 16
79 #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
80 #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
83 #define IPC_MODULE_OPERATION_SHIFT 20
84 #define IPC_MODULE_OPERATION_MASK (0xf << IPC_MODULE_OPERATION_SHIFT)
85 #define IPC_MODULE_OPERATION(x) (x << IPC_MODULE_OPERATION_SHIFT)
87 #define IPC_MODULE_ID_SHIFT 16
88 #define IPC_MODULE_ID_MASK (0xf << IPC_MODULE_ID_SHIFT)
89 #define IPC_MODULE_ID(x) (x << IPC_MODULE_ID_SHIFT)
91 /* IPC message timeout (msecs) */
92 #define IPC_TIMEOUT_MSECS 300
93 #define IPC_BOOT_MSECS 200
94 #define IPC_MSG_WAIT 0
95 #define IPC_MSG_NOWAIT 1
97 /* Firmware Ready Message */
98 #define IPC_FW_READY (0x1 << 29)
99 #define IPC_STATUS_MASK (0x3 << 30)
101 #define IPC_EMPTY_LIST_SIZE 8
102 #define IPC_MAX_STREAMS 4
105 #define IPC_MAX_MAILBOX_BYTES 256
107 #define INVALID_STREAM_HW_ID 0xffffffff
109 /* Global Message - Types and Replies */
111 IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
112 IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
113 IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
114 IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
115 IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
116 IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
117 /* Request to store firmware context during D0->D3 transition */
118 IPC_GLB_REQUEST_DUMP = 7,
119 /* Request to restore firmware context during D3->D0 transition */
120 IPC_GLB_RESTORE_CONTEXT = 8,
121 IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
122 IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
123 IPC_GLB_SHORT_REPLY = 11,
124 IPC_GLB_ENTER_DX_STATE = 12,
125 IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
126 IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
127 IPC_GLB_MODULE_OPERATION = 15, /* Message to loadable fw module */
128 IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
129 IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
133 IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
134 IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
135 IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
136 IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
137 IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
138 IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
139 IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
140 IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
141 IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
142 IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
143 IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
146 enum ipc_module_operation {
147 IPC_MODULE_NOTIFICATION = 0,
148 IPC_MODULE_ENABLE = 1,
149 IPC_MODULE_DISABLE = 2,
150 IPC_MODULE_GET_PARAMETER = 3,
151 IPC_MODULE_SET_PARAMETER = 4,
152 IPC_MODULE_GET_INFO = 5,
153 IPC_MODULE_MAX_MESSAGE
156 /* Stream Message - Types */
157 enum ipc_str_operation {
161 IPC_STR_STAGE_MESSAGE = 3,
162 IPC_STR_NOTIFICATION = 4,
166 /* Stream Stage Message Types */
167 enum ipc_stg_operation {
168 IPC_STG_GET_VOLUME = 0,
170 IPC_STG_SET_WRITE_POSITION,
171 IPC_STG_SET_FX_ENABLE,
172 IPC_STG_SET_FX_DISABLE,
173 IPC_STG_SET_FX_GET_PARAM,
174 IPC_STG_SET_FX_SET_PARAM,
175 IPC_STG_SET_FX_GET_INFO,
176 IPC_STG_MUTE_LOOPBACK,
180 /* Stream Stage Message Types For Notification*/
181 enum ipc_stg_operation_notify {
182 IPC_POSITION_CHANGED = 0,
187 enum ipc_glitch_type {
188 IPC_GLITCH_UNDERRUN = 1,
189 IPC_GLITCH_DECODER_ERROR,
190 IPC_GLITCH_DOUBLED_WRITE_POS,
195 enum ipc_debug_operation {
196 IPC_DEBUG_ENABLE_LOG = 0,
197 IPC_DEBUG_DISABLE_LOG = 1,
198 IPC_DEBUG_REQUEST_LOG_DUMP = 2,
199 IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
200 IPC_DEBUG_MAX_DEBUG_LOG
204 struct sst_hsw_ipc_fw_ready {
210 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
211 } __attribute__((packed));
214 struct list_head list;
217 /* direction wrt host CPU */
218 char tx_data[IPC_MAX_MAILBOX_BYTES];
220 char rx_data[IPC_MAX_MAILBOX_BYTES];
223 wait_queue_head_t waitq;
230 struct sst_hsw_stream;
233 /* Stream infomation */
234 struct sst_hsw_stream {
236 struct sst_hsw_ipc_stream_alloc_req request;
237 struct sst_hsw_ipc_stream_alloc_reply reply;
238 struct sst_hsw_ipc_stream_free_req free_req;
241 u32 mute_volume[SST_HSW_NO_CHANNELS];
242 u32 mute[SST_HSW_NO_CHANNELS];
250 /* Notification work */
251 struct work_struct notify_work;
254 /* Position info from DSP */
255 struct sst_hsw_ipc_stream_set_position wpos;
256 struct sst_hsw_ipc_stream_get_position rpos;
257 struct sst_hsw_ipc_stream_glitch_position glitch;
260 struct sst_hsw_ipc_volume_req vol_req;
262 /* driver callback */
263 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
266 /* record the fw read position when playback */
267 snd_pcm_uframes_t old_position;
269 struct list_head node;
272 /* FW log ring information */
273 struct sst_hsw_log_stream {
275 unsigned char *dma_area;
276 unsigned char *ring_descr;
280 /* Notification work */
281 struct work_struct notify_work;
282 wait_queue_head_t readers_wait_q;
283 struct mutex rw_mutex;
290 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
295 /* SST Haswell IPC data */
299 struct platform_device *pdev_pcm;
302 struct sst_hsw_ipc_fw_ready fw_ready;
303 struct sst_hsw_ipc_fw_version version;
305 struct sst_fw *sst_fw;
308 struct list_head stream_list;
311 struct sst_hsw_ipc_stream_info_reply mixer_info;
312 enum sst_hsw_volume_curve curve_type;
314 u32 mute[SST_HSW_NO_CHANNELS];
315 u32 mute_volume[SST_HSW_NO_CHANNELS];
318 struct sst_hsw_ipc_dx_reply dx;
320 dma_addr_t dx_context_paddr;
323 wait_queue_head_t boot_wait;
328 struct list_head tx_list;
329 struct list_head rx_list;
330 struct list_head empty_list;
331 wait_queue_head_t wait_txq;
332 struct task_struct *tx_thread;
333 struct kthread_worker kworker;
334 struct kthread_work kwork;
336 struct ipc_message *msg;
339 struct sst_hsw_log_stream log_stream;
341 /* flags bit field to track module state when resume from RTD3,
342 * each bit represent state (enabled/disabled) of single module */
343 u32 enabled_modules_rtd3;
345 /* buffer to store parameter lines */
346 u32 param_idx_w; /* write index */
347 u32 param_idx_r; /* read index */
348 u8 param_buf[WAVES_PARAM_LINES][WAVES_PARAM_COUNT];
351 #define CREATE_TRACE_POINTS
352 #include <trace/events/hswadsp.h>
354 static inline u32 msg_get_global_type(u32 msg)
356 return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
359 static inline u32 msg_get_global_reply(u32 msg)
361 return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
364 static inline u32 msg_get_stream_type(u32 msg)
366 return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
369 static inline u32 msg_get_stage_type(u32 msg)
371 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
374 static inline u32 msg_get_stream_id(u32 msg)
376 return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
379 static inline u32 msg_get_notify_reason(u32 msg)
381 return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
384 static inline u32 msg_get_module_operation(u32 msg)
386 return (msg & IPC_MODULE_OPERATION_MASK) >> IPC_MODULE_OPERATION_SHIFT;
389 static inline u32 msg_get_module_id(u32 msg)
391 return (msg & IPC_MODULE_ID_MASK) >> IPC_MODULE_ID_SHIFT;
394 u32 create_channel_map(enum sst_hsw_channel_config config)
397 case SST_HSW_CHANNEL_CONFIG_MONO:
398 return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
399 case SST_HSW_CHANNEL_CONFIG_STEREO:
400 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
401 | (SST_HSW_CHANNEL_RIGHT << 4));
402 case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
403 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
404 | (SST_HSW_CHANNEL_RIGHT << 4)
405 | (SST_HSW_CHANNEL_LFE << 8 ));
406 case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
407 return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
408 | (SST_HSW_CHANNEL_CENTER << 4)
409 | (SST_HSW_CHANNEL_RIGHT << 8));
410 case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
411 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
412 | (SST_HSW_CHANNEL_CENTER << 4)
413 | (SST_HSW_CHANNEL_RIGHT << 8)
414 | (SST_HSW_CHANNEL_LFE << 12));
415 case SST_HSW_CHANNEL_CONFIG_QUATRO:
416 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
417 | (SST_HSW_CHANNEL_RIGHT << 4)
418 | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
419 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
420 case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
421 return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
422 | (SST_HSW_CHANNEL_CENTER << 4)
423 | (SST_HSW_CHANNEL_RIGHT << 8)
424 | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
425 case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
426 return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
427 | (SST_HSW_CHANNEL_CENTER << 4)
428 | (SST_HSW_CHANNEL_RIGHT << 8)
429 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
430 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
431 case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
432 return (0xFF000000 | SST_HSW_CHANNEL_CENTER
433 | (SST_HSW_CHANNEL_LEFT << 4)
434 | (SST_HSW_CHANNEL_RIGHT << 8)
435 | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
436 | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
437 | (SST_HSW_CHANNEL_LFE << 20));
438 case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
439 return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
440 | (SST_HSW_CHANNEL_LEFT << 4));
446 static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
449 struct sst_hsw_stream *stream;
451 list_for_each_entry(stream, &hsw->stream_list, node) {
452 if (stream->reply.stream_hw_id == stream_id)
459 static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
461 struct sst_dsp *sst = hsw->dsp;
462 u32 isr, ipcd, imrx, ipcx;
464 ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
465 isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
466 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
467 imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
469 dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
470 text, ipcx, isr, ipcd, imrx);
473 /* locks held by caller */
474 static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
476 struct ipc_message *msg = NULL;
478 if (!list_empty(&hsw->empty_list)) {
479 msg = list_first_entry(&hsw->empty_list, struct ipc_message,
481 list_del(&msg->list);
487 static void ipc_tx_msgs(struct kthread_work *work)
489 struct sst_hsw *hsw =
490 container_of(work, struct sst_hsw, kwork);
491 struct ipc_message *msg;
495 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
497 if (list_empty(&hsw->tx_list) || hsw->pending) {
498 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
502 /* if the DSP is busy, we will TX messages after IRQ.
503 * also postpone if we are in the middle of procesing completion irq*/
504 ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
505 if (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE)) {
506 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
510 msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
512 list_move(&msg->list, &hsw->rx_list);
514 /* send the message */
515 sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
516 sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
518 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
521 /* locks held by caller */
522 static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
524 msg->complete = true;
525 trace_ipc_reply("completed", msg->header);
528 list_add_tail(&msg->list, &hsw->empty_list);
530 wake_up(&msg->waitq);
533 static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
539 /* wait for DSP completion (in all cases atm inc pending) */
540 ret = wait_event_timeout(msg->waitq, msg->complete,
541 msecs_to_jiffies(IPC_TIMEOUT_MSECS));
543 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
545 ipc_shim_dbg(hsw, "message timeout");
547 trace_ipc_error("error message timeout for", msg->header);
548 list_del(&msg->list);
552 /* copy the data returned from DSP */
554 memcpy(rx_data, msg->rx_data, msg->rx_size);
558 list_add_tail(&msg->list, &hsw->empty_list);
559 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
563 static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
564 size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
566 struct ipc_message *msg;
569 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
571 msg = msg_get_empty(hsw);
573 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
578 memcpy(msg->tx_data, tx_data, tx_bytes);
580 msg->header = header;
581 msg->tx_size = tx_bytes;
582 msg->rx_size = rx_bytes;
585 msg->pending = false;
586 msg->complete = false;
588 list_add_tail(&msg->list, &hsw->tx_list);
589 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
591 queue_kthread_work(&hsw->kworker, &hsw->kwork);
594 return tx_wait_done(hsw, msg, rx_data);
599 static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
600 void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
602 return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
606 static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
607 void *tx_data, size_t tx_bytes)
609 return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
612 static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
614 struct sst_hsw_ipc_fw_ready fw_ready;
616 u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
617 char *tmp[5], *pinfo;
620 offset = (header & 0x1FFFFFFF) << 3;
622 dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
625 /* copy data from the DSP FW ready offset */
626 sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
628 sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
629 fw_ready.inbox_size, fw_ready.outbox_offset,
630 fw_ready.outbox_size);
632 hsw->boot_complete = true;
633 wake_up(&hsw->boot_wait);
635 dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
636 fw_ready.inbox_offset, fw_ready.inbox_size);
637 dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
638 fw_ready.outbox_offset, fw_ready.outbox_size);
639 if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
640 fw_ready.fw_info[fw_ready.fw_info_size] = 0;
641 dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
643 /* log the FW version info got from the mailbox here. */
644 memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
646 for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
647 tmp[i] = strsep(&pinfo, " ");
648 dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
649 "version: %s.%s, build %s, source commit id: %s\n",
650 tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
654 static void hsw_notification_work(struct work_struct *work)
656 struct sst_hsw_stream *stream = container_of(work,
657 struct sst_hsw_stream, notify_work);
658 struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
659 struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
660 struct sst_hsw *hsw = stream->hsw;
663 reason = msg_get_notify_reason(stream->header);
667 trace_ipc_notification("DSP stream under/overrun",
668 stream->reply.stream_hw_id);
669 sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
671 dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
672 glitch->glitch_type, glitch->present_pos,
676 case IPC_POSITION_CHANGED:
677 trace_ipc_notification("DSP stream position changed for",
678 stream->reply.stream_hw_id);
679 sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
681 if (stream->notify_position)
682 stream->notify_position(stream, stream->pdata);
686 dev_err(hsw->dev, "error: unknown notification 0x%x\n",
691 /* tell DSP that notification has been handled */
692 sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,
693 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
695 /* unmask busy interrupt */
696 sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
699 static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
701 struct ipc_message *msg;
703 /* clear reply bits & status bits */
704 header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
706 if (list_empty(&hsw->rx_list)) {
707 dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
712 list_for_each_entry(msg, &hsw->rx_list, list) {
713 if (msg->header == header)
720 static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
722 struct sst_hsw_stream *stream;
723 u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
724 u32 stream_id = msg_get_stream_id(header);
725 u32 stream_msg = msg_get_stream_type(header);
727 stream = get_stream_by_id(hsw, stream_id);
731 switch (stream_msg) {
732 case IPC_STR_STAGE_MESSAGE:
733 case IPC_STR_NOTIFICATION:
736 trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
739 stream->running = false;
740 trace_ipc_notification("stream paused",
741 stream->reply.stream_hw_id);
744 stream->running = true;
745 trace_ipc_notification("stream running",
746 stream->reply.stream_hw_id);
751 static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
753 struct ipc_message *msg;
754 u32 reply = msg_get_global_reply(header);
756 trace_ipc_reply("processing -->", header);
758 msg = reply_find_msg(hsw, header);
760 trace_ipc_error("error: can't find message header", header);
764 /* first process the header */
766 case IPC_GLB_REPLY_PENDING:
767 trace_ipc_pending_reply("received", header);
771 case IPC_GLB_REPLY_SUCCESS:
773 trace_ipc_pending_reply("completed", header);
774 sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
776 hsw->pending = false;
778 /* copy data from the DSP */
779 sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
783 /* these will be rare - but useful for debug */
784 case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
785 trace_ipc_error("error: unknown message type", header);
786 msg->errno = -EBADMSG;
788 case IPC_GLB_REPLY_OUT_OF_RESOURCES:
789 trace_ipc_error("error: out of resources", header);
790 msg->errno = -ENOMEM;
792 case IPC_GLB_REPLY_BUSY:
793 trace_ipc_error("error: reply busy", header);
796 case IPC_GLB_REPLY_FAILURE:
797 trace_ipc_error("error: reply failure", header);
798 msg->errno = -EINVAL;
800 case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
801 trace_ipc_error("error: stage uninitialized", header);
802 msg->errno = -EINVAL;
804 case IPC_GLB_REPLY_NOT_FOUND:
805 trace_ipc_error("error: reply not found", header);
806 msg->errno = -EINVAL;
808 case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
809 trace_ipc_error("error: source not started", header);
810 msg->errno = -EINVAL;
812 case IPC_GLB_REPLY_INVALID_REQUEST:
813 trace_ipc_error("error: invalid request", header);
814 msg->errno = -EINVAL;
816 case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
817 trace_ipc_error("error: invalid parameter", header);
818 msg->errno = -EINVAL;
821 trace_ipc_error("error: unknown reply", header);
822 msg->errno = -EINVAL;
826 /* update any stream states */
827 if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
828 hsw_stream_update(hsw, msg);
830 /* wake up and return the error if we have waiters on this message ? */
831 list_del(&msg->list);
832 tx_msg_reply_complete(hsw, msg);
837 static int hsw_module_message(struct sst_hsw *hsw, u32 header)
839 u32 operation, module_id;
842 operation = msg_get_module_operation(header);
843 module_id = msg_get_module_id(header);
844 dev_dbg(hsw->dev, "received module message header: 0x%8.8x\n",
846 dev_dbg(hsw->dev, "operation: 0x%8.8x module_id: 0x%8.8x\n",
847 operation, module_id);
850 case IPC_MODULE_NOTIFICATION:
851 dev_dbg(hsw->dev, "module notification received");
855 handled = hsw_process_reply(hsw, header);
862 static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
864 u32 stream_msg, stream_id, stage_type;
865 struct sst_hsw_stream *stream;
868 stream_msg = msg_get_stream_type(header);
869 stream_id = msg_get_stream_id(header);
870 stage_type = msg_get_stage_type(header);
872 stream = get_stream_by_id(hsw, stream_id);
876 stream->header = header;
878 switch (stream_msg) {
879 case IPC_STR_STAGE_MESSAGE:
880 dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
883 case IPC_STR_NOTIFICATION:
884 schedule_work(&stream->notify_work);
887 /* handle pending message complete request */
888 handled = hsw_process_reply(hsw, header);
895 static int hsw_log_message(struct sst_hsw *hsw, u32 header)
897 u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
898 struct sst_hsw_log_stream *stream = &hsw->log_stream;
901 if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
903 "error: log msg not implemented 0x%8.8x\n", header);
907 mutex_lock(&stream->rw_mutex);
908 stream->last_pos = stream->curr_pos;
910 hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
911 mutex_unlock(&stream->rw_mutex);
913 schedule_work(&stream->notify_work);
918 static int hsw_process_notification(struct sst_hsw *hsw)
920 struct sst_dsp *sst = hsw->dsp;
924 header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
925 type = msg_get_global_type(header);
927 trace_ipc_request("processing -->", header);
929 /* FW Ready is a special case */
930 if (!hsw->boot_complete && header & IPC_FW_READY) {
931 hsw_fw_ready(hsw, header);
936 case IPC_GLB_GET_FW_VERSION:
937 case IPC_GLB_ALLOCATE_STREAM:
938 case IPC_GLB_FREE_STREAM:
939 case IPC_GLB_GET_FW_CAPABILITIES:
940 case IPC_GLB_REQUEST_DUMP:
941 case IPC_GLB_GET_DEVICE_FORMATS:
942 case IPC_GLB_SET_DEVICE_FORMATS:
943 case IPC_GLB_ENTER_DX_STATE:
944 case IPC_GLB_GET_MIXER_STREAM_INFO:
945 case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
946 case IPC_GLB_RESTORE_CONTEXT:
947 case IPC_GLB_SHORT_REPLY:
948 dev_err(hsw->dev, "error: message type %d header 0x%x\n",
951 case IPC_GLB_STREAM_MESSAGE:
952 handled = hsw_stream_message(hsw, header);
954 case IPC_GLB_DEBUG_LOG_MESSAGE:
955 handled = hsw_log_message(hsw, header);
957 case IPC_GLB_MODULE_OPERATION:
958 handled = hsw_module_message(hsw, header);
961 dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
969 static irqreturn_t hsw_irq_thread(int irq, void *context)
971 struct sst_dsp *sst = (struct sst_dsp *) context;
972 struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
977 spin_lock_irqsave(&sst->spinlock, flags);
979 ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
980 ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
982 /* reply message from DSP */
983 if (ipcx & SST_IPCX_DONE) {
985 /* Handle Immediate reply from DSP Core */
986 handled = hsw_process_reply(hsw, ipcx);
989 /* clear DONE bit - tell DSP we have completed */
990 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
993 /* unmask Done interrupt */
994 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
999 /* new message from DSP */
1000 if (ipcd & SST_IPCD_BUSY) {
1002 /* Handle Notification and Delayed reply from DSP Core */
1003 handled = hsw_process_notification(hsw);
1005 /* clear BUSY bit and set DONE bit - accept new messages */
1007 sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
1008 SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
1010 /* unmask busy interrupt */
1011 sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
1016 spin_unlock_irqrestore(&sst->spinlock, flags);
1018 /* continue to send any remaining messages... */
1019 queue_kthread_work(&hsw->kworker, &hsw->kwork);
1024 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
1025 struct sst_hsw_ipc_fw_version *version)
1029 ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
1030 NULL, 0, version, sizeof(*version));
1032 dev_err(hsw->dev, "error: get version failed\n");
1037 /* Mixer Controls */
1038 int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1039 u32 stage_id, u32 channel, u32 *volume)
1044 sst_dsp_read(hsw->dsp, volume,
1045 stream->reply.volume_register_address[channel],
1052 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
1053 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
1055 struct sst_hsw_ipc_volume_req *req;
1059 trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
1061 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
1064 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1065 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1066 header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
1067 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1068 header |= (stage_id << IPC_STG_ID_SHIFT);
1070 req = &stream->vol_req;
1071 req->target_volume = volume;
1073 /* set both at same time ? */
1074 if (channel == SST_HSW_CHANNELS_ALL) {
1075 if (hsw->mute[0] && hsw->mute[1]) {
1076 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1078 } else if (hsw->mute[0])
1080 else if (hsw->mute[1])
1083 req->channel = SST_HSW_CHANNELS_ALL;
1085 /* set only 1 channel */
1086 if (hsw->mute[channel]) {
1087 hsw->mute_volume[channel] = volume;
1090 req->channel = channel;
1093 ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
1095 dev_err(hsw->dev, "error: set stream volume failed\n");
1102 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1108 sst_dsp_read(hsw->dsp, volume,
1109 hsw->mixer_info.volume_register_address[channel],
1115 /* global mixer volume */
1116 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
1119 struct sst_hsw_ipc_volume_req req;
1123 trace_ipc_request("set mixer volume", volume);
1125 if (channel >= 2 && channel != SST_HSW_CHANNELS_ALL)
1128 /* set both at same time ? */
1129 if (channel == SST_HSW_CHANNELS_ALL) {
1130 if (hsw->mute[0] && hsw->mute[1]) {
1131 hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
1133 } else if (hsw->mute[0])
1135 else if (hsw->mute[1])
1138 req.channel = SST_HSW_CHANNELS_ALL;
1140 /* set only 1 channel */
1141 if (hsw->mute[channel]) {
1142 hsw->mute_volume[channel] = volume;
1145 req.channel = channel;
1148 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
1149 IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
1150 header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
1151 header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
1152 header |= (stage_id << IPC_STG_ID_SHIFT);
1154 req.curve_duration = hsw->curve_duration;
1155 req.curve_type = hsw->curve_type;
1156 req.target_volume = volume;
1158 ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
1160 dev_err(hsw->dev, "error: set mixer volume failed\n");
1168 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
1169 u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
1172 struct sst_hsw_stream *stream;
1173 struct sst_dsp *sst = hsw->dsp;
1174 unsigned long flags;
1176 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
1180 spin_lock_irqsave(&sst->spinlock, flags);
1181 stream->reply.stream_hw_id = INVALID_STREAM_HW_ID;
1182 list_add(&stream->node, &hsw->stream_list);
1183 stream->notify_position = notify_position;
1184 stream->pdata = data;
1186 stream->host_id = id;
1188 /* work to process notification messages */
1189 INIT_WORK(&stream->notify_work, hsw_notification_work);
1190 spin_unlock_irqrestore(&sst->spinlock, flags);
1195 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1199 struct sst_dsp *sst = hsw->dsp;
1200 unsigned long flags;
1203 dev_warn(hsw->dev, "warning: stream is NULL, no stream to free, ignore it.\n");
1207 /* dont free DSP streams that are not commited */
1208 if (!stream->commited)
1211 trace_ipc_request("stream free", stream->host_id);
1213 stream->free_req.stream_id = stream->reply.stream_hw_id;
1214 header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
1216 ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
1217 sizeof(stream->free_req), NULL, 0);
1219 dev_err(hsw->dev, "error: free stream %d failed\n",
1220 stream->free_req.stream_id);
1224 trace_hsw_stream_free_req(stream, &stream->free_req);
1227 cancel_work_sync(&stream->notify_work);
1228 spin_lock_irqsave(&sst->spinlock, flags);
1229 list_del(&stream->node);
1231 spin_unlock_irqrestore(&sst->spinlock, flags);
1236 int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
1237 struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
1239 if (stream->commited) {
1240 dev_err(hsw->dev, "error: stream committed for set bits\n");
1244 stream->request.format.bitdepth = bits;
1248 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
1249 struct sst_hsw_stream *stream, int channels)
1251 if (stream->commited) {
1252 dev_err(hsw->dev, "error: stream committed for set channels\n");
1256 stream->request.format.ch_num = channels;
1260 int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
1261 struct sst_hsw_stream *stream, int rate)
1263 if (stream->commited) {
1264 dev_err(hsw->dev, "error: stream committed for set rate\n");
1268 stream->request.format.frequency = rate;
1272 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
1273 struct sst_hsw_stream *stream, u32 map,
1274 enum sst_hsw_channel_config config)
1276 if (stream->commited) {
1277 dev_err(hsw->dev, "error: stream committed for set map\n");
1281 stream->request.format.map = map;
1282 stream->request.format.config = config;
1286 int sst_hsw_stream_set_style(struct sst_hsw *hsw,
1287 struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
1289 if (stream->commited) {
1290 dev_err(hsw->dev, "error: stream committed for set style\n");
1294 stream->request.format.style = style;
1298 int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
1299 struct sst_hsw_stream *stream, u32 bits)
1301 if (stream->commited) {
1302 dev_err(hsw->dev, "error: stream committed for set valid bits\n");
1306 stream->request.format.valid_bit = bits;
1310 /* Stream Configuration */
1311 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1312 enum sst_hsw_stream_path_id path_id,
1313 enum sst_hsw_stream_type stream_type,
1314 enum sst_hsw_stream_format format_id)
1316 if (stream->commited) {
1317 dev_err(hsw->dev, "error: stream committed for set format\n");
1321 stream->request.path_id = path_id;
1322 stream->request.stream_type = stream_type;
1323 stream->request.format_id = format_id;
1325 trace_hsw_stream_alloc_request(stream, &stream->request);
1330 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1331 u32 ring_pt_address, u32 num_pages,
1332 u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
1334 if (stream->commited) {
1335 dev_err(hsw->dev, "error: stream committed for buffer\n");
1339 stream->request.ringinfo.ring_pt_address = ring_pt_address;
1340 stream->request.ringinfo.num_pages = num_pages;
1341 stream->request.ringinfo.ring_size = ring_size;
1342 stream->request.ringinfo.ring_offset = ring_offset;
1343 stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
1345 trace_hsw_stream_buffer(stream);
1350 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
1351 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime)
1353 struct sst_hsw_module_map *map = &stream->request.map;
1354 struct sst_dsp *dsp = sst_hsw_get_dsp(hsw);
1355 struct sst_module *module = runtime->module;
1357 if (stream->commited) {
1358 dev_err(hsw->dev, "error: stream committed for set module\n");
1362 /* only support initial module atm */
1363 map->module_entries_count = 1;
1364 map->module_entries[0].module_id = module->id;
1365 map->module_entries[0].entry_point = module->entry;
1367 stream->request.persistent_mem.offset =
1368 sst_dsp_get_offset(dsp, runtime->persistent_offset, SST_MEM_DRAM);
1369 stream->request.persistent_mem.size = module->persistent_size;
1371 stream->request.scratch_mem.offset =
1372 sst_dsp_get_offset(dsp, dsp->scratch_offset, SST_MEM_DRAM);
1373 stream->request.scratch_mem.size = dsp->scratch_size;
1375 dev_dbg(hsw->dev, "module %d runtime %d using:\n", module->id,
1377 dev_dbg(hsw->dev, " persistent offset 0x%x bytes 0x%x\n",
1378 stream->request.persistent_mem.offset,
1379 stream->request.persistent_mem.size);
1380 dev_dbg(hsw->dev, " scratch offset 0x%x bytes 0x%x\n",
1381 stream->request.scratch_mem.offset,
1382 stream->request.scratch_mem.size);
1387 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1389 struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
1390 struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
1395 dev_warn(hsw->dev, "warning: stream is NULL, no stream to commit, ignore it.\n");
1399 if (stream->commited) {
1400 dev_warn(hsw->dev, "warning: stream is already committed, ignore it.\n");
1404 trace_ipc_request("stream alloc", stream->host_id);
1406 header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
1408 ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
1409 reply, sizeof(*reply));
1411 dev_err(hsw->dev, "error: stream commit failed\n");
1415 stream->commited = 1;
1416 trace_hsw_stream_alloc_reply(stream);
1421 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
1422 struct sst_hsw_stream *stream)
1424 return stream->old_position;
1427 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
1428 struct sst_hsw_stream *stream, snd_pcm_uframes_t val)
1430 stream->old_position = val;
1433 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
1434 struct sst_hsw_stream *stream)
1436 return stream->play_silence;
1439 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
1440 struct sst_hsw_stream *stream, bool val)
1442 stream->play_silence = val;
1445 /* Stream Information - these calls could be inline but we want the IPC
1446 ABI to be opaque to client PCM drivers to cope with any future ABI changes */
1447 int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
1449 struct sst_hsw_ipc_stream_info_reply *reply;
1453 reply = &hsw->mixer_info;
1454 header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
1456 trace_ipc_request("get global mixer info", 0);
1458 ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
1460 dev_err(hsw->dev, "error: get stream info failed\n");
1464 trace_hsw_mixer_info_reply(reply);
1469 /* Send stream command */
1470 static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
1471 int stream_id, int wait)
1475 header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
1476 header |= (stream_id << IPC_STR_ID_SHIFT);
1479 return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
1481 return ipc_tx_message_nowait(hsw, header, NULL, 0);
1484 /* Stream ALSA trigger operations */
1485 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1491 dev_warn(hsw->dev, "warning: stream is NULL, no stream to pause, ignore it.\n");
1495 trace_ipc_request("stream pause", stream->reply.stream_hw_id);
1497 ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
1498 stream->reply.stream_hw_id, wait);
1500 dev_err(hsw->dev, "error: failed to pause stream %d\n",
1501 stream->reply.stream_hw_id);
1506 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
1512 dev_warn(hsw->dev, "warning: stream is NULL, no stream to resume, ignore it.\n");
1516 trace_ipc_request("stream resume", stream->reply.stream_hw_id);
1518 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
1519 stream->reply.stream_hw_id, wait);
1521 dev_err(hsw->dev, "error: failed to resume stream %d\n",
1522 stream->reply.stream_hw_id);
1527 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
1529 int ret, tries = 10;
1532 dev_warn(hsw->dev, "warning: stream is NULL, no stream to reset, ignore it.\n");
1536 /* dont reset streams that are not commited */
1537 if (!stream->commited)
1540 /* wait for pause to complete before we reset the stream */
1541 while (stream->running && tries--)
1544 dev_err(hsw->dev, "error: reset stream %d still running\n",
1545 stream->reply.stream_hw_id);
1549 trace_ipc_request("stream reset", stream->reply.stream_hw_id);
1551 ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
1552 stream->reply.stream_hw_id, 1);
1554 dev_err(hsw->dev, "error: failed to reset stream %d\n",
1555 stream->reply.stream_hw_id);
1559 /* Stream pointer positions */
1560 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
1561 struct sst_hsw_stream *stream)
1565 sst_dsp_read(hsw->dsp, &rpos,
1566 stream->reply.read_position_register_address, sizeof(rpos));
1571 /* Stream presentation (monotonic) positions */
1572 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
1573 struct sst_hsw_stream *stream)
1577 sst_dsp_read(hsw->dsp, &ppos,
1578 stream->reply.presentation_position_register_address,
1584 /* physical BE config */
1585 int sst_hsw_device_set_config(struct sst_hsw *hsw,
1586 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
1587 enum sst_hsw_device_mode mode, u32 clock_divider)
1589 struct sst_hsw_ipc_device_config_req config;
1593 trace_ipc_request("set device config", dev);
1595 config.ssp_interface = dev;
1596 config.clock_frequency = mclk;
1598 config.clock_divider = clock_divider;
1599 if (mode == SST_HSW_DEVICE_TDM_CLOCK_MASTER)
1600 config.channels = 4;
1602 config.channels = 2;
1604 trace_hsw_device_config_req(&config);
1606 header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
1608 ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
1611 dev_err(hsw->dev, "error: set device formats failed\n");
1615 EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
1618 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
1619 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
1624 header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
1627 trace_ipc_request("PM enter Dx state", state);
1629 ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
1632 dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
1636 for (item = 0; item < dx->entries_no; item++) {
1638 "Item[%d] offset[%x] - size[%x] - source[%x]\n",
1639 item, dx->mem_info[item].offset,
1640 dx->mem_info[item].size,
1641 dx->mem_info[item].source);
1643 dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
1644 dx->entries_no, state);
1649 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
1650 int mod_id, int offset)
1652 struct sst_dsp *dsp = hsw->dsp;
1653 struct sst_module *module;
1654 struct sst_module_runtime *runtime;
1657 module = sst_module_get_from_id(dsp, mod_id);
1658 if (module == NULL) {
1659 dev_err(dsp->dev, "error: failed to get module %d for pcm\n",
1664 runtime = sst_module_runtime_new(module, mod_id, NULL);
1665 if (runtime == NULL) {
1666 dev_err(dsp->dev, "error: failed to create module %d runtime\n",
1671 err = sst_module_runtime_alloc_blocks(runtime, offset);
1673 dev_err(dsp->dev, "error: failed to alloc blocks for module %d runtime\n",
1675 sst_module_runtime_free(runtime);
1679 dev_dbg(dsp->dev, "runtime id %d created for module %d\n", runtime->id,
1684 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime)
1686 sst_module_runtime_free_blocks(runtime);
1687 sst_module_runtime_free(runtime);
1691 static int sst_hsw_dx_state_dump(struct sst_hsw *hsw)
1693 struct sst_dsp *sst = hsw->dsp;
1694 u32 item, offset, size;
1697 trace_ipc_request("PM state dump. Items #", SST_HSW_MAX_DX_REGIONS);
1699 if (hsw->dx.entries_no > SST_HSW_MAX_DX_REGIONS) {
1701 "error: number of FW context regions greater than %d\n",
1702 SST_HSW_MAX_DX_REGIONS);
1703 memset(&hsw->dx, 0, sizeof(hsw->dx));
1707 ret = sst_dsp_dma_get_channel(sst, 0);
1709 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1713 /* set on-demond mode on engine 0 channel 3 */
1714 sst_dsp_shim_update_bits(sst, SST_HMDC,
1715 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH,
1716 SST_HMDC_HDDA_E0_ALLCH | SST_HMDC_HDDA_E1_ALLCH);
1718 for (item = 0; item < hsw->dx.entries_no; item++) {
1719 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1720 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1721 && hsw->dx.mem_info[item].offset <
1722 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1724 offset = hsw->dx.mem_info[item].offset
1725 - DSP_DRAM_ADDR_OFFSET;
1726 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1728 ret = sst_dsp_dma_copyfrom(sst, hsw->dx_context_paddr + offset,
1729 sst->addr.lpe_base + offset, size);
1732 "error: FW context dump failed\n");
1733 memset(&hsw->dx, 0, sizeof(hsw->dx));
1740 sst_dsp_dma_put_channel(sst);
1744 static int sst_hsw_dx_state_restore(struct sst_hsw *hsw)
1746 struct sst_dsp *sst = hsw->dsp;
1747 u32 item, offset, size;
1750 for (item = 0; item < hsw->dx.entries_no; item++) {
1751 if (hsw->dx.mem_info[item].source == SST_HSW_DX_TYPE_MEMORY_DUMP
1752 && hsw->dx.mem_info[item].offset > DSP_DRAM_ADDR_OFFSET
1753 && hsw->dx.mem_info[item].offset <
1754 DSP_DRAM_ADDR_OFFSET + SST_HSW_DX_CONTEXT_SIZE) {
1756 offset = hsw->dx.mem_info[item].offset
1757 - DSP_DRAM_ADDR_OFFSET;
1758 size = (hsw->dx.mem_info[item].size + 3) & (~3);
1760 ret = sst_dsp_dma_copyto(sst, sst->addr.lpe_base + offset,
1761 hsw->dx_context_paddr + offset, size);
1764 "error: FW context restore failed\n");
1773 static void sst_hsw_drop_all(struct sst_hsw *hsw)
1775 struct ipc_message *msg, *tmp;
1776 unsigned long flags;
1777 int tx_drop_cnt = 0, rx_drop_cnt = 0;
1779 /* drop all TX and Rx messages before we stall + reset DSP */
1780 spin_lock_irqsave(&hsw->dsp->spinlock, flags);
1782 list_for_each_entry_safe(msg, tmp, &hsw->tx_list, list) {
1783 list_move(&msg->list, &hsw->empty_list);
1787 list_for_each_entry_safe(msg, tmp, &hsw->rx_list, list) {
1788 list_move(&msg->list, &hsw->empty_list);
1792 spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
1794 if (tx_drop_cnt || rx_drop_cnt)
1795 dev_err(hsw->dev, "dropped IPC msg RX=%d, TX=%d\n",
1796 tx_drop_cnt, rx_drop_cnt);
1799 int sst_hsw_dsp_load(struct sst_hsw *hsw)
1801 struct sst_dsp *dsp = hsw->dsp;
1802 struct sst_fw *sst_fw, *t;
1805 dev_dbg(hsw->dev, "loading audio DSP....");
1807 ret = sst_dsp_wake(dsp);
1809 dev_err(hsw->dev, "error: failed to wake audio DSP\n");
1813 ret = sst_dsp_dma_get_channel(dsp, 0);
1815 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1819 list_for_each_entry_safe_reverse(sst_fw, t, &dsp->fw_list, list) {
1820 ret = sst_fw_reload(sst_fw);
1822 dev_err(hsw->dev, "error: SST FW reload failed\n");
1823 sst_dsp_dma_put_channel(dsp);
1827 ret = sst_block_alloc_scratch(hsw->dsp);
1831 sst_dsp_dma_put_channel(dsp);
1835 static int sst_hsw_dsp_restore(struct sst_hsw *hsw)
1837 struct sst_dsp *dsp = hsw->dsp;
1840 dev_dbg(hsw->dev, "restoring audio DSP....");
1842 ret = sst_dsp_dma_get_channel(dsp, 0);
1844 dev_err(hsw->dev, "error: cant allocate dma channel %d\n", ret);
1848 ret = sst_hsw_dx_state_restore(hsw);
1850 dev_err(hsw->dev, "error: SST FW context restore failed\n");
1851 sst_dsp_dma_put_channel(dsp);
1854 sst_dsp_dma_put_channel(dsp);
1856 /* wait for DSP boot completion */
1862 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw)
1866 dev_dbg(hsw->dev, "audio dsp runtime suspend\n");
1868 ret = sst_hsw_dx_set_state(hsw, SST_HSW_DX_STATE_D3, &hsw->dx);
1872 sst_dsp_stall(hsw->dsp);
1874 ret = sst_hsw_dx_state_dump(hsw);
1878 sst_hsw_drop_all(hsw);
1883 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw)
1885 struct sst_fw *sst_fw, *t;
1886 struct sst_dsp *dsp = hsw->dsp;
1888 list_for_each_entry_safe(sst_fw, t, &dsp->fw_list, list) {
1889 sst_fw_unload(sst_fw);
1891 sst_block_free_scratch(dsp);
1893 hsw->boot_complete = false;
1900 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw)
1902 struct device *dev = hsw->dev;
1905 dev_dbg(dev, "audio dsp runtime resume\n");
1907 if (hsw->boot_complete)
1908 return 1; /* tell caller no action is required */
1910 ret = sst_hsw_dsp_restore(hsw);
1912 dev_err(dev, "error: audio DSP boot failure\n");
1914 sst_hsw_init_module_state(hsw);
1916 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
1917 msecs_to_jiffies(IPC_BOOT_MSECS));
1919 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
1920 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
1921 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
1925 /* Set ADSP SSP port settings */
1926 ret = sst_hsw_device_set_config(hsw, SST_HSW_DEVICE_SSP_0,
1927 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ,
1928 SST_HSW_DEVICE_CLOCK_MASTER, 9);
1930 dev_err(dev, "error: SSP re-initialization failed\n");
1936 static int msg_empty_list_init(struct sst_hsw *hsw)
1940 hsw->msg = kzalloc(sizeof(struct ipc_message) *
1941 IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
1942 if (hsw->msg == NULL)
1945 for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
1946 init_waitqueue_head(&hsw->msg[i].waitq);
1947 list_add(&hsw->msg[i].list, &hsw->empty_list);
1953 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
1958 void sst_hsw_init_module_state(struct sst_hsw *hsw)
1960 struct sst_module *module;
1961 enum sst_hsw_module_id id;
1963 /* the base fw contains several modules */
1964 for (id = SST_HSW_MODULE_BASE_FW; id < SST_HSW_MAX_MODULE_ID; id++) {
1965 module = sst_module_get_from_id(hsw->dsp, id);
1967 /* module waves is active only after being enabled */
1968 if (id == SST_HSW_MODULE_WAVES)
1969 module->state = SST_MODULE_STATE_INITIALIZED;
1971 module->state = SST_MODULE_STATE_ACTIVE;
1976 bool sst_hsw_is_module_loaded(struct sst_hsw *hsw, u32 module_id)
1978 struct sst_module *module;
1980 module = sst_module_get_from_id(hsw->dsp, module_id);
1981 if (module == NULL || module->state == SST_MODULE_STATE_UNLOADED)
1987 bool sst_hsw_is_module_active(struct sst_hsw *hsw, u32 module_id)
1989 struct sst_module *module;
1991 module = sst_module_get_from_id(hsw->dsp, module_id);
1992 if (module != NULL && module->state == SST_MODULE_STATE_ACTIVE)
1998 void sst_hsw_set_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
2000 hsw->enabled_modules_rtd3 |= (1 << module_id);
2003 void sst_hsw_set_module_disabled_rtd3(struct sst_hsw *hsw, u32 module_id)
2005 hsw->enabled_modules_rtd3 &= ~(1 << module_id);
2008 bool sst_hsw_is_module_enabled_rtd3(struct sst_hsw *hsw, u32 module_id)
2010 return hsw->enabled_modules_rtd3 & (1 << module_id);
2013 void sst_hsw_reset_param_buf(struct sst_hsw *hsw)
2015 hsw->param_idx_w = 0;
2016 hsw->param_idx_r = 0;
2017 memset((void *)hsw->param_buf, 0, sizeof(hsw->param_buf));
2020 int sst_hsw_store_param_line(struct sst_hsw *hsw, u8 *buf)
2022 /* save line to the first available position of param buffer */
2023 if (hsw->param_idx_w > WAVES_PARAM_LINES - 1) {
2024 dev_warn(hsw->dev, "warning: param buffer overflow!\n");
2027 memcpy(hsw->param_buf[hsw->param_idx_w], buf, WAVES_PARAM_COUNT);
2032 int sst_hsw_load_param_line(struct sst_hsw *hsw, u8 *buf)
2036 /* read the first matching line from param buffer */
2037 while (hsw->param_idx_r < WAVES_PARAM_LINES) {
2038 id = hsw->param_buf[hsw->param_idx_r][0];
2041 memcpy(buf, hsw->param_buf[hsw->param_idx_r],
2046 if (hsw->param_idx_r > WAVES_PARAM_LINES - 1) {
2047 dev_dbg(hsw->dev, "end of buffer, roll to the beginning\n");
2048 hsw->param_idx_r = 0;
2054 int sst_hsw_launch_param_buf(struct sst_hsw *hsw)
2058 if (!sst_hsw_is_module_active(hsw, SST_HSW_MODULE_WAVES)) {
2059 dev_dbg(hsw->dev, "module waves is not active\n");
2063 /* put all param lines to DSP through ipc */
2064 for (idx = 0; idx < hsw->param_idx_w; idx++) {
2065 ret = sst_hsw_module_set_param(hsw,
2066 SST_HSW_MODULE_WAVES, 0, hsw->param_buf[idx][0],
2067 WAVES_PARAM_COUNT, hsw->param_buf[idx]);
2074 int sst_hsw_module_load(struct sst_hsw *hsw,
2075 u32 module_id, u32 instance_id, char *name)
2078 const struct firmware *fw = NULL;
2079 struct sst_fw *hsw_sst_fw;
2080 struct sst_module *module;
2081 struct device *dev = hsw->dev;
2082 struct sst_dsp *dsp = hsw->dsp;
2084 dev_dbg(dev, "sst_hsw_module_load id=%d, name='%s'", module_id, name);
2086 module = sst_module_get_from_id(dsp, module_id);
2087 if (module == NULL) {
2088 /* loading for the first time */
2089 if (module_id == SST_HSW_MODULE_BASE_FW) {
2090 /* for base module: use fw requested in acpi probe */
2091 fw = dsp->pdata->fw;
2093 dev_err(dev, "request Base fw failed\n");
2097 /* try and load any other optional modules if they are
2098 * available. Use dev_info instead of dev_err in case
2099 * request firmware failed */
2100 ret = request_firmware(&fw, name, dev);
2102 dev_info(dev, "fw image %s not available(%d)\n",
2107 hsw_sst_fw = sst_fw_new(dsp, fw, hsw);
2108 if (hsw_sst_fw == NULL) {
2109 dev_err(dev, "error: failed to load firmware\n");
2113 module = sst_module_get_from_id(dsp, module_id);
2114 if (module == NULL) {
2115 dev_err(dev, "error: no module %d in firmware %s\n",
2119 dev_info(dev, "module %d (%s) already loaded\n",
2122 /* release fw, but base fw should be released by acpi driver */
2123 if (fw && module_id != SST_HSW_MODULE_BASE_FW)
2124 release_firmware(fw);
2129 int sst_hsw_module_enable(struct sst_hsw *hsw,
2130 u32 module_id, u32 instance_id)
2134 struct sst_hsw_ipc_module_config config;
2135 struct sst_module *module;
2136 struct sst_module_runtime *runtime;
2137 struct device *dev = hsw->dev;
2138 struct sst_dsp *dsp = hsw->dsp;
2140 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
2141 dev_dbg(dev, "module %d not loaded\n", module_id);
2145 if (sst_hsw_is_module_active(hsw, module_id)) {
2146 dev_info(dev, "module %d already enabled\n", module_id);
2150 module = sst_module_get_from_id(dsp, module_id);
2151 if (module == NULL) {
2152 dev_err(dev, "module %d not valid\n", module_id);
2156 runtime = sst_module_runtime_get_from_id(module, module_id);
2157 if (runtime == NULL) {
2158 dev_err(dev, "runtime %d not valid", module_id);
2162 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2163 IPC_MODULE_OPERATION(IPC_MODULE_ENABLE) |
2164 IPC_MODULE_ID(module_id);
2165 dev_dbg(dev, "module enable header: %x\n", header);
2167 config.map.module_entries_count = 1;
2168 config.map.module_entries[0].module_id = module->id;
2169 config.map.module_entries[0].entry_point = module->entry;
2171 config.persistent_mem.offset =
2172 sst_dsp_get_offset(dsp,
2173 runtime->persistent_offset, SST_MEM_DRAM);
2174 config.persistent_mem.size = module->persistent_size;
2176 config.scratch_mem.offset =
2177 sst_dsp_get_offset(dsp,
2178 dsp->scratch_offset, SST_MEM_DRAM);
2179 config.scratch_mem.size = module->scratch_size;
2180 dev_dbg(dev, "mod %d enable p:%d @ %x, s:%d @ %x, ep: %x",
2181 config.map.module_entries[0].module_id,
2182 config.persistent_mem.size,
2183 config.persistent_mem.offset,
2184 config.scratch_mem.size, config.scratch_mem.offset,
2185 config.map.module_entries[0].entry_point);
2187 ret = ipc_tx_message_wait(hsw, header,
2188 &config, sizeof(config), NULL, 0);
2190 dev_err(dev, "ipc: module enable failed - %d\n", ret);
2192 module->state = SST_MODULE_STATE_ACTIVE;
2197 int sst_hsw_module_disable(struct sst_hsw *hsw,
2198 u32 module_id, u32 instance_id)
2202 struct sst_module *module;
2203 struct device *dev = hsw->dev;
2204 struct sst_dsp *dsp = hsw->dsp;
2206 if (!sst_hsw_is_module_loaded(hsw, module_id)) {
2207 dev_dbg(dev, "module %d not loaded\n", module_id);
2211 if (!sst_hsw_is_module_active(hsw, module_id)) {
2212 dev_info(dev, "module %d already disabled\n", module_id);
2216 module = sst_module_get_from_id(dsp, module_id);
2217 if (module == NULL) {
2218 dev_err(dev, "module %d not valid\n", module_id);
2222 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2223 IPC_MODULE_OPERATION(IPC_MODULE_DISABLE) |
2224 IPC_MODULE_ID(module_id);
2226 ret = ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
2228 dev_err(dev, "module disable failed - %d\n", ret);
2230 module->state = SST_MODULE_STATE_INITIALIZED;
2235 int sst_hsw_module_set_param(struct sst_hsw *hsw,
2236 u32 module_id, u32 instance_id, u32 parameter_id,
2237 u32 param_size, char *param)
2240 unsigned char *data = NULL;
2242 u32 payload_size = 0, transfer_parameter_size = 0;
2243 dma_addr_t dma_addr = 0;
2244 struct sst_hsw_transfer_parameter *parameter;
2245 struct device *dev = hsw->dev;
2247 header = IPC_GLB_TYPE(IPC_GLB_MODULE_OPERATION) |
2248 IPC_MODULE_OPERATION(IPC_MODULE_SET_PARAMETER) |
2249 IPC_MODULE_ID(module_id);
2250 dev_dbg(dev, "sst_hsw_module_set_param header=%x\n", header);
2252 payload_size = param_size +
2253 sizeof(struct sst_hsw_transfer_parameter) -
2254 sizeof(struct sst_hsw_transfer_list);
2255 dev_dbg(dev, "parameter size : %d\n", param_size);
2256 dev_dbg(dev, "payload size : %d\n", payload_size);
2258 if (payload_size <= SST_HSW_IPC_MAX_SHORT_PARAMETER_SIZE) {
2259 /* short parameter, mailbox can contain data */
2260 dev_dbg(dev, "transfer parameter size : %d\n",
2261 transfer_parameter_size);
2263 transfer_parameter_size = ALIGN(payload_size, 4);
2264 dev_dbg(dev, "transfer parameter aligned size : %d\n",
2265 transfer_parameter_size);
2267 parameter = kzalloc(transfer_parameter_size, GFP_KERNEL);
2268 if (parameter == NULL)
2271 memcpy(parameter->data, param, param_size);
2273 dev_warn(dev, "transfer parameter size too large!");
2277 parameter->parameter_id = parameter_id;
2278 parameter->data_size = param_size;
2280 ret = ipc_tx_message_wait(hsw, header,
2281 parameter, transfer_parameter_size , NULL, 0);
2283 dev_err(dev, "ipc: module set parameter failed - %d\n", ret);
2288 dma_free_coherent(hsw->dsp->dma_dev,
2289 param_size, (void *)data, dma_addr);
2294 static struct sst_dsp_device hsw_dev = {
2295 .thread = hsw_irq_thread,
2296 .ops = &haswell_ops,
2299 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
2301 struct sst_hsw_ipc_fw_version version;
2302 struct sst_hsw *hsw;
2305 dev_dbg(dev, "initialising Audio DSP IPC\n");
2307 hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
2312 INIT_LIST_HEAD(&hsw->stream_list);
2313 INIT_LIST_HEAD(&hsw->tx_list);
2314 INIT_LIST_HEAD(&hsw->rx_list);
2315 INIT_LIST_HEAD(&hsw->empty_list);
2316 init_waitqueue_head(&hsw->boot_wait);
2317 init_waitqueue_head(&hsw->wait_txq);
2319 ret = msg_empty_list_init(hsw);
2323 /* start the IPC message thread */
2324 init_kthread_worker(&hsw->kworker);
2325 hsw->tx_thread = kthread_run(kthread_worker_fn,
2326 &hsw->kworker, "%s",
2327 dev_name(hsw->dev));
2328 if (IS_ERR(hsw->tx_thread)) {
2329 ret = PTR_ERR(hsw->tx_thread);
2330 dev_err(hsw->dev, "error: failed to create message TX task\n");
2333 init_kthread_work(&hsw->kwork, ipc_tx_msgs);
2335 hsw_dev.thread_context = hsw;
2338 hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
2339 if (hsw->dsp == NULL) {
2344 /* allocate DMA buffer for context storage */
2345 hsw->dx_context = dma_alloc_coherent(hsw->dsp->dma_dev,
2346 SST_HSW_DX_CONTEXT_SIZE, &hsw->dx_context_paddr, GFP_KERNEL);
2347 if (hsw->dx_context == NULL) {
2352 /* keep the DSP in reset state for base FW loading */
2353 sst_dsp_reset(hsw->dsp);
2355 /* load base module and other modules in base firmware image */
2356 ret = sst_hsw_module_load(hsw, SST_HSW_MODULE_BASE_FW, 0, "Base");
2360 /* try to load module waves */
2361 sst_hsw_module_load(hsw, SST_HSW_MODULE_WAVES, 0, "intel/IntcPP01.bin");
2363 /* allocate scratch mem regions */
2364 ret = sst_block_alloc_scratch(hsw->dsp);
2368 /* init param buffer */
2369 sst_hsw_reset_param_buf(hsw);
2371 /* wait for DSP boot completion */
2372 sst_dsp_boot(hsw->dsp);
2373 ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
2374 msecs_to_jiffies(IPC_BOOT_MSECS));
2377 dev_err(hsw->dev, "error: audio DSP boot timeout IPCD 0x%x IPCX 0x%x\n",
2378 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCD),
2379 sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX));
2383 /* init module state after boot */
2384 sst_hsw_init_module_state(hsw);
2386 /* get the FW version */
2387 sst_hsw_fw_get_version(hsw, &version);
2389 /* get the globalmixer */
2390 ret = sst_hsw_mixer_get_info(hsw);
2392 dev_err(hsw->dev, "error: failed to get stream info\n");
2400 sst_dsp_reset(hsw->dsp);
2401 sst_fw_free_all(hsw->dsp);
2403 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2404 hsw->dx_context, hsw->dx_context_paddr);
2406 sst_dsp_free(hsw->dsp);
2408 kthread_stop(hsw->tx_thread);
2414 EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
2416 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
2418 struct sst_hsw *hsw = pdata->dsp;
2420 sst_dsp_reset(hsw->dsp);
2421 sst_fw_free_all(hsw->dsp);
2422 dma_free_coherent(hsw->dsp->dma_dev, SST_HSW_DX_CONTEXT_SIZE,
2423 hsw->dx_context, hsw->dx_context_paddr);
2424 sst_dsp_free(hsw->dsp);
2425 kthread_stop(hsw->tx_thread);
2428 EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);