2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 #include <linux/init.h>
18 #include <linux/of_device.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34 #include <sound/dmaengine_pcm.h>
36 #include "jz4740-i2s.h"
38 #define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
39 #define JZ4740_DMA_TYPE_AIC_RECEIVE 25
41 #define JZ_REG_AIC_CONF 0x00
42 #define JZ_REG_AIC_CTRL 0x04
43 #define JZ_REG_AIC_I2S_FMT 0x10
44 #define JZ_REG_AIC_FIFO_STATUS 0x14
45 #define JZ_REG_AIC_I2S_STATUS 0x1c
46 #define JZ_REG_AIC_CLK_DIV 0x30
47 #define JZ_REG_AIC_FIFO 0x34
49 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
50 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
51 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
52 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
53 #define JZ_AIC_CONF_I2S BIT(4)
54 #define JZ_AIC_CONF_RESET BIT(3)
55 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
56 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
57 #define JZ_AIC_CONF_ENABLE BIT(0)
59 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
60 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
62 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
63 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
64 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
65 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
66 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
67 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
68 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
69 #define JZ_AIC_CTRL_FLUSH BIT(8)
70 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
71 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
72 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
73 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
74 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
75 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
76 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
78 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
79 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
81 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
82 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
83 #define JZ_AIC_I2S_FMT_MSB BIT(0)
85 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
87 #define JZ_AIC_CLK_DIV_MASK 0xf
88 #define I2SDIV_DV_SHIFT 8
89 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
99 struct snd_dmaengine_dai_dma_data playback_dma_data;
100 struct snd_dmaengine_dai_dma_data capture_dma_data;
103 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
106 return readl(i2s->base + reg);
109 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
110 unsigned int reg, uint32_t value)
112 writel(value, i2s->base + reg);
115 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
116 struct snd_soc_dai *dai)
118 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
124 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
125 ctrl |= JZ_AIC_CTRL_FLUSH;
126 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
128 clk_prepare_enable(i2s->clk_i2s);
130 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
131 conf |= JZ_AIC_CONF_ENABLE;
132 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
137 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
138 struct snd_soc_dai *dai)
140 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
146 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
147 conf &= ~JZ_AIC_CONF_ENABLE;
148 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
150 clk_disable_unprepare(i2s->clk_i2s);
153 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
154 struct snd_soc_dai *dai)
156 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
161 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
162 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
164 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
166 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
169 case SNDRV_PCM_TRIGGER_START:
170 case SNDRV_PCM_TRIGGER_RESUME:
171 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
174 case SNDRV_PCM_TRIGGER_STOP:
175 case SNDRV_PCM_TRIGGER_SUSPEND:
176 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
183 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
188 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
190 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
195 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
197 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
199 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
200 case SND_SOC_DAIFMT_CBS_CFS:
201 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
202 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
204 case SND_SOC_DAIFMT_CBM_CFS:
205 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
207 case SND_SOC_DAIFMT_CBS_CFM:
208 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
210 case SND_SOC_DAIFMT_CBM_CFM:
216 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
217 case SND_SOC_DAIFMT_MSB:
218 format |= JZ_AIC_I2S_FMT_MSB;
220 case SND_SOC_DAIFMT_I2S:
226 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
227 case SND_SOC_DAIFMT_NB_NF:
233 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
234 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
239 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
240 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
242 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
243 unsigned int sample_size;
244 uint32_t ctrl, div_reg;
247 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
249 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
250 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
252 switch (params_format(params)) {
253 case SNDRV_PCM_FORMAT_S8:
256 case SNDRV_PCM_FORMAT_S16:
263 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
264 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
265 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
266 if (params_channels(params) == 1)
267 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
269 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
271 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
272 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
275 div_reg &= ~I2SDIV_DV_MASK;
276 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
277 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
278 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
283 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
284 unsigned int freq, int dir)
286 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
291 case JZ4740_I2S_CLKSRC_EXT:
292 parent = clk_get(NULL, "ext");
293 clk_set_parent(i2s->clk_i2s, parent);
295 case JZ4740_I2S_CLKSRC_PLL:
296 parent = clk_get(NULL, "pll half");
297 clk_set_parent(i2s->clk_i2s, parent);
298 ret = clk_set_rate(i2s->clk_i2s, freq);
308 static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
310 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
314 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
315 conf &= ~JZ_AIC_CONF_ENABLE;
316 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
318 clk_disable_unprepare(i2s->clk_i2s);
321 clk_disable_unprepare(i2s->clk_aic);
326 static int jz4740_i2s_resume(struct snd_soc_dai *dai)
328 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
331 clk_prepare_enable(i2s->clk_aic);
334 clk_prepare_enable(i2s->clk_i2s);
336 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
337 conf |= JZ_AIC_CONF_ENABLE;
338 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
344 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
346 struct snd_dmaengine_dai_dma_data *dma_data;
349 dma_data = &i2s->playback_dma_data;
350 dma_data->maxburst = 16;
351 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
352 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
355 dma_data = &i2s->capture_dma_data;
356 dma_data->maxburst = 16;
357 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
358 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
361 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
363 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
366 clk_prepare_enable(i2s->clk_aic);
368 jz4740_i2c_init_pcm_config(i2s);
369 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
370 &i2s->capture_dma_data);
372 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
373 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
374 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
376 JZ_AIC_CONF_INTERNAL_CODEC;
378 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
379 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
384 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
386 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
388 clk_disable_unprepare(i2s->clk_aic);
392 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
393 .startup = jz4740_i2s_startup,
394 .shutdown = jz4740_i2s_shutdown,
395 .trigger = jz4740_i2s_trigger,
396 .hw_params = jz4740_i2s_hw_params,
397 .set_fmt = jz4740_i2s_set_fmt,
398 .set_sysclk = jz4740_i2s_set_sysclk,
401 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
402 SNDRV_PCM_FMTBIT_S16_LE)
404 static struct snd_soc_dai_driver jz4740_i2s_dai = {
405 .probe = jz4740_i2s_dai_probe,
406 .remove = jz4740_i2s_dai_remove,
410 .rates = SNDRV_PCM_RATE_8000_48000,
411 .formats = JZ4740_I2S_FMTS,
416 .rates = SNDRV_PCM_RATE_8000_48000,
417 .formats = JZ4740_I2S_FMTS,
419 .symmetric_rates = 1,
420 .ops = &jz4740_i2s_dai_ops,
421 .suspend = jz4740_i2s_suspend,
422 .resume = jz4740_i2s_resume,
425 static const struct snd_soc_component_driver jz4740_i2s_component = {
426 .name = "jz4740-i2s",
430 static const struct of_device_id jz4740_of_matches[] = {
431 { .compatible = "ingenic,jz4740-i2s" },
436 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
438 struct jz4740_i2s *i2s;
439 struct resource *mem;
442 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
446 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
447 i2s->base = devm_ioremap_resource(&pdev->dev, mem);
448 if (IS_ERR(i2s->base))
449 return PTR_ERR(i2s->base);
451 i2s->phys_base = mem->start;
453 i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
454 if (IS_ERR(i2s->clk_aic))
455 return PTR_ERR(i2s->clk_aic);
457 i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
458 if (IS_ERR(i2s->clk_i2s))
459 return PTR_ERR(i2s->clk_i2s);
461 platform_set_drvdata(pdev, i2s);
463 ret = devm_snd_soc_register_component(&pdev->dev,
464 &jz4740_i2s_component, &jz4740_i2s_dai, 1);
468 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
469 SND_DMAENGINE_PCM_FLAG_COMPAT);
472 static struct platform_driver jz4740_i2s_driver = {
473 .probe = jz4740_i2s_dev_probe,
475 .name = "jz4740-i2s",
476 .of_match_table = of_match_ptr(jz4740_of_matches)
480 module_platform_driver(jz4740_i2s_driver);
482 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
483 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
484 MODULE_LICENSE("GPL");
485 MODULE_ALIAS("platform:jz4740-i2s");