2 * Mediatek ALSA SoC AFE platform driver
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author: Koro Chen <koro.chen@mediatek.com>
6 * Sascha Hauer <s.hauer@pengutronix.de>
7 * Hidalgo Huang <hidalgo.huang@mediatek.com>
8 * Ir Lian <ir.lian@mediatek.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 and
12 * only version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #include <linux/delay.h>
21 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/pm_runtime.h>
26 #include <sound/soc.h>
27 #include "mtk-afe-common.h"
29 /*****************************************************************************
30 * R E G I S T E R D E F I N I T I O N
31 *****************************************************************************/
32 #define AUDIO_TOP_CON0 0x0000
33 #define AUDIO_TOP_CON1 0x0004
34 #define AFE_DAC_CON0 0x0010
35 #define AFE_DAC_CON1 0x0014
36 #define AFE_I2S_CON1 0x0034
37 #define AFE_I2S_CON2 0x0038
38 #define AFE_CONN_24BIT 0x006c
39 #define AFE_MEMIF_MSB 0x00cc
41 #define AFE_CONN1 0x0024
42 #define AFE_CONN2 0x0028
43 #define AFE_CONN7 0x0460
44 #define AFE_CONN8 0x0464
45 #define AFE_HDMI_CONN0 0x0390
47 /* Memory interface */
48 #define AFE_DL1_BASE 0x0040
49 #define AFE_DL1_CUR 0x0044
50 #define AFE_DL1_END 0x0048
51 #define AFE_DL2_BASE 0x0050
52 #define AFE_DL2_CUR 0x0054
53 #define AFE_AWB_BASE 0x0070
54 #define AFE_AWB_CUR 0x007c
55 #define AFE_VUL_BASE 0x0080
56 #define AFE_VUL_CUR 0x008c
57 #define AFE_VUL_END 0x0088
58 #define AFE_DAI_BASE 0x0090
59 #define AFE_DAI_CUR 0x009c
60 #define AFE_MOD_PCM_BASE 0x0330
61 #define AFE_MOD_PCM_CUR 0x033c
62 #define AFE_HDMI_OUT_BASE 0x0374
63 #define AFE_HDMI_OUT_CUR 0x0378
64 #define AFE_HDMI_OUT_END 0x037c
66 #define AFE_ADDA2_TOP_CON0 0x0600
68 #define AFE_HDMI_OUT_CON0 0x0370
70 #define AFE_IRQ_MCU_CON 0x03a0
71 #define AFE_IRQ_STATUS 0x03a4
72 #define AFE_IRQ_CLR 0x03a8
73 #define AFE_IRQ_CNT1 0x03ac
74 #define AFE_IRQ_CNT2 0x03b0
75 #define AFE_IRQ_MCU_EN 0x03b4
76 #define AFE_IRQ_CNT5 0x03bc
77 #define AFE_IRQ_CNT7 0x03dc
79 #define AFE_TDM_CON1 0x0548
80 #define AFE_TDM_CON2 0x054c
82 #define AFE_BASE_END_OFFSET 8
83 #define AFE_IRQ_STATUS_BITS 0xff
85 /* AUDIO_TOP_CON0 (0x0000) */
86 #define AUD_TCON0_PDN_SPDF (0x1 << 21)
87 #define AUD_TCON0_PDN_HDMI (0x1 << 20)
88 #define AUD_TCON0_PDN_24M (0x1 << 9)
89 #define AUD_TCON0_PDN_22M (0x1 << 8)
90 #define AUD_TCON0_PDN_AFE (0x1 << 2)
92 /* AFE_I2S_CON1 (0x0034) */
93 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12)
94 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8)
95 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3)
96 #define AFE_I2S_CON1_EN (0x1 << 0)
98 /* AFE_I2S_CON2 (0x0038) */
99 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12)
100 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8)
101 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3)
102 #define AFE_I2S_CON2_EN (0x1 << 0)
104 /* AFE_CONN_24BIT (0x006c) */
105 #define AFE_CONN_24BIT_O04 (0x1 << 4)
106 #define AFE_CONN_24BIT_O03 (0x1 << 3)
108 /* AFE_HDMI_CONN0 (0x0390) */
109 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21)
110 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18)
111 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15)
112 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12)
113 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9)
114 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6)
115 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3)
116 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0)
118 /* AFE_TDM_CON1 (0x0548) */
119 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24)
120 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12)
121 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8)
122 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4)
123 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3)
124 #define AFE_TDM_CON1_BCK_INV (0x1 << 1)
125 #define AFE_TDM_CON1_EN (0x1 << 0)
127 enum afe_tdm_ch_start {
128 AFE_TDM_CH_START_O30_O31 = 0,
129 AFE_TDM_CH_START_O32_O33,
130 AFE_TDM_CH_START_O34_O35,
131 AFE_TDM_CH_START_O36_O37,
135 static const unsigned int mtk_afe_backup_list[] = {
153 /* address for ioremap audio hardware register */
154 void __iomem *base_addr;
156 struct regmap *regmap;
157 struct mtk_afe_memif memif[MTK_AFE_MEMIF_NUM];
158 struct clk *clocks[MTK_CLK_NUM];
159 unsigned int backup_regs[ARRAY_SIZE(mtk_afe_backup_list)];
163 static const struct snd_pcm_hardware mtk_afe_hardware = {
164 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
165 SNDRV_PCM_INFO_MMAP_VALID),
166 .buffer_bytes_max = 256 * 1024,
167 .period_bytes_min = 512,
168 .period_bytes_max = 128 * 1024,
174 static snd_pcm_uframes_t mtk_afe_pcm_pointer
175 (struct snd_pcm_substream *substream)
177 struct snd_soc_pcm_runtime *rtd = substream->private_data;
178 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
179 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
183 ret = regmap_read(afe->regmap, memif->data->reg_ofs_cur, &hw_ptr);
184 if (ret || hw_ptr == 0) {
185 dev_err(afe->dev, "%s hw_ptr err\n", __func__);
186 hw_ptr = memif->phys_buf_addr;
189 return bytes_to_frames(substream->runtime,
190 hw_ptr - memif->phys_buf_addr);
193 static const struct snd_pcm_ops mtk_afe_pcm_ops = {
194 .ioctl = snd_pcm_lib_ioctl,
195 .pointer = mtk_afe_pcm_pointer,
198 static int mtk_afe_pcm_new(struct snd_soc_pcm_runtime *rtd)
201 struct snd_card *card = rtd->card->snd_card;
202 struct snd_pcm *pcm = rtd->pcm;
204 size = mtk_afe_hardware.buffer_bytes_max;
206 return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
207 card->dev, size, size);
210 static void mtk_afe_pcm_free(struct snd_pcm *pcm)
212 snd_pcm_lib_preallocate_free_for_all(pcm);
215 static const struct snd_soc_platform_driver mtk_afe_pcm_platform = {
216 .ops = &mtk_afe_pcm_ops,
217 .pcm_new = mtk_afe_pcm_new,
218 .pcm_free = mtk_afe_pcm_free,
221 struct mtk_afe_rate {
223 unsigned int regvalue;
226 static const struct mtk_afe_rate mtk_afe_i2s_rates[] = {
227 { .rate = 8000, .regvalue = 0 },
228 { .rate = 11025, .regvalue = 1 },
229 { .rate = 12000, .regvalue = 2 },
230 { .rate = 16000, .regvalue = 4 },
231 { .rate = 22050, .regvalue = 5 },
232 { .rate = 24000, .regvalue = 6 },
233 { .rate = 32000, .regvalue = 8 },
234 { .rate = 44100, .regvalue = 9 },
235 { .rate = 48000, .regvalue = 10 },
236 { .rate = 88000, .regvalue = 11 },
237 { .rate = 96000, .regvalue = 12 },
238 { .rate = 174000, .regvalue = 13 },
239 { .rate = 192000, .regvalue = 14 },
242 static int mtk_afe_i2s_fs(unsigned int sample_rate)
246 for (i = 0; i < ARRAY_SIZE(mtk_afe_i2s_rates); i++)
247 if (mtk_afe_i2s_rates[i].rate == sample_rate)
248 return mtk_afe_i2s_rates[i].regvalue;
253 static int mtk_afe_set_i2s(struct mtk_afe *afe, unsigned int rate)
256 int fs = mtk_afe_i2s_fs(rate);
261 /* from external ADC */
262 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1);
265 val = AFE_I2S_CON2_LOW_JITTER_CLK |
266 AFE_I2S_CON2_RATE(fs) |
267 AFE_I2S_CON2_FORMAT_I2S;
269 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val);
272 val = AFE_I2S_CON1_LOW_JITTER_CLK |
273 AFE_I2S_CON1_RATE(fs) |
274 AFE_I2S_CON1_FORMAT_I2S;
276 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val);
280 static void mtk_afe_set_i2s_enable(struct mtk_afe *afe, bool enable)
284 regmap_read(afe->regmap, AFE_I2S_CON2, &val);
285 if (!!(val & AFE_I2S_CON2_EN) == enable)
286 return; /* must skip soft reset */
288 /* I2S soft reset begin */
289 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0x4);
292 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable);
295 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable);
297 /* I2S soft reset end */
299 regmap_update_bits(afe->regmap, AUDIO_TOP_CON1, 0x4, 0);
302 static int mtk_afe_dais_enable_clks(struct mtk_afe *afe,
303 struct clk *m_ck, struct clk *b_ck)
308 ret = clk_prepare_enable(m_ck);
310 dev_err(afe->dev, "Failed to enable m_ck\n");
316 ret = clk_prepare_enable(b_ck);
318 dev_err(afe->dev, "Failed to enable b_ck\n");
325 static int mtk_afe_dais_set_clks(struct mtk_afe *afe,
326 struct clk *m_ck, unsigned int mck_rate,
327 struct clk *b_ck, unsigned int bck_rate)
332 ret = clk_set_rate(m_ck, mck_rate);
334 dev_err(afe->dev, "Failed to set m_ck rate\n");
340 ret = clk_set_rate(b_ck, bck_rate);
342 dev_err(afe->dev, "Failed to set b_ck rate\n");
349 static void mtk_afe_dais_disable_clks(struct mtk_afe *afe,
350 struct clk *m_ck, struct clk *b_ck)
353 clk_disable_unprepare(m_ck);
355 clk_disable_unprepare(b_ck);
358 static int mtk_afe_i2s_startup(struct snd_pcm_substream *substream,
359 struct snd_soc_dai *dai)
361 struct snd_soc_pcm_runtime *rtd = substream->private_data;
362 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
367 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
368 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
369 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0);
373 static void mtk_afe_i2s_shutdown(struct snd_pcm_substream *substream,
374 struct snd_soc_dai *dai)
376 struct snd_soc_pcm_runtime *rtd = substream->private_data;
377 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
382 mtk_afe_set_i2s_enable(afe, false);
383 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
384 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M,
385 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M);
386 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S1_M], NULL);
389 static int mtk_afe_i2s_prepare(struct snd_pcm_substream *substream,
390 struct snd_soc_dai *dai)
392 struct snd_soc_pcm_runtime *rtd = substream->private_data;
393 struct snd_pcm_runtime * const runtime = substream->runtime;
394 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
397 mtk_afe_dais_set_clks(afe,
398 afe->clocks[MTK_CLK_I2S1_M], runtime->rate * 256,
401 ret = mtk_afe_set_i2s(afe, substream->runtime->rate);
405 mtk_afe_set_i2s_enable(afe, true);
410 static int mtk_afe_hdmi_startup(struct snd_pcm_substream *substream,
411 struct snd_soc_dai *dai)
413 struct snd_soc_pcm_runtime *rtd = substream->private_data;
414 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
419 mtk_afe_dais_enable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
420 afe->clocks[MTK_CLK_I2S3_B]);
424 static void mtk_afe_hdmi_shutdown(struct snd_pcm_substream *substream,
425 struct snd_soc_dai *dai)
427 struct snd_soc_pcm_runtime *rtd = substream->private_data;
428 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
433 mtk_afe_dais_disable_clks(afe, afe->clocks[MTK_CLK_I2S3_M],
434 afe->clocks[MTK_CLK_I2S3_B]);
437 static int mtk_afe_hdmi_prepare(struct snd_pcm_substream *substream,
438 struct snd_soc_dai *dai)
440 struct snd_soc_pcm_runtime *rtd = substream->private_data;
441 struct snd_pcm_runtime * const runtime = substream->runtime;
442 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
445 mtk_afe_dais_set_clks(afe,
446 afe->clocks[MTK_CLK_I2S3_M], runtime->rate * 128,
447 afe->clocks[MTK_CLK_I2S3_B],
448 runtime->rate * runtime->channels * 32);
450 val = AFE_TDM_CON1_BCK_INV |
451 AFE_TDM_CON1_1_BCK_DELAY |
452 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */
453 AFE_TDM_CON1_WLEN_32BIT |
454 AFE_TDM_CON1_32_BCK_CYCLES |
455 AFE_TDM_CON1_LRCK_WIDTH(32);
456 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val);
458 /* set tdm2 config */
459 switch (runtime->channels) {
462 val = AFE_TDM_CH_START_O30_O31;
463 val |= (AFE_TDM_CH_ZERO << 4);
464 val |= (AFE_TDM_CH_ZERO << 8);
465 val |= (AFE_TDM_CH_ZERO << 12);
469 val = AFE_TDM_CH_START_O30_O31;
470 val |= (AFE_TDM_CH_START_O32_O33 << 4);
471 val |= (AFE_TDM_CH_ZERO << 8);
472 val |= (AFE_TDM_CH_ZERO << 12);
476 val = AFE_TDM_CH_START_O30_O31;
477 val |= (AFE_TDM_CH_START_O32_O33 << 4);
478 val |= (AFE_TDM_CH_START_O34_O35 << 8);
479 val |= (AFE_TDM_CH_ZERO << 12);
483 val = AFE_TDM_CH_START_O30_O31;
484 val |= (AFE_TDM_CH_START_O32_O33 << 4);
485 val |= (AFE_TDM_CH_START_O34_O35 << 8);
486 val |= (AFE_TDM_CH_START_O36_O37 << 12);
491 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val);
493 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
494 0x000000f0, runtime->channels << 4);
498 static int mtk_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
499 struct snd_soc_dai *dai)
501 struct snd_soc_pcm_runtime *rtd = substream->private_data;
502 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
504 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name);
507 case SNDRV_PCM_TRIGGER_START:
508 case SNDRV_PCM_TRIGGER_RESUME:
509 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
510 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0);
512 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */
513 regmap_write(afe->regmap, AFE_HDMI_CONN0,
514 AFE_HDMI_CONN0_O30_I30 | AFE_HDMI_CONN0_O31_I31 |
515 AFE_HDMI_CONN0_O32_I34 | AFE_HDMI_CONN0_O33_I35 |
516 AFE_HDMI_CONN0_O34_I32 | AFE_HDMI_CONN0_O35_I33 |
517 AFE_HDMI_CONN0_O36_I36 | AFE_HDMI_CONN0_O37_I37);
519 /* enable Out control */
520 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1);
523 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1);
526 case SNDRV_PCM_TRIGGER_STOP:
527 case SNDRV_PCM_TRIGGER_SUSPEND:
529 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0);
531 /* disable Out control */
532 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0);
534 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
535 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF,
536 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF);
544 static int mtk_afe_dais_startup(struct snd_pcm_substream *substream,
545 struct snd_soc_dai *dai)
547 struct snd_soc_pcm_runtime *rtd = substream->private_data;
548 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
549 struct snd_pcm_runtime *runtime = substream->runtime;
550 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
553 memif->substream = substream;
555 snd_soc_set_runtime_hwparams(substream, &mtk_afe_hardware);
558 * Capture cannot use ping-pong buffer since hw_ptr at IRQ may be
559 * smaller than period_size due to AFE's internal buffer.
560 * This easily leads to overrun when avail_min is period_size.
561 * One more period can hold the possible unread buffer.
563 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
564 ret = snd_pcm_hw_constraint_minmax(runtime,
565 SNDRV_PCM_HW_PARAM_PERIODS,
567 mtk_afe_hardware.periods_max);
569 dev_err(afe->dev, "hw_constraint_minmax failed\n");
573 ret = snd_pcm_hw_constraint_integer(runtime,
574 SNDRV_PCM_HW_PARAM_PERIODS);
576 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n");
580 static void mtk_afe_dais_shutdown(struct snd_pcm_substream *substream,
581 struct snd_soc_dai *dai)
583 struct snd_soc_pcm_runtime *rtd = substream->private_data;
584 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
585 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
587 memif->substream = NULL;
590 static int mtk_afe_dais_hw_params(struct snd_pcm_substream *substream,
591 struct snd_pcm_hw_params *params,
592 struct snd_soc_dai *dai)
594 struct snd_soc_pcm_runtime *rtd = substream->private_data;
595 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
596 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
597 int msb_at_bit33 = 0;
601 "%s period = %u, rate= %u, channels=%u\n",
602 __func__, params_period_size(params), params_rate(params),
603 params_channels(params));
605 ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
609 msb_at_bit33 = upper_32_bits(substream->runtime->dma_addr) ? 1 : 0;
610 memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr);
611 memif->buffer_size = substream->runtime->dma_bytes;
614 regmap_write(afe->regmap,
615 memif->data->reg_ofs_base, memif->phys_buf_addr);
617 regmap_write(afe->regmap,
618 memif->data->reg_ofs_base + AFE_BASE_END_OFFSET,
619 memif->phys_buf_addr + memif->buffer_size - 1);
621 /* set MSB to 33-bit */
622 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
623 1 << memif->data->msb_shift,
624 msb_at_bit33 << memif->data->msb_shift);
627 if (memif->data->mono_shift >= 0) {
628 unsigned int mono = (params_channels(params) == 1) ? 1 : 0;
630 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
631 1 << memif->data->mono_shift,
632 mono << memif->data->mono_shift);
636 if (memif->data->fs_shift < 0)
638 if (memif->data->id == MTK_AFE_MEMIF_DAI ||
639 memif->data->id == MTK_AFE_MEMIF_MOD_DAI) {
642 switch (params_rate(params)) {
656 if (memif->data->id == MTK_AFE_MEMIF_DAI)
657 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
658 0x3 << memif->data->fs_shift,
659 val << memif->data->fs_shift);
661 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
662 0x3 << memif->data->fs_shift,
663 val << memif->data->fs_shift);
666 int fs = mtk_afe_i2s_fs(params_rate(params));
671 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
672 0xf << memif->data->fs_shift,
673 fs << memif->data->fs_shift);
679 static int mtk_afe_dais_hw_free(struct snd_pcm_substream *substream,
680 struct snd_soc_dai *dai)
682 return snd_pcm_lib_free_pages(substream);
685 static int mtk_afe_dais_trigger(struct snd_pcm_substream *substream, int cmd,
686 struct snd_soc_dai *dai)
688 struct snd_soc_pcm_runtime *rtd = substream->private_data;
689 struct snd_pcm_runtime * const runtime = substream->runtime;
690 struct mtk_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
691 struct mtk_afe_memif *memif = &afe->memif[rtd->cpu_dai->id];
692 unsigned int counter = runtime->period_size;
694 dev_info(afe->dev, "%s %s cmd=%d\n", __func__, memif->data->name, cmd);
697 case SNDRV_PCM_TRIGGER_START:
698 case SNDRV_PCM_TRIGGER_RESUME:
699 if (memif->data->enable_shift >= 0)
700 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
701 1 << memif->data->enable_shift,
702 1 << memif->data->enable_shift);
704 /* set irq counter */
705 regmap_update_bits(afe->regmap,
706 memif->data->irq_reg_cnt,
707 0x3ffff << memif->data->irq_cnt_shift,
708 counter << memif->data->irq_cnt_shift);
711 if (memif->data->irq_fs_shift >= 0) {
712 int fs = mtk_afe_i2s_fs(runtime->rate);
717 regmap_update_bits(afe->regmap,
719 0xf << memif->data->irq_fs_shift,
720 fs << memif->data->irq_fs_shift);
722 /* enable interrupt */
723 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
724 1 << memif->data->irq_en_shift,
725 1 << memif->data->irq_en_shift);
728 case SNDRV_PCM_TRIGGER_STOP:
729 case SNDRV_PCM_TRIGGER_SUSPEND:
730 if (memif->data->enable_shift >= 0)
731 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
732 1 << memif->data->enable_shift, 0);
733 /* disable interrupt */
734 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CON,
735 1 << memif->data->irq_en_shift,
736 0 << memif->data->irq_en_shift);
737 /* and clear pending IRQ */
738 regmap_write(afe->regmap, AFE_IRQ_CLR,
739 1 << memif->data->irq_clr_shift);
747 static const struct snd_soc_dai_ops mtk_afe_dai_ops = {
748 .startup = mtk_afe_dais_startup,
749 .shutdown = mtk_afe_dais_shutdown,
750 .hw_params = mtk_afe_dais_hw_params,
751 .hw_free = mtk_afe_dais_hw_free,
752 .trigger = mtk_afe_dais_trigger,
756 static const struct snd_soc_dai_ops mtk_afe_i2s_ops = {
757 .startup = mtk_afe_i2s_startup,
758 .shutdown = mtk_afe_i2s_shutdown,
759 .prepare = mtk_afe_i2s_prepare,
762 static const struct snd_soc_dai_ops mtk_afe_hdmi_ops = {
763 .startup = mtk_afe_hdmi_startup,
764 .shutdown = mtk_afe_hdmi_shutdown,
765 .prepare = mtk_afe_hdmi_prepare,
766 .trigger = mtk_afe_hdmi_trigger,
770 static int mtk_afe_runtime_suspend(struct device *dev);
771 static int mtk_afe_runtime_resume(struct device *dev);
773 static int mtk_afe_dai_suspend(struct snd_soc_dai *dai)
775 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
778 dev_dbg(afe->dev, "%s\n", __func__);
779 if (pm_runtime_status_suspended(afe->dev) || afe->suspended)
782 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
783 regmap_read(afe->regmap, mtk_afe_backup_list[i],
784 &afe->backup_regs[i]);
786 afe->suspended = true;
787 mtk_afe_runtime_suspend(afe->dev);
791 static int mtk_afe_dai_resume(struct snd_soc_dai *dai)
793 struct mtk_afe *afe = snd_soc_dai_get_drvdata(dai);
796 dev_dbg(afe->dev, "%s\n", __func__);
797 if (pm_runtime_status_suspended(afe->dev) || !afe->suspended)
800 mtk_afe_runtime_resume(afe->dev);
802 for (i = 0; i < ARRAY_SIZE(mtk_afe_backup_list); i++)
803 regmap_write(afe->regmap, mtk_afe_backup_list[i],
804 afe->backup_regs[i]);
806 afe->suspended = false;
810 static struct snd_soc_dai_driver mtk_afe_pcm_dais[] = {
811 /* FE DAIs: memory intefaces to CPU */
813 .name = "DL1", /* downlink 1 */
814 .id = MTK_AFE_MEMIF_DL1,
815 .suspend = mtk_afe_dai_suspend,
816 .resume = mtk_afe_dai_resume,
818 .stream_name = "DL1",
821 .rates = SNDRV_PCM_RATE_8000_48000,
822 .formats = SNDRV_PCM_FMTBIT_S16_LE,
824 .ops = &mtk_afe_dai_ops,
826 .name = "VUL", /* voice uplink */
827 .id = MTK_AFE_MEMIF_VUL,
828 .suspend = mtk_afe_dai_suspend,
829 .resume = mtk_afe_dai_resume,
831 .stream_name = "VUL",
834 .rates = SNDRV_PCM_RATE_8000_48000,
835 .formats = SNDRV_PCM_FMTBIT_S16_LE,
837 .ops = &mtk_afe_dai_ops,
841 .id = MTK_AFE_IO_I2S,
843 .stream_name = "I2S Playback",
846 .rates = SNDRV_PCM_RATE_8000_48000,
847 .formats = SNDRV_PCM_FMTBIT_S16_LE,
850 .stream_name = "I2S Capture",
853 .rates = SNDRV_PCM_RATE_8000_48000,
854 .formats = SNDRV_PCM_FMTBIT_S16_LE,
856 .ops = &mtk_afe_i2s_ops,
857 .symmetric_rates = 1,
861 static struct snd_soc_dai_driver mtk_afe_hdmi_dais[] = {
865 .id = MTK_AFE_MEMIF_HDMI,
866 .suspend = mtk_afe_dai_suspend,
867 .resume = mtk_afe_dai_resume,
869 .stream_name = "HDMI",
872 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
873 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
874 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
875 SNDRV_PCM_RATE_192000,
876 .formats = SNDRV_PCM_FMTBIT_S16_LE,
878 .ops = &mtk_afe_dai_ops,
882 .id = MTK_AFE_IO_HDMI,
884 .stream_name = "HDMIO Playback",
887 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
888 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
889 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
890 SNDRV_PCM_RATE_192000,
891 .formats = SNDRV_PCM_FMTBIT_S16_LE,
893 .ops = &mtk_afe_hdmi_ops,
897 static const struct snd_kcontrol_new mtk_afe_o03_mix[] = {
898 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0),
901 static const struct snd_kcontrol_new mtk_afe_o04_mix[] = {
902 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0),
905 static const struct snd_kcontrol_new mtk_afe_o09_mix[] = {
906 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0),
909 static const struct snd_kcontrol_new mtk_afe_o10_mix[] = {
910 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0),
913 static const struct snd_soc_dapm_widget mtk_afe_pcm_widgets[] = {
914 /* inter-connections */
915 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0),
916 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0),
917 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0),
918 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0),
920 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0,
921 mtk_afe_o03_mix, ARRAY_SIZE(mtk_afe_o03_mix)),
922 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0,
923 mtk_afe_o04_mix, ARRAY_SIZE(mtk_afe_o04_mix)),
924 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0,
925 mtk_afe_o09_mix, ARRAY_SIZE(mtk_afe_o09_mix)),
926 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0,
927 mtk_afe_o10_mix, ARRAY_SIZE(mtk_afe_o10_mix)),
930 static const struct snd_soc_dapm_route mtk_afe_pcm_routes[] = {
931 {"I05", NULL, "DL1"},
932 {"I06", NULL, "DL1"},
933 {"I2S Playback", NULL, "O03"},
934 {"I2S Playback", NULL, "O04"},
935 {"VUL", NULL, "O09"},
936 {"VUL", NULL, "O10"},
937 {"I17", NULL, "I2S Capture"},
938 {"I18", NULL, "I2S Capture"},
939 { "O03", "I05 Switch", "I05" },
940 { "O04", "I06 Switch", "I06" },
941 { "O09", "I17 Switch", "I17" },
942 { "O10", "I18 Switch", "I18" },
945 static const struct snd_soc_dapm_route mtk_afe_hdmi_routes[] = {
946 {"HDMIO Playback", NULL, "HDMI"},
949 static const struct snd_soc_component_driver mtk_afe_pcm_dai_component = {
950 .name = "mtk-afe-pcm-dai",
951 .dapm_widgets = mtk_afe_pcm_widgets,
952 .num_dapm_widgets = ARRAY_SIZE(mtk_afe_pcm_widgets),
953 .dapm_routes = mtk_afe_pcm_routes,
954 .num_dapm_routes = ARRAY_SIZE(mtk_afe_pcm_routes),
957 static const struct snd_soc_component_driver mtk_afe_hdmi_dai_component = {
958 .name = "mtk-afe-hdmi-dai",
959 .dapm_routes = mtk_afe_hdmi_routes,
960 .num_dapm_routes = ARRAY_SIZE(mtk_afe_hdmi_routes),
963 static const char *aud_clks[MTK_CLK_NUM] = {
964 [MTK_CLK_INFRASYS_AUD] = "infra_sys_audio_clk",
965 [MTK_CLK_TOP_PDN_AUD] = "top_pdn_audio",
966 [MTK_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus",
967 [MTK_CLK_I2S0_M] = "i2s0_m",
968 [MTK_CLK_I2S1_M] = "i2s1_m",
969 [MTK_CLK_I2S2_M] = "i2s2_m",
970 [MTK_CLK_I2S3_M] = "i2s3_m",
971 [MTK_CLK_I2S3_B] = "i2s3_b",
972 [MTK_CLK_BCK0] = "bck0",
973 [MTK_CLK_BCK1] = "bck1",
976 static const struct mtk_afe_memif_data memif_data[MTK_AFE_MEMIF_NUM] = {
979 .id = MTK_AFE_MEMIF_DL1,
980 .reg_ofs_base = AFE_DL1_BASE,
981 .reg_ofs_cur = AFE_DL1_CUR,
985 .irq_reg_cnt = AFE_IRQ_CNT1,
993 .id = MTK_AFE_MEMIF_DL2,
994 .reg_ofs_base = AFE_DL2_BASE,
995 .reg_ofs_cur = AFE_DL2_CUR,
999 .irq_reg_cnt = AFE_IRQ_CNT1,
1000 .irq_cnt_shift = 20,
1007 .id = MTK_AFE_MEMIF_VUL,
1008 .reg_ofs_base = AFE_VUL_BASE,
1009 .reg_ofs_cur = AFE_VUL_CUR,
1013 .irq_reg_cnt = AFE_IRQ_CNT2,
1021 .id = MTK_AFE_MEMIF_DAI,
1022 .reg_ofs_base = AFE_DAI_BASE,
1023 .reg_ofs_cur = AFE_DAI_CUR,
1027 .irq_reg_cnt = AFE_IRQ_CNT2,
1028 .irq_cnt_shift = 20,
1035 .id = MTK_AFE_MEMIF_AWB,
1036 .reg_ofs_base = AFE_AWB_BASE,
1037 .reg_ofs_cur = AFE_AWB_CUR,
1041 .irq_reg_cnt = AFE_IRQ_CNT7,
1049 .id = MTK_AFE_MEMIF_MOD_DAI,
1050 .reg_ofs_base = AFE_MOD_PCM_BASE,
1051 .reg_ofs_cur = AFE_MOD_PCM_CUR,
1055 .irq_reg_cnt = AFE_IRQ_CNT2,
1056 .irq_cnt_shift = 20,
1063 .id = MTK_AFE_MEMIF_HDMI,
1064 .reg_ofs_base = AFE_HDMI_OUT_BASE,
1065 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
1069 .irq_reg_cnt = AFE_IRQ_CNT5,
1078 static const struct regmap_config mtk_afe_regmap_config = {
1082 .max_register = AFE_ADDA2_TOP_CON0,
1083 .cache_type = REGCACHE_NONE,
1086 static irqreturn_t mtk_afe_irq_handler(int irq, void *dev_id)
1088 struct mtk_afe *afe = dev_id;
1089 unsigned int reg_value;
1092 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value);
1094 dev_err(afe->dev, "%s irq status err\n", __func__);
1095 reg_value = AFE_IRQ_STATUS_BITS;
1099 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++) {
1100 struct mtk_afe_memif *memif = &afe->memif[i];
1102 if (!(reg_value & (1 << memif->data->irq_clr_shift)))
1105 snd_pcm_period_elapsed(memif->substream);
1110 regmap_write(afe->regmap, AFE_IRQ_CLR, reg_value & AFE_IRQ_STATUS_BITS);
1115 static int mtk_afe_runtime_suspend(struct device *dev)
1117 struct mtk_afe *afe = dev_get_drvdata(dev);
1120 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0);
1122 /* disable AFE clk */
1123 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
1124 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE);
1126 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1127 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK1]);
1128 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1129 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1130 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1134 static int mtk_afe_runtime_resume(struct device *dev)
1136 struct mtk_afe *afe = dev_get_drvdata(dev);
1139 ret = clk_prepare_enable(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1143 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1147 ret = clk_prepare_enable(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1149 goto err_top_aud_bus;
1151 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK0]);
1155 ret = clk_prepare_enable(afe->clocks[MTK_CLK_BCK1]);
1159 /* enable AFE clk */
1160 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0);
1162 /* set O3/O4 16bits */
1163 regmap_update_bits(afe->regmap, AFE_CONN_24BIT,
1164 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0);
1166 /* unmask all IRQs */
1167 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff);
1170 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1174 clk_disable_unprepare(afe->clocks[MTK_CLK_BCK0]);
1176 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD]);
1178 clk_disable_unprepare(afe->clocks[MTK_CLK_TOP_PDN_AUD_BUS]);
1180 clk_disable_unprepare(afe->clocks[MTK_CLK_INFRASYS_AUD]);
1184 static int mtk_afe_init_audio_clk(struct mtk_afe *afe)
1188 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) {
1189 afe->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1190 if (IS_ERR(afe->clocks[i])) {
1191 dev_err(afe->dev, "%s devm_clk_get %s fail\n",
1192 __func__, aud_clks[i]);
1193 return PTR_ERR(afe->clocks[i]);
1196 clk_set_rate(afe->clocks[MTK_CLK_BCK0], 22579200); /* 22M */
1197 clk_set_rate(afe->clocks[MTK_CLK_BCK1], 24576000); /* 24M */
1201 static int mtk_afe_pcm_dev_probe(struct platform_device *pdev)
1204 unsigned int irq_id;
1205 struct mtk_afe *afe;
1206 struct resource *res;
1208 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
1212 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1216 afe->dev = &pdev->dev;
1218 irq_id = platform_get_irq(pdev, 0);
1220 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1223 ret = devm_request_irq(afe->dev, irq_id, mtk_afe_irq_handler,
1224 0, "Afe_ISR_Handle", (void *)afe);
1226 dev_err(afe->dev, "could not request_irq\n");
1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1231 afe->base_addr = devm_ioremap_resource(&pdev->dev, res);
1232 if (IS_ERR(afe->base_addr))
1233 return PTR_ERR(afe->base_addr);
1235 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1236 &mtk_afe_regmap_config);
1237 if (IS_ERR(afe->regmap))
1238 return PTR_ERR(afe->regmap);
1240 /* initial audio related clock */
1241 ret = mtk_afe_init_audio_clk(afe);
1243 dev_err(afe->dev, "mtk_afe_init_audio_clk fail\n");
1247 for (i = 0; i < MTK_AFE_MEMIF_NUM; i++)
1248 afe->memif[i].data = &memif_data[i];
1250 platform_set_drvdata(pdev, afe);
1252 pm_runtime_enable(&pdev->dev);
1253 if (!pm_runtime_enabled(&pdev->dev)) {
1254 ret = mtk_afe_runtime_resume(&pdev->dev);
1256 goto err_pm_disable;
1259 ret = snd_soc_register_platform(&pdev->dev, &mtk_afe_pcm_platform);
1261 goto err_pm_disable;
1263 ret = snd_soc_register_component(&pdev->dev,
1264 &mtk_afe_pcm_dai_component,
1266 ARRAY_SIZE(mtk_afe_pcm_dais));
1270 ret = snd_soc_register_component(&pdev->dev,
1271 &mtk_afe_hdmi_dai_component,
1273 ARRAY_SIZE(mtk_afe_hdmi_dais));
1277 dev_info(&pdev->dev, "MTK AFE driver initialized.\n");
1281 snd_soc_unregister_component(&pdev->dev);
1283 snd_soc_unregister_platform(&pdev->dev);
1285 pm_runtime_disable(&pdev->dev);
1289 static int mtk_afe_pcm_dev_remove(struct platform_device *pdev)
1291 pm_runtime_disable(&pdev->dev);
1292 if (!pm_runtime_status_suspended(&pdev->dev))
1293 mtk_afe_runtime_suspend(&pdev->dev);
1294 snd_soc_unregister_component(&pdev->dev);
1295 snd_soc_unregister_platform(&pdev->dev);
1299 static const struct of_device_id mtk_afe_pcm_dt_match[] = {
1300 { .compatible = "mediatek,mt8173-afe-pcm", },
1303 MODULE_DEVICE_TABLE(of, mtk_afe_pcm_dt_match);
1305 static const struct dev_pm_ops mtk_afe_pm_ops = {
1306 SET_RUNTIME_PM_OPS(mtk_afe_runtime_suspend, mtk_afe_runtime_resume,
1310 static struct platform_driver mtk_afe_pcm_driver = {
1312 .name = "mtk-afe-pcm",
1313 .of_match_table = mtk_afe_pcm_dt_match,
1314 .pm = &mtk_afe_pm_ops,
1316 .probe = mtk_afe_pcm_dev_probe,
1317 .remove = mtk_afe_pcm_dev_remove,
1320 module_platform_driver(mtk_afe_pcm_driver);
1322 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver");
1323 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>");
1324 MODULE_LICENSE("GPL v2");