2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/time.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/saif.h>
33 #include <asm/mach-types.h>
34 #include <mach/hardware.h>
39 static struct mxs_saif *mxs_saif[2];
42 * SAIF is a little different with other normal SOC DAIs on clock using.
44 * For MXS, two SAIF modules are instantiated on-chip.
45 * Each SAIF has a set of clock pins and can be operating in master
46 * mode simultaneously if they are connected to different off-chip codecs.
47 * Also, one of the two SAIFs can master or drive the clock pins while the
48 * other SAIF, in slave mode, receives clocking from the master SAIF.
49 * This also means that both SAIFs must operate at the same sample rate.
51 * We abstract this as each saif has a master, the master could be
52 * himself or other saifs. In the generic saif driver, saif does not need
53 * to know the different clkmux. Saif only needs to know who is his master
54 * and operating his master to generate the proper clock rate for him.
55 * The master id is provided in mach-specific layer according to different
59 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
60 int clk_id, unsigned int freq, int dir)
62 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
75 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
76 * is provided by other SAIF, we provide a interface here to get its master
78 * Note that the master could be himself.
80 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
82 return mxs_saif[saif->master_id];
86 * Set SAIF clock and MCLK
88 static int mxs_saif_set_clk(struct mxs_saif *saif,
94 struct mxs_saif *master_saif;
96 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
98 /* Set master saif to generate proper clock */
99 master_saif = mxs_saif_get_master(saif);
103 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
105 /* Checking if can playback and capture simutaneously */
106 if (master_saif->ongoing && rate != master_saif->cur_rate) {
108 "can not change clock, master saif%d(rate %d) is ongoing\n",
109 master_saif->id, master_saif->cur_rate);
113 scr = __raw_readl(master_saif->base + SAIF_CTRL);
114 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
115 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
120 * The SAIF clock should be either 384*fs or 512*fs.
121 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
122 * For 32x mclk, set saif clk as 512*fs.
123 * For 48x mclk, set saif clk as 384*fs.
125 * If MCLK is not used, we just set saif clk to 512*fs.
127 clk_prepare_enable(master_saif->clk);
129 if (master_saif->mclk_in_use) {
130 if (mclk % 32 == 0) {
131 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
132 ret = clk_set_rate(master_saif->clk, 512 * rate);
133 } else if (mclk % 48 == 0) {
134 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
135 ret = clk_set_rate(master_saif->clk, 384 * rate);
137 /* SAIF MCLK should be either 32x or 48x */
138 clk_disable_unprepare(master_saif->clk);
142 ret = clk_set_rate(master_saif->clk, 512 * rate);
143 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
146 clk_disable_unprepare(master_saif->clk);
151 master_saif->cur_rate = rate;
153 if (!master_saif->mclk_in_use) {
154 __raw_writel(scr, master_saif->base + SAIF_CTRL);
159 * Program the over-sample rate for MCLK output
161 * The available MCLK range is 32x, 48x... 512x. The rate
162 * could be from 8kHz to 192kH.
164 switch (mclk / rate) {
166 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
196 __raw_writel(scr, master_saif->base + SAIF_CTRL);
202 * Put and disable MCLK.
204 int mxs_saif_put_mclk(unsigned int saif_id)
206 struct mxs_saif *saif = mxs_saif[saif_id];
212 stat = __raw_readl(saif->base + SAIF_STAT);
213 if (stat & BM_SAIF_STAT_BUSY) {
214 dev_err(saif->dev, "error: busy\n");
218 clk_disable_unprepare(saif->clk);
220 /* disable MCLK output */
221 __raw_writel(BM_SAIF_CTRL_CLKGATE,
222 saif->base + SAIF_CTRL + MXS_SET_ADDR);
223 __raw_writel(BM_SAIF_CTRL_RUN,
224 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
226 saif->mclk_in_use = 0;
231 * Get MCLK and set clock rate, then enable it
233 * This interface is used for codecs who are using MCLK provided
236 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
239 struct mxs_saif *saif = mxs_saif[saif_id];
242 struct mxs_saif *master_saif;
248 __raw_writel(BM_SAIF_CTRL_SFTRST,
249 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
251 /* FIXME: need clear clk gate for register r/w */
252 __raw_writel(BM_SAIF_CTRL_CLKGATE,
253 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
255 master_saif = mxs_saif_get_master(saif);
256 if (saif != master_saif) {
257 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
261 stat = __raw_readl(saif->base + SAIF_STAT);
262 if (stat & BM_SAIF_STAT_BUSY) {
263 dev_err(saif->dev, "error: busy\n");
267 saif->mclk_in_use = 1;
268 ret = mxs_saif_set_clk(saif, mclk, rate);
272 ret = clk_prepare_enable(saif->clk);
276 /* enable MCLK output */
277 __raw_writel(BM_SAIF_CTRL_RUN,
278 saif->base + SAIF_CTRL + MXS_SET_ADDR);
284 * SAIF DAI format configuration.
285 * Should only be called when port is inactive.
287 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
291 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
293 stat = __raw_readl(saif->base + SAIF_STAT);
294 if (stat & BM_SAIF_STAT_BUSY) {
295 dev_err(cpu_dai->dev, "error: busy\n");
299 scr0 = __raw_readl(saif->base + SAIF_CTRL);
300 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
301 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
305 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
306 case SND_SOC_DAIFMT_I2S:
307 /* data frame low 1clk before data */
308 scr |= BM_SAIF_CTRL_DELAY;
309 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
311 case SND_SOC_DAIFMT_LEFT_J:
312 /* data frame high with data */
313 scr &= ~BM_SAIF_CTRL_DELAY;
314 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
315 scr &= ~BM_SAIF_CTRL_JUSTIFY;
321 /* DAI clock inversion */
322 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
323 case SND_SOC_DAIFMT_IB_IF:
324 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
325 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
327 case SND_SOC_DAIFMT_IB_NF:
328 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
329 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
331 case SND_SOC_DAIFMT_NB_IF:
332 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
333 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
335 case SND_SOC_DAIFMT_NB_NF:
336 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
337 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
342 * Note: We simply just support master mode since SAIF TX can only
344 * Here the master is relative to codec side.
345 * Saif internally could be slave when working on EXTMASTER mode.
346 * We just hide this to machine driver.
348 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
349 case SND_SOC_DAIFMT_CBS_CFS:
350 if (saif->id == saif->master_id)
351 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
353 scr |= BM_SAIF_CTRL_SLAVE_MODE;
355 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
364 static int mxs_saif_startup(struct snd_pcm_substream *substream,
365 struct snd_soc_dai *cpu_dai)
367 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
368 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
370 /* clear error status to 0 for each re-open */
371 saif->fifo_underrun = 0;
372 saif->fifo_overrun = 0;
374 /* Clear Reset for normal operations */
375 __raw_writel(BM_SAIF_CTRL_SFTRST,
376 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
378 /* clear clock gate */
379 __raw_writel(BM_SAIF_CTRL_CLKGATE,
380 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
386 * Should only be called when port is inactive.
387 * although can be called multiple times by upper layers.
389 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
390 struct snd_pcm_hw_params *params,
391 struct snd_soc_dai *cpu_dai)
393 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
397 /* mclk should already be set */
398 if (!saif->mclk && saif->mclk_in_use) {
399 dev_err(cpu_dai->dev, "set mclk first\n");
403 stat = __raw_readl(saif->base + SAIF_STAT);
404 if (stat & BM_SAIF_STAT_BUSY) {
405 dev_err(cpu_dai->dev, "error: busy\n");
410 * Set saif clk based on sample rate.
411 * If mclk is used, we also set mclk, if not, saif->mclk is
412 * default 0, means not used.
414 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
416 dev_err(cpu_dai->dev, "unable to get proper clk\n");
420 scr = __raw_readl(saif->base + SAIF_CTRL);
422 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
423 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
424 switch (params_format(params)) {
425 case SNDRV_PCM_FORMAT_S16_LE:
426 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
428 case SNDRV_PCM_FORMAT_S20_3LE:
429 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
430 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
432 case SNDRV_PCM_FORMAT_S24_LE:
433 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
434 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
441 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
443 scr &= ~BM_SAIF_CTRL_READ_MODE;
446 scr |= BM_SAIF_CTRL_READ_MODE;
449 __raw_writel(scr, saif->base + SAIF_CTRL);
453 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
454 struct snd_soc_dai *cpu_dai)
456 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
458 /* enable FIFO error irqs */
459 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
460 saif->base + SAIF_CTRL + MXS_SET_ADDR);
465 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
466 struct snd_soc_dai *cpu_dai)
468 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
469 struct mxs_saif *master_saif;
472 master_saif = mxs_saif_get_master(saif);
477 case SNDRV_PCM_TRIGGER_START:
478 case SNDRV_PCM_TRIGGER_RESUME:
479 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
480 dev_dbg(cpu_dai->dev, "start\n");
482 clk_enable(master_saif->clk);
483 if (!master_saif->mclk_in_use)
484 __raw_writel(BM_SAIF_CTRL_RUN,
485 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
488 * If the saif's master is not himself, we also need to enable
489 * itself clk for its internal basic logic to work.
491 if (saif != master_saif) {
492 clk_enable(saif->clk);
493 __raw_writel(BM_SAIF_CTRL_RUN,
494 saif->base + SAIF_CTRL + MXS_SET_ADDR);
497 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
499 * write a data to saif data register to trigger
502 __raw_writel(0, saif->base + SAIF_DATA);
505 * read a data from saif data register to trigger
508 __raw_readl(saif->base + SAIF_DATA);
511 master_saif->ongoing = 1;
513 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
514 __raw_readl(saif->base + SAIF_CTRL),
515 __raw_readl(saif->base + SAIF_STAT));
517 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
518 __raw_readl(master_saif->base + SAIF_CTRL),
519 __raw_readl(master_saif->base + SAIF_STAT));
521 case SNDRV_PCM_TRIGGER_SUSPEND:
522 case SNDRV_PCM_TRIGGER_STOP:
523 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
524 dev_dbg(cpu_dai->dev, "stop\n");
526 /* wait a while for the current sample to complete */
527 delay = USEC_PER_SEC / master_saif->cur_rate;
529 if (!master_saif->mclk_in_use) {
530 __raw_writel(BM_SAIF_CTRL_RUN,
531 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
534 clk_disable(master_saif->clk);
536 if (saif != master_saif) {
537 __raw_writel(BM_SAIF_CTRL_RUN,
538 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
540 clk_disable(saif->clk);
543 master_saif->ongoing = 0;
553 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
554 #define MXS_SAIF_FORMATS \
555 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
556 SNDRV_PCM_FMTBIT_S24_LE)
558 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
559 .startup = mxs_saif_startup,
560 .trigger = mxs_saif_trigger,
561 .prepare = mxs_saif_prepare,
562 .hw_params = mxs_saif_hw_params,
563 .set_sysclk = mxs_saif_set_dai_sysclk,
564 .set_fmt = mxs_saif_set_dai_fmt,
567 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
569 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
571 snd_soc_dai_set_drvdata(dai, saif);
576 static struct snd_soc_dai_driver mxs_saif_dai = {
578 .probe = mxs_saif_dai_probe,
582 .rates = MXS_SAIF_RATES,
583 .formats = MXS_SAIF_FORMATS,
588 .rates = MXS_SAIF_RATES,
589 .formats = MXS_SAIF_FORMATS,
591 .ops = &mxs_saif_dai_ops,
594 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
596 struct mxs_saif *saif = dev_id;
599 stat = __raw_readl(saif->base + SAIF_STAT);
600 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
601 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
604 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
605 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
606 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
607 saif->base + SAIF_STAT + MXS_CLR_ADDR);
610 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
611 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
612 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
613 saif->base + SAIF_STAT + MXS_CLR_ADDR);
616 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
617 __raw_readl(saif->base + SAIF_CTRL),
618 __raw_readl(saif->base + SAIF_STAT));
623 static int mxs_saif_probe(struct platform_device *pdev)
625 struct resource *iores, *dmares;
626 struct mxs_saif *saif;
627 struct mxs_saif_platform_data *pdata;
630 if (pdev->id >= ARRAY_SIZE(mxs_saif))
633 saif = kzalloc(sizeof(*saif), GFP_KERNEL);
637 mxs_saif[pdev->id] = saif;
640 pdata = pdev->dev.platform_data;
641 if (pdata && !pdata->master_mode) {
642 saif->master_id = pdata->master_id;
643 if (saif->master_id < 0 ||
644 saif->master_id >= ARRAY_SIZE(mxs_saif) ||
645 saif->master_id == saif->id) {
646 dev_err(&pdev->dev, "get wrong master id\n");
650 saif->master_id = saif->id;
653 saif->clk = clk_get(&pdev->dev, NULL);
654 if (IS_ERR(saif->clk)) {
655 ret = PTR_ERR(saif->clk);
656 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
661 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 dev_err(&pdev->dev, "failed to get io resource: %d\n",
666 goto failed_get_resource;
669 if (!request_mem_region(iores->start, resource_size(iores),
671 dev_err(&pdev->dev, "request_mem_region failed\n");
673 goto failed_get_resource;
676 saif->base = ioremap(iores->start, resource_size(iores));
678 dev_err(&pdev->dev, "ioremap failed\n");
683 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
686 dev_err(&pdev->dev, "failed to get dma resource: %d\n",
690 saif->dma_param.chan_num = dmares->start;
692 saif->irq = platform_get_irq(pdev, 0);
695 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
697 goto failed_get_irq1;
700 saif->dev = &pdev->dev;
701 ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
703 dev_err(&pdev->dev, "failed to request irq\n");
704 goto failed_get_irq1;
707 saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
708 if (saif->dma_param.chan_irq < 0) {
709 ret = saif->dma_param.chan_irq;
710 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
712 goto failed_get_irq2;
715 platform_set_drvdata(pdev, saif);
717 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
719 dev_err(&pdev->dev, "register DAI failed\n");
720 goto failed_register;
723 saif->soc_platform_pdev = platform_device_alloc(
724 "mxs-pcm-audio", pdev->id);
725 if (!saif->soc_platform_pdev) {
727 goto failed_pdev_alloc;
730 platform_set_drvdata(saif->soc_platform_pdev, saif);
731 ret = platform_device_add(saif->soc_platform_pdev);
733 dev_err(&pdev->dev, "failed to add soc platform device\n");
734 goto failed_pdev_add;
740 platform_device_put(saif->soc_platform_pdev);
742 snd_soc_unregister_dai(&pdev->dev);
745 free_irq(saif->irq, saif);
749 release_mem_region(iores->start, resource_size(iores));
758 static int __devexit mxs_saif_remove(struct platform_device *pdev)
760 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
761 struct mxs_saif *saif = platform_get_drvdata(pdev);
763 platform_device_unregister(saif->soc_platform_pdev);
765 snd_soc_unregister_dai(&pdev->dev);
768 release_mem_region(res->start, resource_size(res));
769 free_irq(saif->irq, saif);
777 static struct platform_driver mxs_saif_driver = {
778 .probe = mxs_saif_probe,
779 .remove = __devexit_p(mxs_saif_remove),
783 .owner = THIS_MODULE,
787 module_platform_driver(mxs_saif_driver);
789 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
790 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
791 MODULE_LICENSE("GPL");