2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/module.h>
20 #include <linux/init.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/time.h>
29 #include <linux/fsl/mxs-dma.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/saif.h>
36 #include <asm/mach-types.h>
37 #include <mach/hardware.h>
42 static struct mxs_saif *mxs_saif[2];
45 * SAIF is a little different with other normal SOC DAIs on clock using.
47 * For MXS, two SAIF modules are instantiated on-chip.
48 * Each SAIF has a set of clock pins and can be operating in master
49 * mode simultaneously if they are connected to different off-chip codecs.
50 * Also, one of the two SAIFs can master or drive the clock pins while the
51 * other SAIF, in slave mode, receives clocking from the master SAIF.
52 * This also means that both SAIFs must operate at the same sample rate.
54 * We abstract this as each saif has a master, the master could be
55 * himself or other saifs. In the generic saif driver, saif does not need
56 * to know the different clkmux. Saif only needs to know who is his master
57 * and operating his master to generate the proper clock rate for him.
58 * The master id is provided in mach-specific layer according to different
62 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
63 int clk_id, unsigned int freq, int dir)
65 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
78 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
79 * is provided by other SAIF, we provide a interface here to get its master
81 * Note that the master could be himself.
83 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
85 return mxs_saif[saif->master_id];
89 * Set SAIF clock and MCLK
91 static int mxs_saif_set_clk(struct mxs_saif *saif,
97 struct mxs_saif *master_saif;
99 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
101 /* Set master saif to generate proper clock */
102 master_saif = mxs_saif_get_master(saif);
106 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
108 /* Checking if can playback and capture simutaneously */
109 if (master_saif->ongoing && rate != master_saif->cur_rate) {
111 "can not change clock, master saif%d(rate %d) is ongoing\n",
112 master_saif->id, master_saif->cur_rate);
116 scr = __raw_readl(master_saif->base + SAIF_CTRL);
117 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
118 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
123 * The SAIF clock should be either 384*fs or 512*fs.
124 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
125 * For 32x mclk, set saif clk as 512*fs.
126 * For 48x mclk, set saif clk as 384*fs.
128 * If MCLK is not used, we just set saif clk to 512*fs.
130 clk_prepare_enable(master_saif->clk);
132 if (master_saif->mclk_in_use) {
133 if (mclk % 32 == 0) {
134 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
135 ret = clk_set_rate(master_saif->clk, 512 * rate);
136 } else if (mclk % 48 == 0) {
137 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
138 ret = clk_set_rate(master_saif->clk, 384 * rate);
140 /* SAIF MCLK should be either 32x or 48x */
141 clk_disable_unprepare(master_saif->clk);
145 ret = clk_set_rate(master_saif->clk, 512 * rate);
146 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
149 clk_disable_unprepare(master_saif->clk);
154 master_saif->cur_rate = rate;
156 if (!master_saif->mclk_in_use) {
157 __raw_writel(scr, master_saif->base + SAIF_CTRL);
162 * Program the over-sample rate for MCLK output
164 * The available MCLK range is 32x, 48x... 512x. The rate
165 * could be from 8kHz to 192kH.
167 switch (mclk / rate) {
169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
193 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
199 __raw_writel(scr, master_saif->base + SAIF_CTRL);
205 * Put and disable MCLK.
207 int mxs_saif_put_mclk(unsigned int saif_id)
209 struct mxs_saif *saif = mxs_saif[saif_id];
215 stat = __raw_readl(saif->base + SAIF_STAT);
216 if (stat & BM_SAIF_STAT_BUSY) {
217 dev_err(saif->dev, "error: busy\n");
221 clk_disable_unprepare(saif->clk);
223 /* disable MCLK output */
224 __raw_writel(BM_SAIF_CTRL_CLKGATE,
225 saif->base + SAIF_CTRL + MXS_SET_ADDR);
226 __raw_writel(BM_SAIF_CTRL_RUN,
227 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
229 saif->mclk_in_use = 0;
234 * Get MCLK and set clock rate, then enable it
236 * This interface is used for codecs who are using MCLK provided
239 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
242 struct mxs_saif *saif = mxs_saif[saif_id];
245 struct mxs_saif *master_saif;
251 __raw_writel(BM_SAIF_CTRL_SFTRST,
252 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
254 /* FIXME: need clear clk gate for register r/w */
255 __raw_writel(BM_SAIF_CTRL_CLKGATE,
256 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
258 master_saif = mxs_saif_get_master(saif);
259 if (saif != master_saif) {
260 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
264 stat = __raw_readl(saif->base + SAIF_STAT);
265 if (stat & BM_SAIF_STAT_BUSY) {
266 dev_err(saif->dev, "error: busy\n");
270 saif->mclk_in_use = 1;
271 ret = mxs_saif_set_clk(saif, mclk, rate);
275 ret = clk_prepare_enable(saif->clk);
279 /* enable MCLK output */
280 __raw_writel(BM_SAIF_CTRL_RUN,
281 saif->base + SAIF_CTRL + MXS_SET_ADDR);
287 * SAIF DAI format configuration.
288 * Should only be called when port is inactive.
290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
296 stat = __raw_readl(saif->base + SAIF_STAT);
297 if (stat & BM_SAIF_STAT_BUSY) {
298 dev_err(cpu_dai->dev, "error: busy\n");
302 scr0 = __raw_readl(saif->base + SAIF_CTRL);
303 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
304 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
309 case SND_SOC_DAIFMT_I2S:
310 /* data frame low 1clk before data */
311 scr |= BM_SAIF_CTRL_DELAY;
312 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
314 case SND_SOC_DAIFMT_LEFT_J:
315 /* data frame high with data */
316 scr &= ~BM_SAIF_CTRL_DELAY;
317 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
318 scr &= ~BM_SAIF_CTRL_JUSTIFY;
324 /* DAI clock inversion */
325 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
326 case SND_SOC_DAIFMT_IB_IF:
327 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
328 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
330 case SND_SOC_DAIFMT_IB_NF:
331 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
334 case SND_SOC_DAIFMT_NB_IF:
335 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
336 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
338 case SND_SOC_DAIFMT_NB_NF:
339 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
340 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
345 * Note: We simply just support master mode since SAIF TX can only
347 * Here the master is relative to codec side.
348 * Saif internally could be slave when working on EXTMASTER mode.
349 * We just hide this to machine driver.
351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
352 case SND_SOC_DAIFMT_CBS_CFS:
353 if (saif->id == saif->master_id)
354 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
356 scr |= BM_SAIF_CTRL_SLAVE_MODE;
358 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
367 static int mxs_saif_startup(struct snd_pcm_substream *substream,
368 struct snd_soc_dai *cpu_dai)
370 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
371 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
373 /* clear error status to 0 for each re-open */
374 saif->fifo_underrun = 0;
375 saif->fifo_overrun = 0;
377 /* Clear Reset for normal operations */
378 __raw_writel(BM_SAIF_CTRL_SFTRST,
379 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
381 /* clear clock gate */
382 __raw_writel(BM_SAIF_CTRL_CLKGATE,
383 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
389 * Should only be called when port is inactive.
390 * although can be called multiple times by upper layers.
392 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
393 struct snd_pcm_hw_params *params,
394 struct snd_soc_dai *cpu_dai)
396 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
397 struct mxs_saif *master_saif;
401 master_saif = mxs_saif_get_master(saif);
405 /* mclk should already be set */
406 if (!saif->mclk && saif->mclk_in_use) {
407 dev_err(cpu_dai->dev, "set mclk first\n");
411 stat = __raw_readl(saif->base + SAIF_STAT);
412 if (stat & BM_SAIF_STAT_BUSY) {
413 dev_err(cpu_dai->dev, "error: busy\n");
418 * Set saif clk based on sample rate.
419 * If mclk is used, we also set mclk, if not, saif->mclk is
420 * default 0, means not used.
422 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
424 dev_err(cpu_dai->dev, "unable to get proper clk\n");
428 /* prepare clk in hw_param, enable in trigger */
429 clk_prepare(saif->clk);
430 if (saif != master_saif) {
432 * Set an initial clock rate for the saif internal logic to work
433 * properly. This is important when working in EXTMASTER mode
434 * that uses the other saif's BITCLK&LRCLK but it still needs a
435 * basic clock which should be fast enough for the internal
438 clk_enable(saif->clk);
439 ret = clk_set_rate(saif->clk, 24000000);
440 clk_disable(saif->clk);
444 clk_prepare(master_saif->clk);
447 scr = __raw_readl(saif->base + SAIF_CTRL);
449 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
450 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
451 switch (params_format(params)) {
452 case SNDRV_PCM_FORMAT_S16_LE:
453 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
455 case SNDRV_PCM_FORMAT_S20_3LE:
456 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
457 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
459 case SNDRV_PCM_FORMAT_S24_LE:
460 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
461 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
470 scr &= ~BM_SAIF_CTRL_READ_MODE;
473 scr |= BM_SAIF_CTRL_READ_MODE;
476 __raw_writel(scr, saif->base + SAIF_CTRL);
480 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
481 struct snd_soc_dai *cpu_dai)
483 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
485 /* enable FIFO error irqs */
486 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
487 saif->base + SAIF_CTRL + MXS_SET_ADDR);
492 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
493 struct snd_soc_dai *cpu_dai)
495 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
496 struct mxs_saif *master_saif;
499 master_saif = mxs_saif_get_master(saif);
504 case SNDRV_PCM_TRIGGER_START:
505 case SNDRV_PCM_TRIGGER_RESUME:
506 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
507 dev_dbg(cpu_dai->dev, "start\n");
509 clk_enable(master_saif->clk);
510 if (!master_saif->mclk_in_use)
511 __raw_writel(BM_SAIF_CTRL_RUN,
512 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
515 * If the saif's master is not himself, we also need to enable
516 * itself clk for its internal basic logic to work.
518 if (saif != master_saif) {
519 clk_enable(saif->clk);
520 __raw_writel(BM_SAIF_CTRL_RUN,
521 saif->base + SAIF_CTRL + MXS_SET_ADDR);
524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
526 * write a data to saif data register to trigger
529 __raw_writel(0, saif->base + SAIF_DATA);
532 * read a data from saif data register to trigger
535 __raw_readl(saif->base + SAIF_DATA);
538 master_saif->ongoing = 1;
540 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
541 __raw_readl(saif->base + SAIF_CTRL),
542 __raw_readl(saif->base + SAIF_STAT));
544 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
545 __raw_readl(master_saif->base + SAIF_CTRL),
546 __raw_readl(master_saif->base + SAIF_STAT));
548 case SNDRV_PCM_TRIGGER_SUSPEND:
549 case SNDRV_PCM_TRIGGER_STOP:
550 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
551 dev_dbg(cpu_dai->dev, "stop\n");
553 /* wait a while for the current sample to complete */
554 delay = USEC_PER_SEC / master_saif->cur_rate;
556 if (!master_saif->mclk_in_use) {
557 __raw_writel(BM_SAIF_CTRL_RUN,
558 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
561 clk_disable(master_saif->clk);
563 if (saif != master_saif) {
564 __raw_writel(BM_SAIF_CTRL_RUN,
565 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
567 clk_disable(saif->clk);
570 master_saif->ongoing = 0;
580 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
581 #define MXS_SAIF_FORMATS \
582 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
583 SNDRV_PCM_FMTBIT_S24_LE)
585 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
586 .startup = mxs_saif_startup,
587 .trigger = mxs_saif_trigger,
588 .prepare = mxs_saif_prepare,
589 .hw_params = mxs_saif_hw_params,
590 .set_sysclk = mxs_saif_set_dai_sysclk,
591 .set_fmt = mxs_saif_set_dai_fmt,
594 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
596 struct mxs_saif *saif = dev_get_drvdata(dai->dev);
598 snd_soc_dai_set_drvdata(dai, saif);
603 static struct snd_soc_dai_driver mxs_saif_dai = {
605 .probe = mxs_saif_dai_probe,
609 .rates = MXS_SAIF_RATES,
610 .formats = MXS_SAIF_FORMATS,
615 .rates = MXS_SAIF_RATES,
616 .formats = MXS_SAIF_FORMATS,
618 .ops = &mxs_saif_dai_ops,
621 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
623 struct mxs_saif *saif = dev_id;
626 stat = __raw_readl(saif->base + SAIF_STAT);
627 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
628 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
631 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
632 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
633 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
634 saif->base + SAIF_STAT + MXS_CLR_ADDR);
637 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
638 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
639 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
640 saif->base + SAIF_STAT + MXS_CLR_ADDR);
643 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
644 __raw_readl(saif->base + SAIF_CTRL),
645 __raw_readl(saif->base + SAIF_STAT));
650 static int __devinit mxs_saif_probe(struct platform_device *pdev)
652 struct device_node *np = pdev->dev.of_node;
653 struct resource *iores, *dmares;
654 struct mxs_saif *saif;
655 struct mxs_saif_platform_data *pdata;
656 struct pinctrl *pinctrl;
660 if (!np && pdev->id >= ARRAY_SIZE(mxs_saif))
663 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
668 struct device_node *master;
669 saif->id = of_alias_get_id(np, "saif");
673 * If there is no "fsl,saif-master" phandle, it's a saif
674 * master. Otherwise, it's a slave and its phandle points
677 master = of_parse_phandle(np, "fsl,saif-master", 0);
679 saif->master_id = saif->id;
681 saif->master_id = of_alias_get_id(master, "saif");
682 if (saif->master_id < 0)
683 return saif->master_id;
687 pdata = pdev->dev.platform_data;
688 if (pdata && !pdata->master_mode)
689 saif->master_id = pdata->master_id;
691 saif->master_id = saif->id;
694 if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) {
695 dev_err(&pdev->dev, "get wrong master id\n");
699 mxs_saif[saif->id] = saif;
701 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
702 if (IS_ERR(pinctrl)) {
703 ret = PTR_ERR(pinctrl);
707 saif->clk = clk_get(&pdev->dev, NULL);
708 if (IS_ERR(saif->clk)) {
709 ret = PTR_ERR(saif->clk);
710 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
715 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
717 saif->base = devm_request_and_ioremap(&pdev->dev, iores);
719 dev_err(&pdev->dev, "ioremap failed\n");
721 goto failed_get_resource;
724 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
727 * TODO: This is a temporary solution and should be changed
728 * to use generic DMA binding later when the helplers get in.
730 ret = of_property_read_u32(np, "fsl,saif-dma-channel",
731 &saif->dma_param.chan_num);
733 dev_err(&pdev->dev, "failed to get dma channel\n");
734 goto failed_get_resource;
737 saif->dma_param.chan_num = dmares->start;
740 saif->irq = platform_get_irq(pdev, 0);
743 dev_err(&pdev->dev, "failed to get irq resource: %d\n",
745 goto failed_get_resource;
748 saif->dev = &pdev->dev;
749 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0,
752 dev_err(&pdev->dev, "failed to request irq\n");
753 goto failed_get_resource;
756 saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
757 if (saif->dma_param.chan_irq < 0) {
758 ret = saif->dma_param.chan_irq;
759 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
761 goto failed_get_resource;
764 platform_set_drvdata(pdev, saif);
766 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
768 dev_err(&pdev->dev, "register DAI failed\n");
769 goto failed_get_resource;
772 ret = mxs_pcm_platform_register(&pdev->dev);
774 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
775 goto failed_pdev_alloc;
781 snd_soc_unregister_dai(&pdev->dev);
788 static int __devexit mxs_saif_remove(struct platform_device *pdev)
790 struct mxs_saif *saif = platform_get_drvdata(pdev);
792 mxs_pcm_platform_unregister(&pdev->dev);
793 snd_soc_unregister_dai(&pdev->dev);
799 static const struct of_device_id mxs_saif_dt_ids[] = {
800 { .compatible = "fsl,imx28-saif", },
803 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
805 static struct platform_driver mxs_saif_driver = {
806 .probe = mxs_saif_probe,
807 .remove = __devexit_p(mxs_saif_remove),
811 .owner = THIS_MODULE,
812 .of_match_table = mxs_saif_dt_ids,
816 module_platform_driver(mxs_saif_driver);
818 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
819 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
820 MODULE_LICENSE("GPL");