sound/soc/omap/mcbsp.c

   1 /*
   2  * sound/soc/omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   8  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Multichannel mode not supported.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29
  30 #include <plat/cpu.h>
  31
  32 #include "mcbsp.h"
  33
  34 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  35 {
  36         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  37
  38         if (mcbsp->pdata->reg_size == 2) {
  39                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  40                 __raw_writew((u16)val, addr);
  41         } else {
  42                 ((u32 *)mcbsp->reg_cache)[reg] = val;
  43                 __raw_writel(val, addr);
  44         }
  45 }
  46
  47 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  48 {
  49         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  50
  51         if (mcbsp->pdata->reg_size == 2) {
  52                 return !from_cache ? __raw_readw(addr) :
  53                                      ((u16 *)mcbsp->reg_cache)[reg];
  54         } else {
  55                 return !from_cache ? __raw_readl(addr) :
  56                                      ((u32 *)mcbsp->reg_cache)[reg];
  57         }
  58 }
  59
  60 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  61 {
  62         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  63 }
  64
  65 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  66 {
  67         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  68 }
  69
  70 #define MCBSP_READ(mcbsp, reg) \
  71                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  72 #define MCBSP_WRITE(mcbsp, reg, val) \
  73                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  74 #define MCBSP_READ_CACHE(mcbsp, reg) \
  75                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  76
  77 #define MCBSP_ST_READ(mcbsp, reg) \
  78                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  79 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  80                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  81
  82 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  83 {
  84         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  85         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  86                         MCBSP_READ(mcbsp, DRR2));
  87         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  88                         MCBSP_READ(mcbsp, DRR1));
  89         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  90                         MCBSP_READ(mcbsp, DXR2));
  91         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  92                         MCBSP_READ(mcbsp, DXR1));
  93         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  94                         MCBSP_READ(mcbsp, SPCR2));
  95         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  96                         MCBSP_READ(mcbsp, SPCR1));
  97         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, RCR2));
  99         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, RCR1));
 101         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, XCR2));
 103         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 104                         MCBSP_READ(mcbsp, XCR1));
 105         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SRGR2));
 107         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 108                         MCBSP_READ(mcbsp, SRGR1));
 109         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, PCR0));
 111         dev_dbg(mcbsp->dev, "***********************\n");
 112 }
 113
 114 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
 115 {
 116         struct omap_mcbsp *mcbsp = dev_id;
 117         u16 irqst;
 118
 119         irqst = MCBSP_READ(mcbsp, IRQST);
 120         dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
 121
 122         if (irqst & RSYNCERREN)
 123                 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
 124         if (irqst & RFSREN)
 125                 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
 126         if (irqst & REOFEN)
 127                 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
 128         if (irqst & RRDYEN)
 129                 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
 130         if (irqst & RUNDFLEN)
 131                 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
 132         if (irqst & ROVFLEN)
 133                 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
 134
 135         if (irqst & XSYNCERREN)
 136                 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
 137         if (irqst & XFSXEN)
 138                 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
 139         if (irqst & XEOFEN)
 140                 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
 141         if (irqst & XRDYEN)
 142                 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
 143         if (irqst & XUNDFLEN)
 144                 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
 145         if (irqst & XOVFLEN)
 146                 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
 147         if (irqst & XEMPTYEOFEN)
 148                 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
 149
 150         MCBSP_WRITE(mcbsp, IRQST, irqst);
 151
 152         return IRQ_HANDLED;
 153 }
 154
 155 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 156 {
 157         struct omap_mcbsp *mcbsp_tx = dev_id;
 158         u16 irqst_spcr2;
 159
 160         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 161         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 162
 163         if (irqst_spcr2 & XSYNC_ERR) {
 164                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 165                         irqst_spcr2);
 166                 /* Writing zero to XSYNC_ERR clears the IRQ */
 167                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 168         }
 169
 170         return IRQ_HANDLED;
 171 }
 172
 173 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 174 {
 175         struct omap_mcbsp *mcbsp_rx = dev_id;
 176         u16 irqst_spcr1;
 177
 178         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 179         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 180
 181         if (irqst_spcr1 & RSYNC_ERR) {
 182                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 183                         irqst_spcr1);
 184                 /* Writing zero to RSYNC_ERR clears the IRQ */
 185                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 186         }
 187
 188         return IRQ_HANDLED;
 189 }
 190
 191 /*
 192  * omap_mcbsp_config simply write a config to the
 193  * appropriate McBSP.
 194  * You either call this function or set the McBSP registers
 195  * by yourself before calling omap_mcbsp_start().
 196  */
 197 void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
 198                        const struct omap_mcbsp_reg_cfg *config)
 199 {
 200         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 201                         mcbsp->id, mcbsp->phys_base);
 202
 203         /* We write the given config */
 204         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 205         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 206         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 207         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 208         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 209         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 210         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 211         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 212         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 213         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 214         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 215         if (mcbsp->pdata->has_ccr) {
 216                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 217                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 218         }
 219         /* Enable wakeup behavior */
 220         if (mcbsp->pdata->has_wakeup)
 221                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 222
 223         /* Enable TX/RX sync error interrupts by default */
 224         if (mcbsp->irq)
 225                 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
 226 }
 227
 228 /**
 229  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 230  * @id - mcbsp id
 231  * @stream - indicates the direction of data flow (rx or tx)
 232  *
 233  * Returns the address of mcbsp data transmit register or data receive register
 234  * to be used by DMA for transferring/receiving data based on the value of
 235  * @stream for the requested mcbsp given by @id
 236  */
 237 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
 238                                      unsigned int stream)
 239 {
 240         int data_reg;
 241
 242         if (mcbsp->pdata->reg_size == 2) {
 243                 if (stream)
 244                         data_reg = OMAP_MCBSP_REG_DRR1;
 245                 else
 246                         data_reg = OMAP_MCBSP_REG_DXR1;
 247         } else {
 248                 if (stream)
 249                         data_reg = OMAP_MCBSP_REG_DRR;
 250                 else
 251                         data_reg = OMAP_MCBSP_REG_DXR;
 252         }
 253
 254         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 255 }
 256
 257 static void omap_st_on(struct omap_mcbsp *mcbsp)
 258 {
 259         unsigned int w;
 260
 261         if (mcbsp->pdata->enable_st_clock)
 262                 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
 263
 264         /* Enable McBSP Sidetone */
 265         w = MCBSP_READ(mcbsp, SSELCR);
 266         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 267
 268         /* Enable Sidetone from Sidetone Core */
 269         w = MCBSP_ST_READ(mcbsp, SSELCR);
 270         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 271 }
 272
 273 static void omap_st_off(struct omap_mcbsp *mcbsp)
 274 {
 275         unsigned int w;
 276
 277         w = MCBSP_ST_READ(mcbsp, SSELCR);
 278         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 279
 280         w = MCBSP_READ(mcbsp, SSELCR);
 281         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 282
 283         if (mcbsp->pdata->enable_st_clock)
 284                 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
 285 }
 286
 287 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 288 {
 289         u16 val, i;
 290
 291         val = MCBSP_ST_READ(mcbsp, SSELCR);
 292
 293         if (val & ST_COEFFWREN)
 294                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 295
 296         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 297
 298         for (i = 0; i < 128; i++)
 299                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 300
 301         i = 0;
 302
 303         val = MCBSP_ST_READ(mcbsp, SSELCR);
 304         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 305                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 306
 307         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 308
 309         if (i == 1000)
 310                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 311 }
 312
 313 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 314 {
 315         u16 w;
 316         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 317
 318         w = MCBSP_ST_READ(mcbsp, SSELCR);
 319
 320         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 321                       ST_CH1GAIN(st_data->ch1gain));
 322 }
 323
 324 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
 325 {
 326         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 327         int ret = 0;
 328
 329         if (!st_data)
 330                 return -ENOENT;
 331
 332         spin_lock_irq(&mcbsp->lock);
 333         if (channel == 0)
 334                 st_data->ch0gain = chgain;
 335         else if (channel == 1)
 336                 st_data->ch1gain = chgain;
 337         else
 338                 ret = -EINVAL;
 339
 340         if (st_data->enabled)
 341                 omap_st_chgain(mcbsp);
 342         spin_unlock_irq(&mcbsp->lock);
 343
 344         return ret;
 345 }
 346
 347 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
 348 {
 349         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 350         int ret = 0;
 351
 352         if (!st_data)
 353                 return -ENOENT;
 354
 355         spin_lock_irq(&mcbsp->lock);
 356         if (channel == 0)
 357                 *chgain = st_data->ch0gain;
 358         else if (channel == 1)
 359                 *chgain = st_data->ch1gain;
 360         else
 361                 ret = -EINVAL;
 362         spin_unlock_irq(&mcbsp->lock);
 363
 364         return ret;
 365 }
 366
 367 static int omap_st_start(struct omap_mcbsp *mcbsp)
 368 {
 369         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 370
 371         if (st_data->enabled && !st_data->running) {
 372                 omap_st_fir_write(mcbsp, st_data->taps);
 373                 omap_st_chgain(mcbsp);
 374
 375                 if (!mcbsp->free) {
 376                         omap_st_on(mcbsp);
 377                         st_data->running = 1;
 378                 }
 379         }
 380
 381         return 0;
 382 }
 383
 384 int omap_st_enable(struct omap_mcbsp *mcbsp)
 385 {
 386         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 387
 388         if (!st_data)
 389                 return -ENODEV;
 390
 391         spin_lock_irq(&mcbsp->lock);
 392         st_data->enabled = 1;
 393         omap_st_start(mcbsp);
 394         spin_unlock_irq(&mcbsp->lock);
 395
 396         return 0;
 397 }
 398
 399 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 400 {
 401         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 402
 403         if (st_data->running) {
 404                 if (!mcbsp->free) {
 405                         omap_st_off(mcbsp);
 406                         st_data->running = 0;
 407                 }
 408         }
 409
 410         return 0;
 411 }
 412
 413 int omap_st_disable(struct omap_mcbsp *mcbsp)
 414 {
 415         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 416         int ret = 0;
 417
 418         if (!st_data)
 419                 return -ENODEV;
 420
 421         spin_lock_irq(&mcbsp->lock);
 422         omap_st_stop(mcbsp);
 423         st_data->enabled = 0;
 424         spin_unlock_irq(&mcbsp->lock);
 425
 426         return ret;
 427 }
 428
 429 int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
 430 {
 431         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 432
 433         if (!st_data)
 434                 return -ENODEV;
 435
 436         return st_data->enabled;
 437 }
 438
 439 /*
 440  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 441  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 442  * for the THRSH2 register.
 443  */
 444 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 445 {
 446         if (mcbsp->pdata->buffer_size == 0)
 447                 return;
 448
 449         if (threshold && threshold <= mcbsp->max_tx_thres)
 450                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 451 }
 452
 453 /*
 454  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 455  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 456  * for the THRSH1 register.
 457  */
 458 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
 459 {
 460         if (mcbsp->pdata->buffer_size == 0)
 461                 return;
 462
 463         if (threshold && threshold <= mcbsp->max_rx_thres)
 464                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 465 }
 466
 467 /*
 468  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 469  */
 470 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
 471 {
 472         u16 buffstat;
 473
 474         if (mcbsp->pdata->buffer_size == 0)
 475                 return 0;
 476
 477         /* Returns the number of free locations in the buffer */
 478         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 479
 480         /* Number of slots are different in McBSP ports */
 481         return mcbsp->pdata->buffer_size - buffstat;
 482 }
 483
 484 /*
 485  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 486  * to reach the threshold value (when the DMA will be triggered to read it)
 487  */
 488 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
 489 {
 490         u16 buffstat, threshold;
 491
 492         if (mcbsp->pdata->buffer_size == 0)
 493                 return 0;
 494
 495         /* Returns the number of used locations in the buffer */
 496         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 497         /* RX threshold */
 498         threshold = MCBSP_READ(mcbsp, THRSH1);
 499
 500         /* Return the number of location till we reach the threshold limit */
 501         if (threshold <= buffstat)
 502                 return 0;
 503         else
 504                 return threshold - buffstat;
 505 }
 506
 507 int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
 508 {
 509         void *reg_cache;
 510         int err;
 511
 512         reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
 513         if (!reg_cache) {
 514                 return -ENOMEM;
 515         }
 516
 517         spin_lock(&mcbsp->lock);
 518         if (!mcbsp->free) {
 519                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 520                         mcbsp->id);
 521                 err = -EBUSY;
 522                 goto err_kfree;
 523         }
 524
 525         mcbsp->free = false;
 526         mcbsp->reg_cache = reg_cache;
 527         spin_unlock(&mcbsp->lock);
 528
 529         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 530                 mcbsp->pdata->ops->request(mcbsp->id - 1);
 531
 532         /*
 533          * Make sure that transmitter, receiver and sample-rate generator are
 534          * not running before activating IRQs.
 535          */
 536         MCBSP_WRITE(mcbsp, SPCR1, 0);
 537         MCBSP_WRITE(mcbsp, SPCR2, 0);
 538
 539         if (mcbsp->irq) {
 540                 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
 541                                   "McBSP", (void *)mcbsp);
 542                 if (err != 0) {
 543                         dev_err(mcbsp->dev, "Unable to request IRQ\n");
 544                         goto err_clk_disable;
 545                 }
 546         } else {
 547                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
 548                                   "McBSP TX", (void *)mcbsp);
 549                 if (err != 0) {
 550                         dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
 551                         goto err_clk_disable;
 552                 }
 553
 554                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
 555                                   "McBSP RX", (void *)mcbsp);
 556                 if (err != 0) {
 557                         dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
 558                         goto err_free_irq;
 559                 }
 560         }
 561
 562         return 0;
 563 err_free_irq:
 564         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 565 err_clk_disable:
 566         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 567                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 568
 569         /* Disable wakeup behavior */
 570         if (mcbsp->pdata->has_wakeup)
 571                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 572
 573         spin_lock(&mcbsp->lock);
 574         mcbsp->free = true;
 575         mcbsp->reg_cache = NULL;
 576 err_kfree:
 577         spin_unlock(&mcbsp->lock);
 578         kfree(reg_cache);
 579
 580         return err;
 581 }
 582
 583 void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
 584 {
 585         void *reg_cache;
 586
 587         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 588                 mcbsp->pdata->ops->free(mcbsp->id - 1);
 589
 590         /* Disable wakeup behavior */
 591         if (mcbsp->pdata->has_wakeup)
 592                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 593
 594         /* Disable interrupt requests */
 595         if (mcbsp->irq)
 596                 MCBSP_WRITE(mcbsp, IRQEN, 0);
 597
 598         if (mcbsp->irq) {
 599                 free_irq(mcbsp->irq, (void *)mcbsp);
 600         } else {
 601                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 602                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 603         }
 604
 605         reg_cache = mcbsp->reg_cache;
 606
 607         /*
 608          * Select CLKS source from internal source unconditionally before
 609          * marking the McBSP port as free.
 610          * If the external clock source via MCBSP_CLKS pin has been selected the
 611          * system will refuse to enter idle if the CLKS pin source is not reset
 612          * back to internal source.
 613          */
 614         if (!cpu_class_is_omap1())
 615                 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
 616
 617         spin_lock(&mcbsp->lock);
 618         if (mcbsp->free)
 619                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 620         else
 621                 mcbsp->free = true;
 622         mcbsp->reg_cache = NULL;
 623         spin_unlock(&mcbsp->lock);
 624
 625         if (reg_cache)
 626                 kfree(reg_cache);
 627 }
 628
 629 /*
 630  * Here we start the McBSP, by enabling transmitter, receiver or both.
 631  * If no transmitter or receiver is active prior calling, then sample-rate
 632  * generator and frame sync are started.
 633  */
 634 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
 635 {
 636         int enable_srg = 0;
 637         u16 w;
 638
 639         if (mcbsp->st_data)
 640                 omap_st_start(mcbsp);
 641
 642         /* Only enable SRG, if McBSP is master */
 643         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 644         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 645                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 646                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 647
 648         if (enable_srg) {
 649                 /* Start the sample generator */
 650                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 651                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 652         }
 653
 654         /* Enable transmitter and receiver */
 655         tx &= 1;
 656         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 657         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 658
 659         rx &= 1;
 660         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 661         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 662
 663         /*
 664          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 665          * REVISIT: 100us may give enough time for two CLKSRG, however
 666          * due to some unknown PM related, clock gating etc. reason it
 667          * is now at 500us.
 668          */
 669         udelay(500);
 670
 671         if (enable_srg) {
 672                 /* Start frame sync */
 673                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 674                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 675         }
 676
 677         if (mcbsp->pdata->has_ccr) {
 678                 /* Release the transmitter and receiver */
 679                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 680                 w &= ~(tx ? XDISABLE : 0);
 681                 MCBSP_WRITE(mcbsp, XCCR, w);
 682                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 683                 w &= ~(rx ? RDISABLE : 0);
 684                 MCBSP_WRITE(mcbsp, RCCR, w);
 685         }
 686
 687         /* Dump McBSP Regs */
 688         omap_mcbsp_dump_reg(mcbsp);
 689 }
 690
 691 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
 692 {
 693         int idle;
 694         u16 w;
 695
 696         /* Reset transmitter */
 697         tx &= 1;
 698         if (mcbsp->pdata->has_ccr) {
 699                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 700                 w |= (tx ? XDISABLE : 0);
 701                 MCBSP_WRITE(mcbsp, XCCR, w);
 702         }
 703         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 704         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 705
 706         /* Reset receiver */
 707         rx &= 1;
 708         if (mcbsp->pdata->has_ccr) {
 709                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 710                 w |= (rx ? RDISABLE : 0);
 711                 MCBSP_WRITE(mcbsp, RCCR, w);
 712         }
 713         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 714         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 715
 716         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 717                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 718
 719         if (idle) {
 720                 /* Reset the sample rate generator */
 721                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 722                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 723         }
 724
 725         if (mcbsp->st_data)
 726                 omap_st_stop(mcbsp);
 727 }
 728
 729 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
 730 {
 731         const char *src;
 732
 733         if (fck_src_id == MCBSP_CLKS_PAD_SRC)
 734                 src = "clks_ext";
 735         else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
 736                 src = "clks_fclk";
 737         else
 738                 return -EINVAL;
 739
 740         if (mcbsp->pdata->set_clk_src)
 741                 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
 742         else
 743                 return -EINVAL;
 744 }
 745
 746 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
 747 {
 748         const char *signal, *src;
 749
 750         if (!mcbsp->pdata->mux_signal)
 751                 return -EINVAL;
 752
 753         switch (mux) {
 754         case CLKR_SRC_CLKR:
 755                 signal = "clkr";
 756                 src = "clkr";
 757                 break;
 758         case CLKR_SRC_CLKX:
 759                 signal = "clkr";
 760                 src = "clkx";
 761                 break;
 762         case FSR_SRC_FSR:
 763                 signal = "fsr";
 764                 src = "fsr";
 765                 break;
 766         case FSR_SRC_FSX:
 767                 signal = "fsr";
 768                 src = "fsx";
 769                 break;
 770         default:
 771                 return -EINVAL;
 772         }
 773
 774         return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
 775 }
 776
 777 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 778 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 779 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 780 static ssize_t prop##_show(struct device *dev,                          \
 781                         struct device_attribute *attr, char *buf)       \
 782 {                                                                       \
 783         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 784                                                                         \
 785         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 786 }                                                                       \
 787                                                                         \
 788 static ssize_t prop##_store(struct device *dev,                         \
 789                                 struct device_attribute *attr,          \
 790                                 const char *buf, size_t size)           \
 791 {                                                                       \
 792         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 793         unsigned long val;                                              \
 794         int status;                                                     \
 795                                                                         \
 796         status = strict_strtoul(buf, 0, &val);                          \
 797         if (status)                                                     \
 798                 return status;                                          \
 799                                                                         \
 800         if (!valid_threshold(mcbsp, val))                               \
 801                 return -EDOM;                                           \
 802                                                                         \
 803         mcbsp->prop = val;                                              \
 804         return size;                                                    \
 805 }                                                                       \
 806                                                                         \
 807 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
 808
 809 THRESHOLD_PROP_BUILDER(max_tx_thres);
 810 THRESHOLD_PROP_BUILDER(max_rx_thres);
 811
 812 static const char *dma_op_modes[] = {
 813         "element", "threshold",
 814 };
 815
 816 static ssize_t dma_op_mode_show(struct device *dev,
 817                         struct device_attribute *attr, char *buf)
 818 {
 819         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 820         int dma_op_mode, i = 0;
 821         ssize_t len = 0;
 822         const char * const *s;
 823
 824         dma_op_mode = mcbsp->dma_op_mode;
 825
 826         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
 827                 if (dma_op_mode == i)
 828                         len += sprintf(buf + len, "[%s] ", *s);
 829                 else
 830                         len += sprintf(buf + len, "%s ", *s);
 831         }
 832         len += sprintf(buf + len, "\n");
 833
 834         return len;
 835 }
 836
 837 static ssize_t dma_op_mode_store(struct device *dev,
 838                                 struct device_attribute *attr,
 839                                 const char *buf, size_t size)
 840 {
 841         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 842         const char * const *s;
 843         int i = 0;
 844
 845         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
 846                 if (sysfs_streq(buf, *s))
 847                         break;
 848
 849         if (i == ARRAY_SIZE(dma_op_modes))
 850                 return -EINVAL;
 851
 852         spin_lock_irq(&mcbsp->lock);
 853         if (!mcbsp->free) {
 854                 size = -EBUSY;
 855                 goto unlock;
 856         }
 857         mcbsp->dma_op_mode = i;
 858
 859 unlock:
 860         spin_unlock_irq(&mcbsp->lock);
 861
 862         return size;
 863 }
 864
 865 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
 866
 867 static const struct attribute *additional_attrs[] = {
 868         &dev_attr_max_tx_thres.attr,
 869         &dev_attr_max_rx_thres.attr,
 870         &dev_attr_dma_op_mode.attr,
 871         NULL,
 872 };
 873
 874 static const struct attribute_group additional_attr_group = {
 875         .attrs = (struct attribute **)additional_attrs,
 876 };
 877
 878 static ssize_t st_taps_show(struct device *dev,
 879                             struct device_attribute *attr, char *buf)
 880 {
 881         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 882         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 883         ssize_t status = 0;
 884         int i;
 885
 886         spin_lock_irq(&mcbsp->lock);
 887         for (i = 0; i < st_data->nr_taps; i++)
 888                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
 889                                   st_data->taps[i]);
 890         if (i)
 891                 status += sprintf(&buf[status], "\n");
 892         spin_unlock_irq(&mcbsp->lock);
 893
 894         return status;
 895 }
 896
 897 static ssize_t st_taps_store(struct device *dev,
 898                              struct device_attribute *attr,
 899                              const char *buf, size_t size)
 900 {
 901         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
 902         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 903         int val, tmp, status, i = 0;
 904
 905         spin_lock_irq(&mcbsp->lock);
 906         memset(st_data->taps, 0, sizeof(st_data->taps));
 907         st_data->nr_taps = 0;
 908
 909         do {
 910                 status = sscanf(buf, "%d%n", &val, &tmp);
 911                 if (status < 0 || status == 0) {
 912                         size = -EINVAL;
 913                         goto out;
 914                 }
 915                 if (val < -32768 || val > 32767) {
 916                         size = -EINVAL;
 917                         goto out;
 918                 }
 919                 st_data->taps[i++] = val;
 920                 buf += tmp;
 921                 if (*buf != ',')
 922                         break;
 923                 buf++;
 924         } while (1);
 925
 926         st_data->nr_taps = i;
 927
 928 out:
 929         spin_unlock_irq(&mcbsp->lock);
 930
 931         return size;
 932 }
 933
 934 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
 935
 936 static const struct attribute *sidetone_attrs[] = {
 937         &dev_attr_st_taps.attr,
 938         NULL,
 939 };
 940
 941 static const struct attribute_group sidetone_attr_group = {
 942         .attrs = (struct attribute **)sidetone_attrs,
 943 };
 944
 945 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
 946                                  struct resource *res)
 947 {
 948         struct omap_mcbsp_st_data *st_data;
 949         int err;
 950
 951         st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
 952         if (!st_data)
 953                 return -ENOMEM;
 954
 955         st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
 956                                            resource_size(res));
 957         if (!st_data->io_base_st)
 958                 return -ENOMEM;
 959
 960         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
 961         if (err)
 962                 return err;
 963
 964         mcbsp->st_data = st_data;
 965         return 0;
 966 }
 967
 968 /*
 969  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 970  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 971  */
 972 int __devinit omap_mcbsp_init(struct platform_device *pdev)
 973 {
 974         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 975         struct resource *res;
 976         int ret = 0;
 977
 978         spin_lock_init(&mcbsp->lock);
 979         mcbsp->free = true;
 980
 981         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
 982         if (!res) {
 983                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 984                 if (!res) {
 985                         dev_err(mcbsp->dev, "invalid memory resource\n");
 986                         return -ENOMEM;
 987                 }
 988         }
 989         if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
 990                                      dev_name(&pdev->dev))) {
 991                 dev_err(mcbsp->dev, "memory region already claimed\n");
 992                 return -ENODEV;
 993         }
 994
 995         mcbsp->phys_base = res->start;
 996         mcbsp->reg_cache_size = resource_size(res);
 997         mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
 998                                       resource_size(res));
 999         if (!mcbsp->io_base)
1000                 return -ENOMEM;
1001
1002         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1003         if (!res)
1004                 mcbsp->phys_dma_base = mcbsp->phys_base;
1005         else
1006                 mcbsp->phys_dma_base = res->start;
1007
1008         /*
1009          * OMAP1, 2 uses two interrupt lines: TX, RX
1010          * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1011          * OMAP4 and newer SoC only have the combined IRQ line.
1012          * Use the combined IRQ if available since it gives better debugging
1013          * possibilities.
1014          */
1015         mcbsp->irq = platform_get_irq_byname(pdev, "common");
1016         if (mcbsp->irq == -ENXIO) {
1017                 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1018
1019                 if (mcbsp->tx_irq == -ENXIO) {
1020                         mcbsp->irq = platform_get_irq(pdev, 0);
1021                         mcbsp->tx_irq = 0;
1022                 } else {
1023                         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1024                         mcbsp->irq = 0;
1025                 }
1026         }
1027
1028         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1029         if (!res) {
1030                 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1031                 return -ENODEV;
1032         }
1033         /* RX DMA request number, and port address configuration */
1034         mcbsp->dma_data[1].name = "Audio Capture";
1035         mcbsp->dma_data[1].dma_req = res->start;
1036         mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1037
1038         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1039         if (!res) {
1040                 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1041                 return -ENODEV;
1042         }
1043         /* TX DMA request number, and port address configuration */
1044         mcbsp->dma_data[0].name = "Audio Playback";
1045         mcbsp->dma_data[0].dma_req = res->start;
1046         mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1047
1048         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1049         if (IS_ERR(mcbsp->fclk)) {
1050                 ret = PTR_ERR(mcbsp->fclk);
1051                 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1052                 return ret;
1053         }
1054
1055         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1056         if (mcbsp->pdata->buffer_size) {
1057                 /*
1058                  * Initially configure the maximum thresholds to a safe value.
1059                  * The McBSP FIFO usage with these values should not go under
1060                  * 16 locations.
1061                  * If the whole FIFO without safety buffer is used, than there
1062                  * is a possibility that the DMA will be not able to push the
1063                  * new data on time, causing channel shifts in runtime.
1064                  */
1065                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1066                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1067
1068                 ret = sysfs_create_group(&mcbsp->dev->kobj,
1069                                          &additional_attr_group);
1070                 if (ret) {
1071                         dev_err(mcbsp->dev,
1072                                 "Unable to create additional controls\n");
1073                         goto err_thres;
1074                 }
1075         } else {
1076                 mcbsp->max_tx_thres = -EINVAL;
1077                 mcbsp->max_rx_thres = -EINVAL;
1078         }
1079
1080         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1081         if (res) {
1082                 ret = omap_st_add(mcbsp, res);
1083                 if (ret) {
1084                         dev_err(mcbsp->dev,
1085                                 "Unable to create sidetone controls\n");
1086                         goto err_st;
1087                 }
1088         }
1089
1090         return 0;
1091
1092 err_st:
1093         if (mcbsp->pdata->buffer_size)
1094                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1095 err_thres:
1096         clk_put(mcbsp->fclk);
1097         return ret;
1098 }
1099
1100 void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
1101 {
1102         if (mcbsp->pdata->buffer_size)
1103                 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1104
1105         if (mcbsp->st_data)
1106                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1107 }