2 * sound/soc/omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Multichannel mode not supported.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
28 #include <plat/mcbsp.h>
32 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
34 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
36 if (mcbsp->pdata->reg_size == 2) {
37 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
38 __raw_writew((u16)val, addr);
40 ((u32 *)mcbsp->reg_cache)[reg] = val;
41 __raw_writel(val, addr);
45 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
47 void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
49 if (mcbsp->pdata->reg_size == 2) {
50 return !from_cache ? __raw_readw(addr) :
51 ((u16 *)mcbsp->reg_cache)[reg];
53 return !from_cache ? __raw_readl(addr) :
54 ((u32 *)mcbsp->reg_cache)[reg];
58 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
60 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
63 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
65 return __raw_readl(mcbsp->st_data->io_base_st + reg);
68 #define MCBSP_READ(mcbsp, reg) \
69 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
70 #define MCBSP_WRITE(mcbsp, reg, val) \
71 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
72 #define MCBSP_READ_CACHE(mcbsp, reg) \
73 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
75 #define MCBSP_ST_READ(mcbsp, reg) \
76 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
77 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
78 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
80 static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
82 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
83 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
84 MCBSP_READ(mcbsp, DRR2));
85 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
86 MCBSP_READ(mcbsp, DRR1));
87 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
88 MCBSP_READ(mcbsp, DXR2));
89 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
90 MCBSP_READ(mcbsp, DXR1));
91 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
92 MCBSP_READ(mcbsp, SPCR2));
93 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
94 MCBSP_READ(mcbsp, SPCR1));
95 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
96 MCBSP_READ(mcbsp, RCR2));
97 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
98 MCBSP_READ(mcbsp, RCR1));
99 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
100 MCBSP_READ(mcbsp, XCR2));
101 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
102 MCBSP_READ(mcbsp, XCR1));
103 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
104 MCBSP_READ(mcbsp, SRGR2));
105 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
106 MCBSP_READ(mcbsp, SRGR1));
107 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
108 MCBSP_READ(mcbsp, PCR0));
109 dev_dbg(mcbsp->dev, "***********************\n");
112 static irqreturn_t omap_mcbsp_irq_handler(int irq, void *dev_id)
114 struct omap_mcbsp *mcbsp = dev_id;
117 irqst = MCBSP_READ(mcbsp, IRQST);
118 dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
120 if (irqst & RSYNCERREN)
121 dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
123 dev_dbg(mcbsp->dev, "RX Frame Sync\n");
125 dev_dbg(mcbsp->dev, "RX End Of Frame\n");
127 dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
128 if (irqst & RUNDFLEN)
129 dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
131 dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
133 if (irqst & XSYNCERREN)
134 dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
136 dev_dbg(mcbsp->dev, "TX Frame Sync\n");
138 dev_dbg(mcbsp->dev, "TX End Of Frame\n");
140 dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
141 if (irqst & XUNDFLEN)
142 dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
144 dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
145 if (irqst & XEMPTYEOFEN)
146 dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
148 MCBSP_WRITE(mcbsp, IRQST, irqst);
153 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
155 struct omap_mcbsp *mcbsp_tx = dev_id;
158 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
159 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
161 if (irqst_spcr2 & XSYNC_ERR) {
162 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
164 /* Writing zero to XSYNC_ERR clears the IRQ */
165 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
171 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
173 struct omap_mcbsp *mcbsp_rx = dev_id;
176 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
177 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
179 if (irqst_spcr1 & RSYNC_ERR) {
180 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
182 /* Writing zero to RSYNC_ERR clears the IRQ */
183 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
190 * omap_mcbsp_config simply write a config to the
192 * You either call this function or set the McBSP registers
193 * by yourself before calling omap_mcbsp_start().
195 void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
196 const struct omap_mcbsp_reg_cfg *config)
198 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
199 mcbsp->id, mcbsp->phys_base);
201 /* We write the given config */
202 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
203 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
204 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
205 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
206 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
207 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
208 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
209 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
210 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
211 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
212 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
213 if (mcbsp->pdata->has_ccr) {
214 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
215 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
217 /* Enable wakeup behavior */
218 if (mcbsp->pdata->has_wakeup)
219 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
221 /* Enable TX/RX sync error interrupts by default */
223 MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN);
227 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
229 * @stream - indicates the direction of data flow (rx or tx)
231 * Returns the address of mcbsp data transmit register or data receive register
232 * to be used by DMA for transferring/receiving data based on the value of
233 * @stream for the requested mcbsp given by @id
235 static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
240 if (mcbsp->pdata->reg_size == 2) {
242 data_reg = OMAP_MCBSP_REG_DRR1;
244 data_reg = OMAP_MCBSP_REG_DXR1;
247 data_reg = OMAP_MCBSP_REG_DRR;
249 data_reg = OMAP_MCBSP_REG_DXR;
252 return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
255 static void omap_st_on(struct omap_mcbsp *mcbsp)
259 if (mcbsp->pdata->enable_st_clock)
260 mcbsp->pdata->enable_st_clock(mcbsp->id, 1);
262 /* Enable McBSP Sidetone */
263 w = MCBSP_READ(mcbsp, SSELCR);
264 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
266 /* Enable Sidetone from Sidetone Core */
267 w = MCBSP_ST_READ(mcbsp, SSELCR);
268 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
271 static void omap_st_off(struct omap_mcbsp *mcbsp)
275 w = MCBSP_ST_READ(mcbsp, SSELCR);
276 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
278 w = MCBSP_READ(mcbsp, SSELCR);
279 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
281 if (mcbsp->pdata->enable_st_clock)
282 mcbsp->pdata->enable_st_clock(mcbsp->id, 0);
285 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
289 val = MCBSP_ST_READ(mcbsp, SSELCR);
291 if (val & ST_COEFFWREN)
292 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
294 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
296 for (i = 0; i < 128; i++)
297 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
301 val = MCBSP_ST_READ(mcbsp, SSELCR);
302 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
303 val = MCBSP_ST_READ(mcbsp, SSELCR);
305 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
308 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
311 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
314 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
316 w = MCBSP_ST_READ(mcbsp, SSELCR);
318 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
319 ST_CH1GAIN(st_data->ch1gain));
322 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain)
324 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
330 spin_lock_irq(&mcbsp->lock);
332 st_data->ch0gain = chgain;
333 else if (channel == 1)
334 st_data->ch1gain = chgain;
338 if (st_data->enabled)
339 omap_st_chgain(mcbsp);
340 spin_unlock_irq(&mcbsp->lock);
345 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain)
347 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
353 spin_lock_irq(&mcbsp->lock);
355 *chgain = st_data->ch0gain;
356 else if (channel == 1)
357 *chgain = st_data->ch1gain;
360 spin_unlock_irq(&mcbsp->lock);
365 static int omap_st_start(struct omap_mcbsp *mcbsp)
367 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
369 if (st_data->enabled && !st_data->running) {
370 omap_st_fir_write(mcbsp, st_data->taps);
371 omap_st_chgain(mcbsp);
375 st_data->running = 1;
382 int omap_st_enable(struct omap_mcbsp *mcbsp)
384 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
389 spin_lock_irq(&mcbsp->lock);
390 st_data->enabled = 1;
391 omap_st_start(mcbsp);
392 spin_unlock_irq(&mcbsp->lock);
397 static int omap_st_stop(struct omap_mcbsp *mcbsp)
399 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
401 if (st_data->running) {
404 st_data->running = 0;
411 int omap_st_disable(struct omap_mcbsp *mcbsp)
413 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
419 spin_lock_irq(&mcbsp->lock);
421 st_data->enabled = 0;
422 spin_unlock_irq(&mcbsp->lock);
427 int omap_st_is_enabled(struct omap_mcbsp *mcbsp)
429 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
434 return st_data->enabled;
438 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
439 * The threshold parameter is 1 based, and it is converted (threshold - 1)
440 * for the THRSH2 register.
442 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
444 if (mcbsp->pdata->buffer_size == 0)
447 if (threshold && threshold <= mcbsp->max_tx_thres)
448 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
452 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
453 * The threshold parameter is 1 based, and it is converted (threshold - 1)
454 * for the THRSH1 register.
456 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
458 if (mcbsp->pdata->buffer_size == 0)
461 if (threshold && threshold <= mcbsp->max_rx_thres)
462 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
466 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
468 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
472 if (mcbsp->pdata->buffer_size == 0)
475 /* Returns the number of free locations in the buffer */
476 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
478 /* Number of slots are different in McBSP ports */
479 return mcbsp->pdata->buffer_size - buffstat;
483 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
484 * to reach the threshold value (when the DMA will be triggered to read it)
486 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
488 u16 buffstat, threshold;
490 if (mcbsp->pdata->buffer_size == 0)
493 /* Returns the number of used locations in the buffer */
494 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
496 threshold = MCBSP_READ(mcbsp, THRSH1);
498 /* Return the number of location till we reach the threshold limit */
499 if (threshold <= buffstat)
502 return threshold - buffstat;
505 int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
510 reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
515 spin_lock(&mcbsp->lock);
517 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
524 mcbsp->reg_cache = reg_cache;
525 spin_unlock(&mcbsp->lock);
527 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
528 mcbsp->pdata->ops->request(mcbsp->id - 1);
531 * Make sure that transmitter, receiver and sample-rate generator are
532 * not running before activating IRQs.
534 MCBSP_WRITE(mcbsp, SPCR1, 0);
535 MCBSP_WRITE(mcbsp, SPCR2, 0);
538 err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
539 "McBSP", (void *)mcbsp);
541 dev_err(mcbsp->dev, "Unable to request IRQ\n");
542 goto err_clk_disable;
545 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
546 "McBSP TX", (void *)mcbsp);
548 dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
549 goto err_clk_disable;
552 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
553 "McBSP RX", (void *)mcbsp);
555 dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
562 free_irq(mcbsp->tx_irq, (void *)mcbsp);
564 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
565 mcbsp->pdata->ops->free(mcbsp->id - 1);
567 /* Disable wakeup behavior */
568 if (mcbsp->pdata->has_wakeup)
569 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
571 spin_lock(&mcbsp->lock);
573 mcbsp->reg_cache = NULL;
575 spin_unlock(&mcbsp->lock);
581 void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
585 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
586 mcbsp->pdata->ops->free(mcbsp->id - 1);
588 /* Disable wakeup behavior */
589 if (mcbsp->pdata->has_wakeup)
590 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
592 /* Disable interrupt requests */
594 MCBSP_WRITE(mcbsp, IRQEN, 0);
597 free_irq(mcbsp->irq, (void *)mcbsp);
599 free_irq(mcbsp->rx_irq, (void *)mcbsp);
600 free_irq(mcbsp->tx_irq, (void *)mcbsp);
603 reg_cache = mcbsp->reg_cache;
606 * Select CLKS source from internal source unconditionally before
607 * marking the McBSP port as free.
608 * If the external clock source via MCBSP_CLKS pin has been selected the
609 * system will refuse to enter idle if the CLKS pin source is not reset
610 * back to internal source.
612 if (!cpu_class_is_omap1())
613 omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
615 spin_lock(&mcbsp->lock);
617 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
620 mcbsp->reg_cache = NULL;
621 spin_unlock(&mcbsp->lock);
628 * Here we start the McBSP, by enabling transmitter, receiver or both.
629 * If no transmitter or receiver is active prior calling, then sample-rate
630 * generator and frame sync are started.
632 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx)
638 omap_st_start(mcbsp);
640 /* Only enable SRG, if McBSP is master */
641 w = MCBSP_READ_CACHE(mcbsp, PCR0);
642 if (w & (FSXM | FSRM | CLKXM | CLKRM))
643 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
644 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
647 /* Start the sample generator */
648 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
649 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
652 /* Enable transmitter and receiver */
654 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
655 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
658 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
659 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
662 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
663 * REVISIT: 100us may give enough time for two CLKSRG, however
664 * due to some unknown PM related, clock gating etc. reason it
670 /* Start frame sync */
671 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
672 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
675 if (mcbsp->pdata->has_ccr) {
676 /* Release the transmitter and receiver */
677 w = MCBSP_READ_CACHE(mcbsp, XCCR);
678 w &= ~(tx ? XDISABLE : 0);
679 MCBSP_WRITE(mcbsp, XCCR, w);
680 w = MCBSP_READ_CACHE(mcbsp, RCCR);
681 w &= ~(rx ? RDISABLE : 0);
682 MCBSP_WRITE(mcbsp, RCCR, w);
685 /* Dump McBSP Regs */
686 omap_mcbsp_dump_reg(mcbsp);
689 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx)
694 /* Reset transmitter */
696 if (mcbsp->pdata->has_ccr) {
697 w = MCBSP_READ_CACHE(mcbsp, XCCR);
698 w |= (tx ? XDISABLE : 0);
699 MCBSP_WRITE(mcbsp, XCCR, w);
701 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
702 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
706 if (mcbsp->pdata->has_ccr) {
707 w = MCBSP_READ_CACHE(mcbsp, RCCR);
708 w |= (rx ? RDISABLE : 0);
709 MCBSP_WRITE(mcbsp, RCCR, w);
711 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
712 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
714 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
715 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
718 /* Reset the sample rate generator */
719 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
720 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
727 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
731 if (fck_src_id == MCBSP_CLKS_PAD_SRC)
733 else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
738 if (mcbsp->pdata->set_clk_src)
739 return mcbsp->pdata->set_clk_src(mcbsp->dev, mcbsp->fclk, src);
744 int omap_mcbsp_6pin_src_mux(struct omap_mcbsp *mcbsp, u8 mux)
746 const char *signal, *src;
748 if (!mcbsp->pdata->mux_signal)
772 return mcbsp->pdata->mux_signal(mcbsp->dev, signal, src);
775 #define max_thres(m) (mcbsp->pdata->buffer_size)
776 #define valid_threshold(m, val) ((val) <= max_thres(m))
777 #define THRESHOLD_PROP_BUILDER(prop) \
778 static ssize_t prop##_show(struct device *dev, \
779 struct device_attribute *attr, char *buf) \
781 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
783 return sprintf(buf, "%u\n", mcbsp->prop); \
786 static ssize_t prop##_store(struct device *dev, \
787 struct device_attribute *attr, \
788 const char *buf, size_t size) \
790 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
794 status = strict_strtoul(buf, 0, &val); \
798 if (!valid_threshold(mcbsp, val)) \
805 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
807 THRESHOLD_PROP_BUILDER(max_tx_thres);
808 THRESHOLD_PROP_BUILDER(max_rx_thres);
810 static const char *dma_op_modes[] = {
811 "element", "threshold",
814 static ssize_t dma_op_mode_show(struct device *dev,
815 struct device_attribute *attr, char *buf)
817 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
818 int dma_op_mode, i = 0;
820 const char * const *s;
822 dma_op_mode = mcbsp->dma_op_mode;
824 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
825 if (dma_op_mode == i)
826 len += sprintf(buf + len, "[%s] ", *s);
828 len += sprintf(buf + len, "%s ", *s);
830 len += sprintf(buf + len, "\n");
835 static ssize_t dma_op_mode_store(struct device *dev,
836 struct device_attribute *attr,
837 const char *buf, size_t size)
839 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
840 const char * const *s;
843 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
844 if (sysfs_streq(buf, *s))
847 if (i == ARRAY_SIZE(dma_op_modes))
850 spin_lock_irq(&mcbsp->lock);
855 mcbsp->dma_op_mode = i;
858 spin_unlock_irq(&mcbsp->lock);
863 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
865 static const struct attribute *additional_attrs[] = {
866 &dev_attr_max_tx_thres.attr,
867 &dev_attr_max_rx_thres.attr,
868 &dev_attr_dma_op_mode.attr,
872 static const struct attribute_group additional_attr_group = {
873 .attrs = (struct attribute **)additional_attrs,
876 static ssize_t st_taps_show(struct device *dev,
877 struct device_attribute *attr, char *buf)
879 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
880 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
884 spin_lock_irq(&mcbsp->lock);
885 for (i = 0; i < st_data->nr_taps; i++)
886 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
889 status += sprintf(&buf[status], "\n");
890 spin_unlock_irq(&mcbsp->lock);
895 static ssize_t st_taps_store(struct device *dev,
896 struct device_attribute *attr,
897 const char *buf, size_t size)
899 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
900 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
901 int val, tmp, status, i = 0;
903 spin_lock_irq(&mcbsp->lock);
904 memset(st_data->taps, 0, sizeof(st_data->taps));
905 st_data->nr_taps = 0;
908 status = sscanf(buf, "%d%n", &val, &tmp);
909 if (status < 0 || status == 0) {
913 if (val < -32768 || val > 32767) {
917 st_data->taps[i++] = val;
924 st_data->nr_taps = i;
927 spin_unlock_irq(&mcbsp->lock);
932 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
934 static const struct attribute *sidetone_attrs[] = {
935 &dev_attr_st_taps.attr,
939 static const struct attribute_group sidetone_attr_group = {
940 .attrs = (struct attribute **)sidetone_attrs,
943 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp,
944 struct resource *res)
946 struct omap_mcbsp_st_data *st_data;
949 st_data = devm_kzalloc(mcbsp->dev, sizeof(*mcbsp->st_data), GFP_KERNEL);
953 st_data->io_base_st = devm_ioremap(mcbsp->dev, res->start,
955 if (!st_data->io_base_st)
958 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
962 mcbsp->st_data = st_data;
967 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
968 * 730 has only 2 McBSP, and both of them are MPU peripherals.
970 int __devinit omap_mcbsp_init(struct platform_device *pdev)
972 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
973 struct resource *res;
976 spin_lock_init(&mcbsp->lock);
979 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
981 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
983 dev_err(mcbsp->dev, "invalid memory resource\n");
987 if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
988 dev_name(&pdev->dev))) {
989 dev_err(mcbsp->dev, "memory region already claimed\n");
993 mcbsp->phys_base = res->start;
994 mcbsp->reg_cache_size = resource_size(res);
995 mcbsp->io_base = devm_ioremap(&pdev->dev, res->start,
1000 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1002 mcbsp->phys_dma_base = mcbsp->phys_base;
1004 mcbsp->phys_dma_base = res->start;
1007 * OMAP1, 2 uses two interrupt lines: TX, RX
1008 * OMAP2430, OMAP3 SoC have combined IRQ line as well.
1009 * OMAP4 and newer SoC only have the combined IRQ line.
1010 * Use the combined IRQ if available since it gives better debugging
1013 mcbsp->irq = platform_get_irq_byname(pdev, "common");
1014 if (mcbsp->irq == -ENXIO) {
1015 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1017 if (mcbsp->tx_irq == -ENXIO) {
1018 mcbsp->irq = platform_get_irq(pdev, 0);
1021 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1026 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1028 dev_err(&pdev->dev, "invalid rx DMA channel\n");
1031 /* RX DMA request number, and port address configuration */
1032 mcbsp->dma_data[1].name = "Audio Capture";
1033 mcbsp->dma_data[1].dma_req = res->start;
1034 mcbsp->dma_data[1].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 1);
1036 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1038 dev_err(&pdev->dev, "invalid tx DMA channel\n");
1041 /* TX DMA request number, and port address configuration */
1042 mcbsp->dma_data[0].name = "Audio Playback";
1043 mcbsp->dma_data[0].dma_req = res->start;
1044 mcbsp->dma_data[0].port_addr = omap_mcbsp_dma_reg_params(mcbsp, 0);
1046 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1047 if (IS_ERR(mcbsp->fclk)) {
1048 ret = PTR_ERR(mcbsp->fclk);
1049 dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
1053 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1054 if (mcbsp->pdata->buffer_size) {
1056 * Initially configure the maximum thresholds to a safe value.
1057 * The McBSP FIFO usage with these values should not go under
1059 * If the whole FIFO without safety buffer is used, than there
1060 * is a possibility that the DMA will be not able to push the
1061 * new data on time, causing channel shifts in runtime.
1063 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1064 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1066 ret = sysfs_create_group(&mcbsp->dev->kobj,
1067 &additional_attr_group);
1070 "Unable to create additional controls\n");
1074 mcbsp->max_tx_thres = -EINVAL;
1075 mcbsp->max_rx_thres = -EINVAL;
1078 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1080 ret = omap_st_add(mcbsp, res);
1083 "Unable to create sidetone controls\n");
1091 if (mcbsp->pdata->buffer_size)
1092 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1094 clk_put(mcbsp->fclk);
1098 void __devexit omap_mcbsp_sysfs_remove(struct omap_mcbsp *mcbsp)
1100 if (mcbsp->pdata->buffer_size)
1101 sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
1104 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);