2 * mcpdm.c -- McPDM interface driver
4 * Author: Jorge Eduardo Candelaria <x0107209@ti.com>
5 * Copyright (C) 2009 - Texas Instruments, Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/device.h>
26 #include <linux/platform_device.h>
27 #include <linux/wait.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
32 #include <linux/delay.h>
34 #include <linux/irq.h>
38 static struct omap_mcpdm *mcpdm;
40 static inline void omap_mcpdm_write(u16 reg, u32 val)
42 __raw_writel(val, mcpdm->io_base + reg);
45 static inline int omap_mcpdm_read(u16 reg)
47 return __raw_readl(mcpdm->io_base + reg);
50 static void omap_mcpdm_reg_dump(void)
52 dev_dbg(mcpdm->dev, "***********************\n");
53 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
54 omap_mcpdm_read(MCPDM_IRQSTATUS_RAW));
55 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
56 omap_mcpdm_read(MCPDM_IRQSTATUS));
57 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
58 omap_mcpdm_read(MCPDM_IRQENABLE_SET));
59 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
60 omap_mcpdm_read(MCPDM_IRQENABLE_CLR));
61 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
62 omap_mcpdm_read(MCPDM_IRQWAKE_EN));
63 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
64 omap_mcpdm_read(MCPDM_DMAENABLE_SET));
65 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
66 omap_mcpdm_read(MCPDM_DMAENABLE_CLR));
67 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
68 omap_mcpdm_read(MCPDM_DMAWAKEEN));
69 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
70 omap_mcpdm_read(MCPDM_CTRL));
71 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
72 omap_mcpdm_read(MCPDM_DN_DATA));
73 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
74 omap_mcpdm_read(MCPDM_UP_DATA));
75 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
76 omap_mcpdm_read(MCPDM_FIFO_CTRL_DN));
77 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
78 omap_mcpdm_read(MCPDM_FIFO_CTRL_UP));
79 dev_dbg(mcpdm->dev, "DN_OFFSET: 0x%04x\n",
80 omap_mcpdm_read(MCPDM_DN_OFFSET));
81 dev_dbg(mcpdm->dev, "***********************\n");
85 * Takes the McPDM module in and out of reset state.
86 * Uplink and downlink can be reset individually.
88 static void omap_mcpdm_reset_capture(int reset)
90 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
97 omap_mcpdm_write(MCPDM_CTRL, ctrl);
100 static void omap_mcpdm_reset_playback(int reset)
102 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
109 omap_mcpdm_write(MCPDM_CTRL, ctrl);
113 * Enables the transfer through the PDM interface to/from the Phoenix
114 * codec by enabling the corresponding UP or DN channels.
116 void omap_mcpdm_start(int stream)
118 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
121 ctrl |= mcpdm->up_channels;
123 ctrl |= mcpdm->dn_channels;
125 omap_mcpdm_write(MCPDM_CTRL, ctrl);
129 * Disables the transfer through the PDM interface to/from the Phoenix
130 * codec by disabling the corresponding UP or DN channels.
132 void omap_mcpdm_stop(int stream)
134 int ctrl = omap_mcpdm_read(MCPDM_CTRL);
137 ctrl &= ~mcpdm->up_channels;
139 ctrl &= ~mcpdm->dn_channels;
141 omap_mcpdm_write(MCPDM_CTRL, ctrl);
145 * Configures McPDM uplink for audio recording.
146 * This function should be called before omap_mcpdm_start.
148 int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink)
156 mcpdm->uplink = uplink;
158 /* Enable irq request generation */
159 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
160 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
162 /* Configure uplink threshold */
163 if (uplink->threshold > UP_THRES_MAX)
164 uplink->threshold = UP_THRES_MAX;
166 omap_mcpdm_write(MCPDM_FIFO_CTRL_UP, uplink->threshold);
168 /* Configure DMA controller */
169 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_UP_ENABLE);
171 /* Set pdm out format */
172 ctrl = omap_mcpdm_read(MCPDM_CTRL);
173 ctrl &= ~PDMOUTFORMAT;
174 ctrl |= uplink->format & PDMOUTFORMAT;
176 /* Uplink channels */
177 mcpdm->up_channels = uplink->channels & (PDM_UP_MASK | PDM_STATUS_MASK);
179 omap_mcpdm_write(MCPDM_CTRL, ctrl);
185 * Configures McPDM downlink for audio playback.
186 * This function should be called before omap_mcpdm_start.
188 int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink)
196 mcpdm->downlink = downlink;
198 /* Enable irq request generation */
199 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
200 omap_mcpdm_write(MCPDM_IRQENABLE_SET, irq_mask);
202 /* Configure uplink threshold */
203 if (downlink->threshold > DN_THRES_MAX)
204 downlink->threshold = DN_THRES_MAX;
206 omap_mcpdm_write(MCPDM_FIFO_CTRL_DN, downlink->threshold);
208 /* Enable DMA request generation */
209 omap_mcpdm_write(MCPDM_DMAENABLE_SET, DMA_DN_ENABLE);
211 /* Set pdm out format */
212 ctrl = omap_mcpdm_read(MCPDM_CTRL);
213 ctrl &= ~PDMOUTFORMAT;
214 ctrl |= downlink->format & PDMOUTFORMAT;
216 /* Downlink channels */
217 mcpdm->dn_channels = downlink->channels & (PDM_DN_MASK | PDM_CMD_MASK);
219 omap_mcpdm_write(MCPDM_CTRL, ctrl);
225 * Cleans McPDM uplink configuration.
226 * This function should be called when the stream is closed.
228 int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink)
235 /* Disable irq request generation */
236 irq_mask |= uplink->irq_mask & MCPDM_UPLINK_IRQ_MASK;
237 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
239 /* Disable DMA request generation */
240 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_UP_ENABLE);
242 /* Clear Downlink channels */
243 mcpdm->up_channels = 0;
245 mcpdm->uplink = NULL;
251 * Cleans McPDM downlink configuration.
252 * This function should be called when the stream is closed.
254 int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink)
261 /* Disable irq request generation */
262 irq_mask |= downlink->irq_mask & MCPDM_DOWNLINK_IRQ_MASK;
263 omap_mcpdm_write(MCPDM_IRQENABLE_CLR, irq_mask);
265 /* Disable DMA request generation */
266 omap_mcpdm_write(MCPDM_DMAENABLE_CLR, DMA_DN_ENABLE);
268 /* clear Downlink channels */
269 mcpdm->dn_channels = 0;
271 mcpdm->downlink = NULL;
276 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
278 struct omap_mcpdm *mcpdm_irq = dev_id;
281 irq_status = omap_mcpdm_read(MCPDM_IRQSTATUS);
283 /* Acknowledge irq event */
284 omap_mcpdm_write(MCPDM_IRQSTATUS, irq_status);
286 if (irq & MCPDM_DN_IRQ_FULL) {
287 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
288 omap_mcpdm_reset_playback(1);
289 omap_mcpdm_playback_open(mcpdm_irq->downlink);
290 omap_mcpdm_reset_playback(0);
293 if (irq & MCPDM_DN_IRQ_EMPTY) {
294 dev_err(mcpdm_irq->dev, "DN FIFO error %x\n", irq_status);
295 omap_mcpdm_reset_playback(1);
296 omap_mcpdm_playback_open(mcpdm_irq->downlink);
297 omap_mcpdm_reset_playback(0);
300 if (irq & MCPDM_DN_IRQ) {
301 dev_dbg(mcpdm_irq->dev, "DN write request\n");
304 if (irq & MCPDM_UP_IRQ_FULL) {
305 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
306 omap_mcpdm_reset_capture(1);
307 omap_mcpdm_capture_open(mcpdm_irq->uplink);
308 omap_mcpdm_reset_capture(0);
311 if (irq & MCPDM_UP_IRQ_EMPTY) {
312 dev_err(mcpdm_irq->dev, "UP FIFO error %x\n", irq_status);
313 omap_mcpdm_reset_capture(1);
314 omap_mcpdm_capture_open(mcpdm_irq->uplink);
315 omap_mcpdm_reset_capture(0);
318 if (irq & MCPDM_UP_IRQ) {
319 dev_dbg(mcpdm_irq->dev, "UP write request\n");
325 int omap_mcpdm_request(void)
329 clk_enable(mcpdm->clk);
331 spin_lock(&mcpdm->lock);
334 dev_err(mcpdm->dev, "McPDM interface is in use\n");
335 spin_unlock(&mcpdm->lock);
341 spin_unlock(&mcpdm->lock);
343 /* Disable lines while request is ongoing */
344 omap_mcpdm_write(MCPDM_CTRL, 0x00);
346 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
347 0, "McPDM", (void *)mcpdm);
349 dev_err(mcpdm->dev, "Request for McPDM IRQ failed\n");
356 clk_disable(mcpdm->clk);
360 void omap_mcpdm_free(void)
362 spin_lock(&mcpdm->lock);
364 dev_err(mcpdm->dev, "McPDM interface is already free\n");
365 spin_unlock(&mcpdm->lock);
369 spin_unlock(&mcpdm->lock);
371 clk_disable(mcpdm->clk);
373 free_irq(mcpdm->irq, (void *)mcpdm);
376 /* Enable/disable DC offset cancelation for the analog
377 * headset path (PDM channels 1 and 2).
379 int omap_mcpdm_set_offset(int offset1, int offset2)
383 if ((offset1 > DN_OFST_MAX) || (offset2 > DN_OFST_MAX))
386 offset = (offset1 << DN_OFST_RX1) | (offset2 << DN_OFST_RX2);
388 /* offset cancellation for channel 1 */
390 offset |= DN_OFST_RX1_EN;
392 offset &= ~DN_OFST_RX1_EN;
394 /* offset cancellation for channel 2 */
396 offset |= DN_OFST_RX2_EN;
398 offset &= ~DN_OFST_RX2_EN;
400 omap_mcpdm_write(MCPDM_DN_OFFSET, offset);
405 int __devinit omap_mcpdm_probe(struct platform_device *pdev)
407 struct resource *res;
410 mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
416 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
418 dev_err(&pdev->dev, "no resource\n");
422 spin_lock_init(&mcpdm->lock);
424 mcpdm->io_base = ioremap(res->start, resource_size(res));
425 if (!mcpdm->io_base) {
430 mcpdm->irq = platform_get_irq(pdev, 0);
432 mcpdm->clk = clk_get(&pdev->dev, "pdm_ck");
433 if (IS_ERR(mcpdm->clk)) {
434 ret = PTR_ERR(mcpdm->clk);
435 dev_err(&pdev->dev, "unable to get pdm_ck: %d\n", ret);
439 mcpdm->dev = &pdev->dev;
440 platform_set_drvdata(pdev, mcpdm);
445 iounmap(mcpdm->io_base);
452 int __devexit omap_mcpdm_remove(struct platform_device *pdev)
454 struct omap_mcpdm *mcpdm_ptr = platform_get_drvdata(pdev);
456 platform_set_drvdata(pdev, NULL);
458 clk_put(mcpdm_ptr->clk);
460 iounmap(mcpdm_ptr->io_base);
462 mcpdm_ptr->clk = NULL;
464 mcpdm_ptr->dev = NULL;