sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <sound/core.h>
  32 #include <sound/pcm.h>
  33 #include <sound/pcm_params.h>
  34 #include <sound/initval.h>
  35 #include <sound/soc.h>
  36
  37 #include <plat/cpu.h>
  38 #include <linux/platform_data/asoc-ti-mcbsp.h>
  39 #include "mcbsp.h"
  40 #include "omap-mcbsp.h"
  41 #include "omap-pcm.h"
  42
  43 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  44
  45 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  46         xhandler_get, xhandler_put) \
  47 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  48         .info = omap_mcbsp_st_info_volsw, \
  49         .get = xhandler_get, .put = xhandler_put, \
  50         .private_value = (unsigned long) &(struct soc_mixer_control) \
  51         {.min = xmin, .max = xmax} }
  52
  53 enum {
  54         OMAP_MCBSP_WORD_8 = 0,
  55         OMAP_MCBSP_WORD_12,
  56         OMAP_MCBSP_WORD_16,
  57         OMAP_MCBSP_WORD_20,
  58         OMAP_MCBSP_WORD_24,
  59         OMAP_MCBSP_WORD_32,
  60 };
  61
  62 /*
  63  * Stream DMA parameters. DMA request line and port address are set runtime
  64  * since they are different between OMAP1 and later OMAPs
  65  */
  66 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  67 {
  68         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  69         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  70         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  71         struct omap_pcm_dma_data *dma_data;
  72         int words;
  73
  74         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  75
  76         /*
  77          * Configure McBSP threshold based on either:
  78          * packet_size, when the sDMA is in packet mode, or based on the
  79          * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  80          * for mono streams.
  81          */
  82         if (dma_data->packet_size)
  83                 words = dma_data->packet_size;
  84         else
  85                 words = 1;
  86
  87         /* Configure McBSP internal buffer usage */
  88         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  89                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  90         else
  91                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  92 }
  93
  94 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  95                                     struct snd_pcm_hw_rule *rule)
  96 {
  97         struct snd_interval *buffer_size = hw_param_interval(params,
  98                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  99         struct snd_interval *channels = hw_param_interval(params,
 100                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 101         struct omap_mcbsp *mcbsp = rule->private;
 102         struct snd_interval frames;
 103         int size;
 104
 105         snd_interval_any(&frames);
 106         size = mcbsp->pdata->buffer_size;
 107
 108         frames.min = size / channels->min;
 109         frames.integer = 1;
 110         return snd_interval_refine(buffer_size, &frames);
 111 }
 112
 113 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 114                                   struct snd_soc_dai *cpu_dai)
 115 {
 116         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 117         int err = 0;
 118
 119         if (!cpu_dai->active)
 120                 err = omap_mcbsp_request(mcbsp);
 121
 122         /*
 123          * OMAP3 McBSP FIFO is word structured.
 124          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 125          * McBSP1,3,4,5 has 128 word long buffer
 126          * This means that the size of the FIFO depends on the sample format.
 127          * For example on McBSP3:
 128          * 16bit samples: size is 128 * 2 = 256 bytes
 129          * 32bit samples: size is 128 * 4 = 512 bytes
 130          * It is simpler to place constraint for buffer and period based on
 131          * channels.
 132          * McBSP3 as example again (16 or 32 bit samples):
 133          * 1 channel (mono): size is 128 frames (128 words)
 134          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 135          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 136          */
 137         if (mcbsp->pdata->buffer_size) {
 138                 /*
 139                 * Rule for the buffer size. We should not allow
 140                 * smaller buffer than the FIFO size to avoid underruns.
 141                 * This applies only for the playback stream.
 142                 */
 143                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 144                         snd_pcm_hw_rule_add(substream->runtime, 0,
 145                                             SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 146                                             omap_mcbsp_hwrule_min_buffersize,
 147                                             mcbsp,
 148                                             SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 149
 150                 /* Make sure, that the period size is always even */
 151                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 152                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 153         }
 154
 155         snd_soc_dai_set_dma_data(cpu_dai, substream,
 156                                  &mcbsp->dma_data[substream->stream]);
 157
 158         return err;
 159 }
 160
 161 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 162                                     struct snd_soc_dai *cpu_dai)
 163 {
 164         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 165
 166         if (!cpu_dai->active) {
 167                 omap_mcbsp_free(mcbsp);
 168                 mcbsp->configured = 0;
 169         }
 170 }
 171
 172 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 173                                   struct snd_soc_dai *cpu_dai)
 174 {
 175         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 176         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 177
 178         switch (cmd) {
 179         case SNDRV_PCM_TRIGGER_START:
 180         case SNDRV_PCM_TRIGGER_RESUME:
 181         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 182                 mcbsp->active++;
 183                 omap_mcbsp_start(mcbsp, play, !play);
 184                 break;
 185
 186         case SNDRV_PCM_TRIGGER_STOP:
 187         case SNDRV_PCM_TRIGGER_SUSPEND:
 188         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 189                 omap_mcbsp_stop(mcbsp, play, !play);
 190                 mcbsp->active--;
 191                 break;
 192         default:
 193                 err = -EINVAL;
 194         }
 195
 196         return err;
 197 }
 198
 199 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 200                         struct snd_pcm_substream *substream,
 201                         struct snd_soc_dai *dai)
 202 {
 203         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 204         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 205         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 206         u16 fifo_use;
 207         snd_pcm_sframes_t delay;
 208
 209         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 210                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 211         else
 212                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 213
 214         /*
 215          * Divide the used locations with the channel count to get the
 216          * FIFO usage in samples (don't care about partial samples in the
 217          * buffer).
 218          */
 219         delay = fifo_use / substream->runtime->channels;
 220
 221         return delay;
 222 }
 223
 224 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 225                                     struct snd_pcm_hw_params *params,
 226                                     struct snd_soc_dai *cpu_dai)
 227 {
 228         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 229         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 230         struct omap_pcm_dma_data *dma_data;
 231         int wlen, channels, wpf;
 232         int pkt_size = 0;
 233         unsigned int format, div, framesize, master;
 234
 235         dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
 236         channels = params_channels(params);
 237
 238         switch (params_format(params)) {
 239         case SNDRV_PCM_FORMAT_S16_LE:
 240                 wlen = 16;
 241                 break;
 242         case SNDRV_PCM_FORMAT_S32_LE:
 243                 wlen = 32;
 244                 break;
 245         default:
 246                 return -EINVAL;
 247         }
 248         if (mcbsp->pdata->buffer_size) {
 249                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 250                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 251                         int period_words, max_thrsh;
 252                         int divider = 0;
 253
 254                         period_words = params_period_bytes(params) / (wlen / 8);
 255                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 256                                 max_thrsh = mcbsp->max_tx_thres;
 257                         else
 258                                 max_thrsh = mcbsp->max_rx_thres;
 259                         /*
 260                          * Use sDMA packet mode if McBSP is in threshold mode:
 261                          * If period words less than the FIFO size the packet
 262                          * size is set to the number of period words, otherwise
 263                          * Look for the biggest threshold value which divides
 264                          * the period size evenly.
 265                          */
 266                         divider = period_words / max_thrsh;
 267                         if (period_words % max_thrsh)
 268                                 divider++;
 269                         while (period_words % divider &&
 270                                 divider < period_words)
 271                                 divider++;
 272                         if (divider == period_words)
 273                                 return -EINVAL;
 274
 275                         pkt_size = period_words / divider;
 276                 } else if (channels > 1) {
 277                         /* Use packet mode for non mono streams */
 278                         pkt_size = channels;
 279                 }
 280         }
 281
 282         dma_data->packet_size = pkt_size;
 283
 284         if (mcbsp->configured) {
 285                 /* McBSP already configured by another stream */
 286                 return 0;
 287         }
 288
 289         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 290         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 291         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 292         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 293         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 294         wpf = channels;
 295         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 296                               format == SND_SOC_DAIFMT_LEFT_J)) {
 297                 /* Use dual-phase frames */
 298                 regs->rcr2      |= RPHASE;
 299                 regs->xcr2      |= XPHASE;
 300                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 301                 wpf--;
 302                 regs->rcr2      |= RFRLEN2(wpf - 1);
 303                 regs->xcr2      |= XFRLEN2(wpf - 1);
 304         }
 305
 306         regs->rcr1      |= RFRLEN1(wpf - 1);
 307         regs->xcr1      |= XFRLEN1(wpf - 1);
 308
 309         switch (params_format(params)) {
 310         case SNDRV_PCM_FORMAT_S16_LE:
 311                 /* Set word lengths */
 312                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 313                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 314                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 315                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 316                 break;
 317         case SNDRV_PCM_FORMAT_S32_LE:
 318                 /* Set word lengths */
 319                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 320                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 321                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 322                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 323                 break;
 324         default:
 325                 /* Unsupported PCM format */
 326                 return -EINVAL;
 327         }
 328
 329         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 330          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 331         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 332         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 333                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 334                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 335
 336                 if (framesize < wlen * channels) {
 337                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 338                                         "channels\n", __func__);
 339                         return -EINVAL;
 340                 }
 341         } else
 342                 framesize = wlen * channels;
 343
 344         /* Set FS period and length in terms of bit clock periods */
 345         regs->srgr2     &= ~FPER(0xfff);
 346         regs->srgr1     &= ~FWID(0xff);
 347         switch (format) {
 348         case SND_SOC_DAIFMT_I2S:
 349         case SND_SOC_DAIFMT_LEFT_J:
 350                 regs->srgr2     |= FPER(framesize - 1);
 351                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 352                 break;
 353         case SND_SOC_DAIFMT_DSP_A:
 354         case SND_SOC_DAIFMT_DSP_B:
 355                 regs->srgr2     |= FPER(framesize - 1);
 356                 regs->srgr1     |= FWID(0);
 357                 break;
 358         }
 359
 360         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 361         mcbsp->wlen = wlen;
 362         mcbsp->configured = 1;
 363
 364         return 0;
 365 }
 366
 367 /*
 368  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 369  * cache is initialized here
 370  */
 371 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 372                                       unsigned int fmt)
 373 {
 374         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 375         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 376         bool inv_fs = false;
 377
 378         if (mcbsp->configured)
 379                 return 0;
 380
 381         mcbsp->fmt = fmt;
 382         memset(regs, 0, sizeof(*regs));
 383         /* Generic McBSP register settings */
 384         regs->spcr2     |= XINTM(3) | FREE;
 385         regs->spcr1     |= RINTM(3);
 386         /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
 387         if (!mcbsp->pdata->has_ccr) {
 388                 regs->rcr2      |= RFIG;
 389                 regs->xcr2      |= XFIG;
 390         }
 391
 392         /* Configure XCCR/RCCR only for revisions which have ccr registers */
 393         if (mcbsp->pdata->has_ccr) {
 394                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 395                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 396         }
 397
 398         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 399         case SND_SOC_DAIFMT_I2S:
 400                 /* 1-bit data delay */
 401                 regs->rcr2      |= RDATDLY(1);
 402                 regs->xcr2      |= XDATDLY(1);
 403                 break;
 404         case SND_SOC_DAIFMT_LEFT_J:
 405                 /* 0-bit data delay */
 406                 regs->rcr2      |= RDATDLY(0);
 407                 regs->xcr2      |= XDATDLY(0);
 408                 regs->spcr1     |= RJUST(2);
 409                 /* Invert FS polarity configuration */
 410                 inv_fs = true;
 411                 break;
 412         case SND_SOC_DAIFMT_DSP_A:
 413                 /* 1-bit data delay */
 414                 regs->rcr2      |= RDATDLY(1);
 415                 regs->xcr2      |= XDATDLY(1);
 416                 /* Invert FS polarity configuration */
 417                 inv_fs = true;
 418                 break;
 419         case SND_SOC_DAIFMT_DSP_B:
 420                 /* 0-bit data delay */
 421                 regs->rcr2      |= RDATDLY(0);
 422                 regs->xcr2      |= XDATDLY(0);
 423                 /* Invert FS polarity configuration */
 424                 inv_fs = true;
 425                 break;
 426         default:
 427                 /* Unsupported data format */
 428                 return -EINVAL;
 429         }
 430
 431         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 432         case SND_SOC_DAIFMT_CBS_CFS:
 433                 /* McBSP master. Set FS and bit clocks as outputs */
 434                 regs->pcr0      |= FSXM | FSRM |
 435                                    CLKXM | CLKRM;
 436                 /* Sample rate generator drives the FS */
 437                 regs->srgr2     |= FSGM;
 438                 break;
 439         case SND_SOC_DAIFMT_CBM_CFM:
 440                 /* McBSP slave */
 441                 break;
 442         default:
 443                 /* Unsupported master/slave configuration */
 444                 return -EINVAL;
 445         }
 446
 447         /* Set bit clock (CLKX/CLKR) and FS polarities */
 448         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 449         case SND_SOC_DAIFMT_NB_NF:
 450                 /*
 451                  * Normal BCLK + FS.
 452                  * FS active low. TX data driven on falling edge of bit clock
 453                  * and RX data sampled on rising edge of bit clock.
 454                  */
 455                 regs->pcr0      |= FSXP | FSRP |
 456                                    CLKXP | CLKRP;
 457                 break;
 458         case SND_SOC_DAIFMT_NB_IF:
 459                 regs->pcr0      |= CLKXP | CLKRP;
 460                 break;
 461         case SND_SOC_DAIFMT_IB_NF:
 462                 regs->pcr0      |= FSXP | FSRP;
 463                 break;
 464         case SND_SOC_DAIFMT_IB_IF:
 465                 break;
 466         default:
 467                 return -EINVAL;
 468         }
 469         if (inv_fs == true)
 470                 regs->pcr0 ^= FSXP | FSRP;
 471
 472         return 0;
 473 }
 474
 475 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 476                                      int div_id, int div)
 477 {
 478         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 479         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 480
 481         if (div_id != OMAP_MCBSP_CLKGDV)
 482                 return -ENODEV;
 483
 484         mcbsp->clk_div = div;
 485         regs->srgr1     &= ~CLKGDV(0xff);
 486         regs->srgr1     |= CLKGDV(div - 1);
 487
 488         return 0;
 489 }
 490
 491 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 492                                          int clk_id, unsigned int freq,
 493                                          int dir)
 494 {
 495         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 496         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 497         int err = 0;
 498
 499         if (mcbsp->active) {
 500                 if (freq == mcbsp->in_freq)
 501                         return 0;
 502                 else
 503                         return -EBUSY;
 504         }
 505
 506         mcbsp->in_freq = freq;
 507         regs->srgr2 &= ~CLKSM;
 508         regs->pcr0 &= ~SCLKME;
 509
 510         switch (clk_id) {
 511         case OMAP_MCBSP_SYSCLK_CLK:
 512                 regs->srgr2     |= CLKSM;
 513                 break;
 514         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 515                 if (cpu_class_is_omap1()) {
 516                         err = -EINVAL;
 517                         break;
 518                 }
 519                 err = omap2_mcbsp_set_clks_src(mcbsp,
 520                                                MCBSP_CLKS_PRCM_SRC);
 521                 break;
 522         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 523                 if (cpu_class_is_omap1()) {
 524                         err = 0;
 525                         break;
 526                 }
 527                 err = omap2_mcbsp_set_clks_src(mcbsp,
 528                                                MCBSP_CLKS_PAD_SRC);
 529                 break;
 530
 531         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 532                 regs->srgr2     |= CLKSM;
 533         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 534                 regs->pcr0      |= SCLKME;
 535                 break;
 536         default:
 537                 err = -ENODEV;
 538         }
 539
 540         return err;
 541 }
 542
 543 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 544         .startup        = omap_mcbsp_dai_startup,
 545         .shutdown       = omap_mcbsp_dai_shutdown,
 546         .trigger        = omap_mcbsp_dai_trigger,
 547         .delay          = omap_mcbsp_dai_delay,
 548         .hw_params      = omap_mcbsp_dai_hw_params,
 549         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 550         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 551         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 552 };
 553
 554 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 555 {
 556         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 557
 558         pm_runtime_enable(mcbsp->dev);
 559
 560         return 0;
 561 }
 562
 563 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 564 {
 565         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 566
 567         pm_runtime_disable(mcbsp->dev);
 568
 569         return 0;
 570 }
 571
 572 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 573         .probe = omap_mcbsp_probe,
 574         .remove = omap_mcbsp_remove,
 575         .playback = {
 576                 .channels_min = 1,
 577                 .channels_max = 16,
 578                 .rates = OMAP_MCBSP_RATES,
 579                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 580         },
 581         .capture = {
 582                 .channels_min = 1,
 583                 .channels_max = 16,
 584                 .rates = OMAP_MCBSP_RATES,
 585                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 586         },
 587         .ops = &mcbsp_dai_ops,
 588 };
 589
 590 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 591                         struct snd_ctl_elem_info *uinfo)
 592 {
 593         struct soc_mixer_control *mc =
 594                 (struct soc_mixer_control *)kcontrol->private_value;
 595         int max = mc->max;
 596         int min = mc->min;
 597
 598         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 599         uinfo->count = 1;
 600         uinfo->value.integer.min = min;
 601         uinfo->value.integer.max = max;
 602         return 0;
 603 }
 604
 605 #define OMAP_MCBSP_ST_CHANNEL_VOLUME(channel)                           \
 606 static int                                                              \
 607 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 608                                         struct snd_ctl_elem_value *uc)  \
 609 {                                                                       \
 610         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 611         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 612         struct soc_mixer_control *mc =                                  \
 613                 (struct soc_mixer_control *)kc->private_value;          \
 614         int max = mc->max;                                              \
 615         int min = mc->min;                                              \
 616         int val = uc->value.integer.value[0];                           \
 617                                                                         \
 618         if (val < min || val > max)                                     \
 619                 return -EINVAL;                                         \
 620                                                                         \
 621         /* OMAP McBSP implementation uses index values 0..4 */          \
 622         return omap_st_set_chgain(mcbsp, channel, val);                 \
 623 }                                                                       \
 624                                                                         \
 625 static int                                                              \
 626 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc,         \
 627                                         struct snd_ctl_elem_value *uc)  \
 628 {                                                                       \
 629         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 630         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 631         s16 chgain;                                                     \
 632                                                                         \
 633         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 634                 return -EAGAIN;                                         \
 635                                                                         \
 636         uc->value.integer.value[0] = chgain;                            \
 637         return 0;                                                       \
 638 }
 639
 640 OMAP_MCBSP_ST_CHANNEL_VOLUME(0)
 641 OMAP_MCBSP_ST_CHANNEL_VOLUME(1)
 642
 643 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 644                                 struct snd_ctl_elem_value *ucontrol)
 645 {
 646         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 647         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 648         u8 value = ucontrol->value.integer.value[0];
 649
 650         if (value == omap_st_is_enabled(mcbsp))
 651                 return 0;
 652
 653         if (value)
 654                 omap_st_enable(mcbsp);
 655         else
 656                 omap_st_disable(mcbsp);
 657
 658         return 1;
 659 }
 660
 661 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 662                                 struct snd_ctl_elem_value *ucontrol)
 663 {
 664         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 665         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 666
 667         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 668         return 0;
 669 }
 670
 671 #define OMAP_MCBSP_ST_CONTROLS(port)                                      \
 672 static const struct snd_kcontrol_new omap_mcbsp##port##_st_controls[] = { \
 673 SOC_SINGLE_EXT("McBSP" #port " Sidetone Switch", 1, 0, 1, 0,              \
 674                omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),           \
 675 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 0 Volume", \
 676                               -32768, 32767,                              \
 677                               omap_mcbsp_get_st_ch0_volume,               \
 678                               omap_mcbsp_set_st_ch0_volume),              \
 679 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP" #port " Sidetone Channel 1 Volume", \
 680                               -32768, 32767,                              \
 681                               omap_mcbsp_get_st_ch1_volume,               \
 682                               omap_mcbsp_set_st_ch1_volume),              \
 683 }
 684
 685 OMAP_MCBSP_ST_CONTROLS(2);
 686 OMAP_MCBSP_ST_CONTROLS(3);
 687
 688 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 689 {
 690         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 691         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 692
 693         if (!mcbsp->st_data) {
 694                 dev_warn(mcbsp->dev, "No sidetone data for port\n");
 695                 return 0;
 696         }
 697
 698         switch (mcbsp->id) {
 699         case 2: /* McBSP 2 */
 700                 return snd_soc_add_dai_controls(cpu_dai,
 701                                         omap_mcbsp2_st_controls,
 702                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 703         case 3: /* McBSP 3 */
 704                 return snd_soc_add_dai_controls(cpu_dai,
 705                                         omap_mcbsp3_st_controls,
 706                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 707         default:
 708                 break;
 709         }
 710
 711         return -EINVAL;
 712 }
 713 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 714
 715 static struct omap_mcbsp_platform_data omap2420_pdata = {
 716         .reg_step = 4,
 717         .reg_size = 2,
 718 };
 719
 720 static struct omap_mcbsp_platform_data omap2430_pdata = {
 721         .reg_step = 4,
 722         .reg_size = 4,
 723         .has_ccr = true,
 724 };
 725
 726 static struct omap_mcbsp_platform_data omap3_pdata = {
 727         .reg_step = 4,
 728         .reg_size = 4,
 729         .has_ccr = true,
 730         .has_wakeup = true,
 731 };
 732
 733 static struct omap_mcbsp_platform_data omap4_pdata = {
 734         .reg_step = 4,
 735         .reg_size = 4,
 736         .has_ccr = true,
 737         .has_wakeup = true,
 738 };
 739
 740 static const struct of_device_id omap_mcbsp_of_match[] = {
 741         {
 742                 .compatible = "ti,omap2420-mcbsp",
 743                 .data = &omap2420_pdata,
 744         },
 745         {
 746                 .compatible = "ti,omap2430-mcbsp",
 747                 .data = &omap2430_pdata,
 748         },
 749         {
 750                 .compatible = "ti,omap3-mcbsp",
 751                 .data = &omap3_pdata,
 752         },
 753         {
 754                 .compatible = "ti,omap4-mcbsp",
 755                 .data = &omap4_pdata,
 756         },
 757         { },
 758 };
 759 MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
 760
 761 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 762 {
 763         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 764         struct omap_mcbsp *mcbsp;
 765         const struct of_device_id *match;
 766         int ret;
 767
 768         match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
 769         if (match) {
 770                 struct device_node *node = pdev->dev.of_node;
 771                 int buffer_size;
 772
 773                 pdata = devm_kzalloc(&pdev->dev,
 774                                      sizeof(struct omap_mcbsp_platform_data),
 775                                      GFP_KERNEL);
 776                 if (!pdata)
 777                         return -ENOMEM;
 778
 779                 memcpy(pdata, match->data, sizeof(*pdata));
 780                 if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
 781                         pdata->buffer_size = buffer_size;
 782         } else if (!pdata) {
 783                 dev_err(&pdev->dev, "missing platform data.\n");
 784                 return -EINVAL;
 785         }
 786         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 787         if (!mcbsp)
 788                 return -ENOMEM;
 789
 790         mcbsp->id = pdev->id;
 791         mcbsp->pdata = pdata;
 792         mcbsp->dev = &pdev->dev;
 793         platform_set_drvdata(pdev, mcbsp);
 794
 795         ret = omap_mcbsp_init(pdev);
 796         if (!ret)
 797                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 798
 799         return ret;
 800 }
 801
 802 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 803 {
 804         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 805
 806         snd_soc_unregister_dai(&pdev->dev);
 807
 808         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 809                 mcbsp->pdata->ops->free(mcbsp->id);
 810
 811         omap_mcbsp_sysfs_remove(mcbsp);
 812
 813         clk_put(mcbsp->fclk);
 814
 815         platform_set_drvdata(pdev, NULL);
 816
 817         return 0;
 818 }
 819
 820 static struct platform_driver asoc_mcbsp_driver = {
 821         .driver = {
 822                         .name = "omap-mcbsp",
 823                         .owner = THIS_MODULE,
 824                         .of_match_table = omap_mcbsp_of_match,
 825         },
 826
 827         .probe = asoc_mcbsp_probe,
 828         .remove = __devexit_p(asoc_mcbsp_remove),
 829 };
 830
 831 module_platform_driver(asoc_mcbsp_driver);
 832
 833 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 834 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 835 MODULE_LICENSE("GPL");
 836 MODULE_ALIAS("platform:omap-mcbsp");