sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/dma.h>
  35 #include <plat/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  40
  41 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  42         xhandler_get, xhandler_put) \
  43 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  44         .info = omap_mcbsp_st_info_volsw, \
  45         .get = xhandler_get, .put = xhandler_put, \
  46         .private_value = (unsigned long) &(struct soc_mixer_control) \
  47         {.min = xmin, .max = xmax} }
  48
  49 struct omap_mcbsp_data {
  50         unsigned int                    bus_id;
  51         struct omap_mcbsp_reg_cfg       regs;
  52         unsigned int                    fmt;
  53         /*
  54          * Flags indicating is the bus already activated and configured by
  55          * another substream
  56          */
  57         int                             active;
  58         int                             configured;
  59         unsigned int                    in_freq;
  60         int                             clk_div;
  61         int                             wlen;
  62 };
  63
  64 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  65
  66 /*
  67  * Stream DMA parameters. DMA request line and port address are set runtime
  68  * since they are different between OMAP1 and later OMAPs
  69  */
  70 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  71
  72 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  73 static const int omap1_dma_reqs[][2] = {
  74         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  75         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  76         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  77 };
  78 static const unsigned long omap1_mcbsp_port[][2] = {
  79         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  80           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  81         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  82           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  83         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  84           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  85 };
  86 #else
  87 static const int omap1_dma_reqs[][2] = {};
  88 static const unsigned long omap1_mcbsp_port[][2] = {};
  89 #endif
  90
  91 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  92 static const int omap24xx_dma_reqs[][2] = {
  93         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  94         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  95 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  96         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  97         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  98         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  99 #endif
 100 };
 101 #else
 102 static const int omap24xx_dma_reqs[][2] = {};
 103 #endif
 104
 105 #if defined(CONFIG_ARCH_OMAP4)
 106 static const int omap44xx_dma_reqs[][2] = {
 107         { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX },
 108         { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX },
 109         { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX },
 110         { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX },
 111 };
 112 #else
 113 static const int omap44xx_dma_reqs[][2] = {};
 114 #endif
 115
 116 #if defined(CONFIG_ARCH_OMAP2420)
 117 static const unsigned long omap2420_mcbsp_port[][2] = {
 118         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 119           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 120         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 121           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 122 };
 123 #else
 124 static const unsigned long omap2420_mcbsp_port[][2] = {};
 125 #endif
 126
 127 #if defined(CONFIG_ARCH_OMAP2430)
 128 static const unsigned long omap2430_mcbsp_port[][2] = {
 129         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 131         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 132           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 133         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 134           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 135         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 136           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 137         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 138           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 139 };
 140 #else
 141 static const unsigned long omap2430_mcbsp_port[][2] = {};
 142 #endif
 143
 144 #if defined(CONFIG_ARCH_OMAP3)
 145 static const unsigned long omap34xx_mcbsp_port[][2] = {
 146         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 147           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 148         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 149           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 150         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 151           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 152         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 153           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 154         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 155           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 156 };
 157 #else
 158 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 159 #endif
 160
 161 #if defined(CONFIG_ARCH_OMAP4)
 162 static const unsigned long omap44xx_mcbsp_port[][2] = {
 163         { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 164           OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 165         { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 166           OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 167         { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 168           OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 169         { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 170           OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 171 };
 172 #else
 173 static const unsigned long omap44xx_mcbsp_port[][2] = {};
 174 #endif
 175
 176 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 177 {
 178         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 179         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 180         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 181         struct omap_pcm_dma_data *dma_data;
 182         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 183         int words;
 184
 185         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
 186
 187         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 188         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 189                 /*
 190                  * Configure McBSP threshold based on either:
 191                  * packet_size, when the sDMA is in packet mode, or
 192                  * based on the period size.
 193                  */
 194                 if (dma_data->packet_size)
 195                         words = dma_data->packet_size;
 196                 else
 197                         words = snd_pcm_lib_period_bytes(substream) /
 198                                                         (mcbsp_data->wlen / 8);
 199         else
 200                 words = 1;
 201
 202         /* Configure McBSP internal buffer usage */
 203         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 204                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
 205         else
 206                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
 207 }
 208
 209 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 210                                     struct snd_pcm_hw_rule *rule)
 211 {
 212         struct snd_interval *buffer_size = hw_param_interval(params,
 213                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 214         struct snd_interval *channels = hw_param_interval(params,
 215                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 216         struct omap_mcbsp_data *mcbsp_data = rule->private;
 217         struct snd_interval frames;
 218         int size;
 219
 220         snd_interval_any(&frames);
 221         size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
 222
 223         frames.min = size / channels->min;
 224         frames.integer = 1;
 225         return snd_interval_refine(buffer_size, &frames);
 226 }
 227
 228 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 229                                   struct snd_soc_dai *cpu_dai)
 230 {
 231         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 232         int bus_id = mcbsp_data->bus_id;
 233         int err = 0;
 234
 235         if (!cpu_dai->active)
 236                 err = omap_mcbsp_request(bus_id);
 237
 238         /*
 239          * OMAP3 McBSP FIFO is word structured.
 240          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 241          * McBSP1,3,4,5 has 128 word long buffer
 242          * This means that the size of the FIFO depends on the sample format.
 243          * For example on McBSP3:
 244          * 16bit samples: size is 128 * 2 = 256 bytes
 245          * 32bit samples: size is 128 * 4 = 512 bytes
 246          * It is simpler to place constraint for buffer and period based on
 247          * channels.
 248          * McBSP3 as example again (16 or 32 bit samples):
 249          * 1 channel (mono): size is 128 frames (128 words)
 250          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 251          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 252          */
 253         if (cpu_is_omap343x() || cpu_is_omap44xx()) {
 254                 /*
 255                 * Rule for the buffer size. We should not allow
 256                 * smaller buffer than the FIFO size to avoid underruns
 257                 */
 258                 snd_pcm_hw_rule_add(substream->runtime, 0,
 259                                     SNDRV_PCM_HW_PARAM_CHANNELS,
 260                                     omap_mcbsp_hwrule_min_buffersize,
 261                                     mcbsp_data,
 262                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 263
 264                 /* Make sure, that the period size is always even */
 265                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 266                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 267         }
 268
 269         return err;
 270 }
 271
 272 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 273                                     struct snd_soc_dai *cpu_dai)
 274 {
 275         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 276
 277         if (!cpu_dai->active) {
 278                 omap_mcbsp_free(mcbsp_data->bus_id);
 279                 mcbsp_data->configured = 0;
 280         }
 281 }
 282
 283 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 284                                   struct snd_soc_dai *cpu_dai)
 285 {
 286         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 287         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 288
 289         switch (cmd) {
 290         case SNDRV_PCM_TRIGGER_START:
 291         case SNDRV_PCM_TRIGGER_RESUME:
 292         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 293                 mcbsp_data->active++;
 294                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 295                 break;
 296
 297         case SNDRV_PCM_TRIGGER_STOP:
 298         case SNDRV_PCM_TRIGGER_SUSPEND:
 299         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 300                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 301                 mcbsp_data->active--;
 302                 break;
 303         default:
 304                 err = -EINVAL;
 305         }
 306
 307         return err;
 308 }
 309
 310 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 311                         struct snd_pcm_substream *substream,
 312                         struct snd_soc_dai *dai)
 313 {
 314         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 315         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 316         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 317         u16 fifo_use;
 318         snd_pcm_sframes_t delay;
 319
 320         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 321                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
 322         else
 323                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
 324
 325         /*
 326          * Divide the used locations with the channel count to get the
 327          * FIFO usage in samples (don't care about partial samples in the
 328          * buffer).
 329          */
 330         delay = fifo_use / substream->runtime->channels;
 331
 332         return delay;
 333 }
 334
 335 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 336                                     struct snd_pcm_hw_params *params,
 337                                     struct snd_soc_dai *cpu_dai)
 338 {
 339         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 340         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 341         struct omap_pcm_dma_data *dma_data;
 342         int dma, bus_id = mcbsp_data->bus_id;
 343         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 344         int pkt_size = 0;
 345         unsigned long port;
 346         unsigned int format, div, framesize, master;
 347
 348         dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
 349         if (cpu_class_is_omap1()) {
 350                 dma = omap1_dma_reqs[bus_id][substream->stream];
 351                 port = omap1_mcbsp_port[bus_id][substream->stream];
 352         } else if (cpu_is_omap2420()) {
 353                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 354                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 355         } else if (cpu_is_omap2430()) {
 356                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 357                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 358         } else if (cpu_is_omap343x()) {
 359                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 360                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 361          } else if (cpu_is_omap44xx()) {
 362                 dma = omap44xx_dma_reqs[bus_id][substream->stream];
 363                 port = omap44xx_mcbsp_port[bus_id][substream->stream];
 364         } else {
 365                 return -ENODEV;
 366         }
 367         switch (params_format(params)) {
 368         case SNDRV_PCM_FORMAT_S16_LE:
 369                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 370                 wlen = 16;
 371                 break;
 372         case SNDRV_PCM_FORMAT_S32_LE:
 373                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 374                 wlen = 32;
 375                 break;
 376         default:
 377                 return -EINVAL;
 378         }
 379         if (cpu_is_omap343x()) {
 380                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 381                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 382                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 383                                                 MCBSP_DMA_MODE_THRESHOLD) {
 384                         int period_words, max_thrsh;
 385
 386                         period_words = params_period_bytes(params) / (wlen / 8);
 387                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 388                                 max_thrsh = omap_mcbsp_get_max_tx_threshold(
 389                                                             mcbsp_data->bus_id);
 390                         else
 391                                 max_thrsh = omap_mcbsp_get_max_rx_threshold(
 392                                                             mcbsp_data->bus_id);
 393                         /*
 394                          * If the period contains less or equal number of words,
 395                          * we are using the original threshold mode setup:
 396                          * McBSP threshold = sDMA frame size = period_size
 397                          * Otherwise we switch to sDMA packet mode:
 398                          * McBSP threshold = sDMA packet size
 399                          * sDMA frame size = period size
 400                          */
 401                         if (period_words > max_thrsh) {
 402                                 int divider = 0;
 403
 404                                 /*
 405                                  * Look for the biggest threshold value, which
 406                                  * divides the period size evenly.
 407                                  */
 408                                 divider = period_words / max_thrsh;
 409                                 if (period_words % max_thrsh)
 410                                         divider++;
 411                                 while (period_words % divider &&
 412                                         divider < period_words)
 413                                         divider++;
 414                                 if (divider == period_words)
 415                                         return -EINVAL;
 416
 417                                 pkt_size = period_words / divider;
 418                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 419                         } else {
 420                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 421                         }
 422                 }
 423         }
 424
 425         dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
 426         dma_data->dma_req = dma;
 427         dma_data->port_addr = port;
 428         dma_data->sync_mode = sync_mode;
 429         dma_data->packet_size = pkt_size;
 430
 431         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 432
 433         if (mcbsp_data->configured) {
 434                 /* McBSP already configured by another stream */
 435                 return 0;
 436         }
 437
 438         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 439         wpf = channels = params_channels(params);
 440         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 441                               format == SND_SOC_DAIFMT_LEFT_J)) {
 442                 /* Use dual-phase frames */
 443                 regs->rcr2      |= RPHASE;
 444                 regs->xcr2      |= XPHASE;
 445                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 446                 wpf--;
 447                 regs->rcr2      |= RFRLEN2(wpf - 1);
 448                 regs->xcr2      |= XFRLEN2(wpf - 1);
 449         }
 450
 451         regs->rcr1      |= RFRLEN1(wpf - 1);
 452         regs->xcr1      |= XFRLEN1(wpf - 1);
 453
 454         switch (params_format(params)) {
 455         case SNDRV_PCM_FORMAT_S16_LE:
 456                 /* Set word lengths */
 457                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 458                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 459                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 460                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 461                 break;
 462         case SNDRV_PCM_FORMAT_S32_LE:
 463                 /* Set word lengths */
 464                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 465                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 466                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 467                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 468                 break;
 469         default:
 470                 /* Unsupported PCM format */
 471                 return -EINVAL;
 472         }
 473
 474         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 475          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 476         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 477         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 478                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 479                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 480
 481                 if (framesize < wlen * channels) {
 482                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 483                                         "channels\n", __func__);
 484                         return -EINVAL;
 485                 }
 486         } else
 487                 framesize = wlen * channels;
 488
 489         /* Set FS period and length in terms of bit clock periods */
 490         switch (format) {
 491         case SND_SOC_DAIFMT_I2S:
 492         case SND_SOC_DAIFMT_LEFT_J:
 493                 regs->srgr2     |= FPER(framesize - 1);
 494                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 495                 break;
 496         case SND_SOC_DAIFMT_DSP_A:
 497         case SND_SOC_DAIFMT_DSP_B:
 498                 regs->srgr2     |= FPER(framesize - 1);
 499                 regs->srgr1     |= FWID(0);
 500                 break;
 501         }
 502
 503         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 504         mcbsp_data->wlen = wlen;
 505         mcbsp_data->configured = 1;
 506
 507         return 0;
 508 }
 509
 510 /*
 511  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 512  * cache is initialized here
 513  */
 514 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 515                                       unsigned int fmt)
 516 {
 517         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 518         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 519         unsigned int temp_fmt = fmt;
 520
 521         if (mcbsp_data->configured)
 522                 return 0;
 523
 524         mcbsp_data->fmt = fmt;
 525         memset(regs, 0, sizeof(*regs));
 526         /* Generic McBSP register settings */
 527         regs->spcr2     |= XINTM(3) | FREE;
 528         regs->spcr1     |= RINTM(3);
 529         /* RFIG and XFIG are not defined in 34xx */
 530         if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
 531                 regs->rcr2      |= RFIG;
 532                 regs->xcr2      |= XFIG;
 533         }
 534         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 535                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 536                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 537         }
 538
 539         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 540         case SND_SOC_DAIFMT_I2S:
 541                 /* 1-bit data delay */
 542                 regs->rcr2      |= RDATDLY(1);
 543                 regs->xcr2      |= XDATDLY(1);
 544                 break;
 545         case SND_SOC_DAIFMT_LEFT_J:
 546                 /* 0-bit data delay */
 547                 regs->rcr2      |= RDATDLY(0);
 548                 regs->xcr2      |= XDATDLY(0);
 549                 regs->spcr1     |= RJUST(2);
 550                 /* Invert FS polarity configuration */
 551                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 552                 break;
 553         case SND_SOC_DAIFMT_DSP_A:
 554                 /* 1-bit data delay */
 555                 regs->rcr2      |= RDATDLY(1);
 556                 regs->xcr2      |= XDATDLY(1);
 557                 /* Invert FS polarity configuration */
 558                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 559                 break;
 560         case SND_SOC_DAIFMT_DSP_B:
 561                 /* 0-bit data delay */
 562                 regs->rcr2      |= RDATDLY(0);
 563                 regs->xcr2      |= XDATDLY(0);
 564                 /* Invert FS polarity configuration */
 565                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 566                 break;
 567         default:
 568                 /* Unsupported data format */
 569                 return -EINVAL;
 570         }
 571
 572         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 573         case SND_SOC_DAIFMT_CBS_CFS:
 574                 /* McBSP master. Set FS and bit clocks as outputs */
 575                 regs->pcr0      |= FSXM | FSRM |
 576                                    CLKXM | CLKRM;
 577                 /* Sample rate generator drives the FS */
 578                 regs->srgr2     |= FSGM;
 579                 break;
 580         case SND_SOC_DAIFMT_CBM_CFM:
 581                 /* McBSP slave */
 582                 break;
 583         default:
 584                 /* Unsupported master/slave configuration */
 585                 return -EINVAL;
 586         }
 587
 588         /* Set bit clock (CLKX/CLKR) and FS polarities */
 589         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 590         case SND_SOC_DAIFMT_NB_NF:
 591                 /*
 592                  * Normal BCLK + FS.
 593                  * FS active low. TX data driven on falling edge of bit clock
 594                  * and RX data sampled on rising edge of bit clock.
 595                  */
 596                 regs->pcr0      |= FSXP | FSRP |
 597                                    CLKXP | CLKRP;
 598                 break;
 599         case SND_SOC_DAIFMT_NB_IF:
 600                 regs->pcr0      |= CLKXP | CLKRP;
 601                 break;
 602         case SND_SOC_DAIFMT_IB_NF:
 603                 regs->pcr0      |= FSXP | FSRP;
 604                 break;
 605         case SND_SOC_DAIFMT_IB_IF:
 606                 break;
 607         default:
 608                 return -EINVAL;
 609         }
 610
 611         return 0;
 612 }
 613
 614 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 615                                      int div_id, int div)
 616 {
 617         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 618         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 619
 620         if (div_id != OMAP_MCBSP_CLKGDV)
 621                 return -ENODEV;
 622
 623         mcbsp_data->clk_div = div;
 624         regs->srgr1     |= CLKGDV(div - 1);
 625
 626         return 0;
 627 }
 628
 629 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 630                                          int clk_id, unsigned int freq,
 631                                          int dir)
 632 {
 633         struct omap_mcbsp_data *mcbsp_data = snd_soc_dai_get_drvdata(cpu_dai);
 634         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 635         int err = 0;
 636
 637         /* The McBSP signal muxing functions are only available on McBSP1 */
 638         if (clk_id == OMAP_MCBSP_CLKR_SRC_CLKR ||
 639             clk_id == OMAP_MCBSP_CLKR_SRC_CLKX ||
 640             clk_id == OMAP_MCBSP_FSR_SRC_FSR ||
 641             clk_id == OMAP_MCBSP_FSR_SRC_FSX)
 642                 if (cpu_class_is_omap1() || mcbsp_data->bus_id != 0)
 643                         return -EINVAL;
 644
 645         mcbsp_data->in_freq = freq;
 646
 647         switch (clk_id) {
 648         case OMAP_MCBSP_SYSCLK_CLK:
 649                 regs->srgr2     |= CLKSM;
 650                 break;
 651         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 652                 if (cpu_class_is_omap1()) {
 653                         err = -EINVAL;
 654                         break;
 655                 }
 656                 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
 657                                                MCBSP_CLKS_PRCM_SRC);
 658                 break;
 659         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 660                 if (cpu_class_is_omap1()) {
 661                         err = 0;
 662                         break;
 663                 }
 664                 err = omap2_mcbsp_set_clks_src(mcbsp_data->bus_id,
 665                                                MCBSP_CLKS_PAD_SRC);
 666                 break;
 667
 668         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 669                 regs->srgr2     |= CLKSM;
 670         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 671                 regs->pcr0      |= SCLKME;
 672                 break;
 673
 674
 675         case OMAP_MCBSP_CLKR_SRC_CLKR:
 676                 if (cpu_class_is_omap1())
 677                         break;
 678                 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKR);
 679                 break;
 680         case OMAP_MCBSP_CLKR_SRC_CLKX:
 681                 if (cpu_class_is_omap1())
 682                         break;
 683                 omap2_mcbsp1_mux_clkr_src(CLKR_SRC_CLKX);
 684                 break;
 685         case OMAP_MCBSP_FSR_SRC_FSR:
 686                 if (cpu_class_is_omap1())
 687                         break;
 688                 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSR);
 689                 break;
 690         case OMAP_MCBSP_FSR_SRC_FSX:
 691                 if (cpu_class_is_omap1())
 692                         break;
 693                 omap2_mcbsp1_mux_fsr_src(FSR_SRC_FSX);
 694                 break;
 695         default:
 696                 err = -ENODEV;
 697         }
 698
 699         return err;
 700 }
 701
 702 static struct snd_soc_dai_ops mcbsp_dai_ops = {
 703         .startup        = omap_mcbsp_dai_startup,
 704         .shutdown       = omap_mcbsp_dai_shutdown,
 705         .trigger        = omap_mcbsp_dai_trigger,
 706         .delay          = omap_mcbsp_dai_delay,
 707         .hw_params      = omap_mcbsp_dai_hw_params,
 708         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 709         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 710         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 711 };
 712
 713 static int mcbsp_dai_probe(struct snd_soc_dai *dai)
 714 {
 715         mcbsp_data[dai->id].bus_id = dai->id;
 716         snd_soc_dai_set_drvdata(dai, &mcbsp_data[dai->id].bus_id);
 717         return 0;
 718 }
 719
 720 static struct snd_soc_dai_driver omap_mcbsp_dai =
 721 {
 722         .probe = mcbsp_dai_probe,
 723         .playback = {
 724                 .channels_min = 1,
 725                 .channels_max = 16,
 726                 .rates = OMAP_MCBSP_RATES,
 727                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 728         },
 729         .capture = {
 730                 .channels_min = 1,
 731                 .channels_max = 16,
 732                 .rates = OMAP_MCBSP_RATES,
 733                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 734         },
 735         .ops = &mcbsp_dai_ops,
 736 };
 737
 738 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 739                         struct snd_ctl_elem_info *uinfo)
 740 {
 741         struct soc_mixer_control *mc =
 742                 (struct soc_mixer_control *)kcontrol->private_value;
 743         int max = mc->max;
 744         int min = mc->min;
 745
 746         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 747         uinfo->count = 1;
 748         uinfo->value.integer.min = min;
 749         uinfo->value.integer.max = max;
 750         return 0;
 751 }
 752
 753 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
 754 static int                                                              \
 755 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 756                                         struct snd_ctl_elem_value *uc)  \
 757 {                                                                       \
 758         struct soc_mixer_control *mc =                                  \
 759                 (struct soc_mixer_control *)kc->private_value;          \
 760         int max = mc->max;                                              \
 761         int min = mc->min;                                              \
 762         int val = uc->value.integer.value[0];                           \
 763                                                                         \
 764         if (val < min || val > max)                                     \
 765                 return -EINVAL;                                         \
 766                                                                         \
 767         /* OMAP McBSP implementation uses index values 0..4 */          \
 768         return omap_st_set_chgain((id)-1, channel, val);                \
 769 }
 770
 771 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
 772 static int                                                              \
 773 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 774                                         struct snd_ctl_elem_value *uc)  \
 775 {                                                                       \
 776         s16 chgain;                                                     \
 777                                                                         \
 778         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
 779                 return -EAGAIN;                                         \
 780                                                                         \
 781         uc->value.integer.value[0] = chgain;                            \
 782         return 0;                                                       \
 783 }
 784
 785 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
 786 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
 787 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
 788 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
 789 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
 790 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
 791 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
 792 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
 793
 794 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 795                                 struct snd_ctl_elem_value *ucontrol)
 796 {
 797         struct soc_mixer_control *mc =
 798                 (struct soc_mixer_control *)kcontrol->private_value;
 799         u8 value = ucontrol->value.integer.value[0];
 800
 801         if (value == omap_st_is_enabled(mc->reg))
 802                 return 0;
 803
 804         if (value)
 805                 omap_st_enable(mc->reg);
 806         else
 807                 omap_st_disable(mc->reg);
 808
 809         return 1;
 810 }
 811
 812 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 813                                 struct snd_ctl_elem_value *ucontrol)
 814 {
 815         struct soc_mixer_control *mc =
 816                 (struct soc_mixer_control *)kcontrol->private_value;
 817
 818         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
 819         return 0;
 820 }
 821
 822 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 823         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 824                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 825         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 826                                       -32768, 32767,
 827                                       omap_mcbsp2_get_st_ch0_volume,
 828                                       omap_mcbsp2_set_st_ch0_volume),
 829         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 830                                       -32768, 32767,
 831                                       omap_mcbsp2_get_st_ch1_volume,
 832                                       omap_mcbsp2_set_st_ch1_volume),
 833 };
 834
 835 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 836         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 837                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 838         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 839                                       -32768, 32767,
 840                                       omap_mcbsp3_get_st_ch0_volume,
 841                                       omap_mcbsp3_set_st_ch0_volume),
 842         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 843                                       -32768, 32767,
 844                                       omap_mcbsp3_get_st_ch1_volume,
 845                                       omap_mcbsp3_set_st_ch1_volume),
 846 };
 847
 848 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
 849 {
 850         if (!cpu_is_omap34xx())
 851                 return -ENODEV;
 852
 853         switch (mcbsp_id) {
 854         case 1: /* McBSP 2 */
 855                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
 856                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 857         case 2: /* McBSP 3 */
 858                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
 859                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 860         default:
 861                 break;
 862         }
 863
 864         return -EINVAL;
 865 }
 866 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 867
 868 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 869 {
 870         return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 871 }
 872
 873 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 874 {
 875         snd_soc_unregister_dai(&pdev->dev);
 876         return 0;
 877 }
 878
 879 static struct platform_driver asoc_mcbsp_driver = {
 880         .driver = {
 881                         .name = "omap-mcbsp-dai",
 882                         .owner = THIS_MODULE,
 883         },
 884
 885         .probe = asoc_mcbsp_probe,
 886         .remove = __devexit_p(asoc_mcbsp_remove),
 887 };
 888
 889 static int __init snd_omap_mcbsp_init(void)
 890 {
 891         return platform_driver_register(&asoc_mcbsp_driver);
 892 }
 893 module_init(snd_omap_mcbsp_init);
 894
 895 static void __exit snd_omap_mcbsp_exit(void)
 896 {
 897         platform_driver_unregister(&asoc_mcbsp_driver);
 898 }
 899 module_exit(snd_omap_mcbsp_exit);
 900
 901 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 902 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 903 MODULE_LICENSE("GPL");