sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/control.h>
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 struct omap_mcbsp_data {
  43         unsigned int                    bus_id;
  44         struct omap_mcbsp_reg_cfg       regs;
  45         unsigned int                    fmt;
  46         /*
  47          * Flags indicating is the bus already activated and configured by
  48          * another substream
  49          */
  50         int                             active;
  51         int                             configured;
  52         unsigned int                    in_freq;
  53         int                             clk_div;
  54 };
  55
  56 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  57
  58 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  59
  60 /*
  61  * Stream DMA parameters. DMA request line and port address are set runtime
  62  * since they are different between OMAP1 and later OMAPs
  63  */
  64 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  65
  66 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  67 static const int omap1_dma_reqs[][2] = {
  68         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  69         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  70         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  71 };
  72 static const unsigned long omap1_mcbsp_port[][2] = {
  73         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  74           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  75         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  76           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  77         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  78           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  79 };
  80 #else
  81 static const int omap1_dma_reqs[][2] = {};
  82 static const unsigned long omap1_mcbsp_port[][2] = {};
  83 #endif
  84
  85 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  86 static const int omap24xx_dma_reqs[][2] = {
  87         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  88         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  89 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  90         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  91         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  92         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  93 #endif
  94 };
  95 #else
  96 static const int omap24xx_dma_reqs[][2] = {};
  97 #endif
  98
  99 #if defined(CONFIG_ARCH_OMAP2420)
 100 static const unsigned long omap2420_mcbsp_port[][2] = {
 101         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 102           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 103         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 104           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 105 };
 106 #else
 107 static const unsigned long omap2420_mcbsp_port[][2] = {};
 108 #endif
 109
 110 #if defined(CONFIG_ARCH_OMAP2430)
 111 static const unsigned long omap2430_mcbsp_port[][2] = {
 112         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 113           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 114         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 115           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 116         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 117           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 118         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 119           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 120         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 121           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 122 };
 123 #else
 124 static const unsigned long omap2430_mcbsp_port[][2] = {};
 125 #endif
 126
 127 #if defined(CONFIG_ARCH_OMAP34XX)
 128 static const unsigned long omap34xx_mcbsp_port[][2] = {
 129         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 131         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 132           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 133         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 134           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 135         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 136           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 137         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 138           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 139 };
 140 #else
 141 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 142 #endif
 143
 144 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 145 {
 146         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 147         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 148         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 149         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 150         int samples;
 151
 152         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 153         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 154                 samples = snd_pcm_lib_period_bytes(substream) >> 1;
 155         else
 156                 samples = 1;
 157
 158         /* Configure McBSP internal buffer usage */
 159         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 160                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
 161         else
 162                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
 163 }
 164
 165 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 166                                   struct snd_soc_dai *dai)
 167 {
 168         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 169         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 170         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 171         int bus_id = mcbsp_data->bus_id;
 172         int err = 0;
 173
 174         if (!cpu_dai->active)
 175                 err = omap_mcbsp_request(bus_id);
 176
 177         if (cpu_is_omap343x()) {
 178                 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
 179                 int max_period;
 180
 181                 /*
 182                  * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
 183                  * Set constraint for minimum buffer size to the same than FIFO
 184                  * size in order to avoid underruns in playback startup because
 185                  * HW is keeping the DMA request active until FIFO is filled.
 186                  */
 187                 if (bus_id == 1)
 188                         snd_pcm_hw_constraint_minmax(substream->runtime,
 189                                         SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 190                                         4096, UINT_MAX);
 191
 192                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 193                         max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
 194                 else
 195                         max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
 196
 197                 max_period++;
 198                 max_period <<= 1;
 199
 200                 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 201                         snd_pcm_hw_constraint_minmax(substream->runtime,
 202                                                 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 203                                                 32, max_period);
 204         }
 205
 206         return err;
 207 }
 208
 209 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 210                                     struct snd_soc_dai *dai)
 211 {
 212         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 213         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 214         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 215
 216         if (!cpu_dai->active) {
 217                 omap_mcbsp_free(mcbsp_data->bus_id);
 218                 mcbsp_data->configured = 0;
 219         }
 220 }
 221
 222 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 223                                   struct snd_soc_dai *dai)
 224 {
 225         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 226         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 227         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 228         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 229
 230         switch (cmd) {
 231         case SNDRV_PCM_TRIGGER_START:
 232         case SNDRV_PCM_TRIGGER_RESUME:
 233         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 234                 mcbsp_data->active++;
 235                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 236                 break;
 237
 238         case SNDRV_PCM_TRIGGER_STOP:
 239         case SNDRV_PCM_TRIGGER_SUSPEND:
 240         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 241                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 242                 mcbsp_data->active--;
 243                 break;
 244         default:
 245                 err = -EINVAL;
 246         }
 247
 248         return err;
 249 }
 250
 251 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 252                                     struct snd_pcm_hw_params *params,
 253                                     struct snd_soc_dai *dai)
 254 {
 255         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 256         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 257         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 258         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 259         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 260         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 261         unsigned long port;
 262         unsigned int format, div, framesize, master;
 263
 264         if (cpu_class_is_omap1()) {
 265                 dma = omap1_dma_reqs[bus_id][substream->stream];
 266                 port = omap1_mcbsp_port[bus_id][substream->stream];
 267         } else if (cpu_is_omap2420()) {
 268                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 269                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 270         } else if (cpu_is_omap2430()) {
 271                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 272                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 273         } else if (cpu_is_omap343x()) {
 274                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 275                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 276                 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
 277                                                 omap_mcbsp_set_threshold;
 278                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 279                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 280                                                 MCBSP_DMA_MODE_THRESHOLD)
 281                         sync_mode = OMAP_DMA_SYNC_FRAME;
 282         } else {
 283                 return -ENODEV;
 284         }
 285         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 286                 substream->stream ? "Audio Capture" : "Audio Playback";
 287         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 288         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 289         omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
 290         omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
 291                                                         OMAP_DMA_DATA_TYPE_S16;
 292         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 293
 294         if (mcbsp_data->configured) {
 295                 /* McBSP already configured by another stream */
 296                 return 0;
 297         }
 298
 299         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 300         wpf = channels = params_channels(params);
 301         if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
 302                 /* Use dual-phase frames */
 303                 regs->rcr2      |= RPHASE;
 304                 regs->xcr2      |= XPHASE;
 305                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 306                 wpf--;
 307                 regs->rcr2      |= RFRLEN2(wpf - 1);
 308                 regs->xcr2      |= XFRLEN2(wpf - 1);
 309         }
 310
 311         regs->rcr1      |= RFRLEN1(wpf - 1);
 312         regs->xcr1      |= XFRLEN1(wpf - 1);
 313
 314         switch (params_format(params)) {
 315         case SNDRV_PCM_FORMAT_S16_LE:
 316                 /* Set word lengths */
 317                 wlen = 16;
 318                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 319                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 320                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 321                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 322                 break;
 323         default:
 324                 /* Unsupported PCM format */
 325                 return -EINVAL;
 326         }
 327
 328         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 329          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 330         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 331         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 332                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 333                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 334
 335                 if (framesize < wlen * channels) {
 336                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 337                                         "channels\n", __func__);
 338                         return -EINVAL;
 339                 }
 340         } else
 341                 framesize = wlen * channels;
 342
 343         /* Set FS period and length in terms of bit clock periods */
 344         switch (format) {
 345         case SND_SOC_DAIFMT_I2S:
 346                 regs->srgr2     |= FPER(framesize - 1);
 347                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 348                 break;
 349         case SND_SOC_DAIFMT_DSP_A:
 350         case SND_SOC_DAIFMT_DSP_B:
 351                 regs->srgr2     |= FPER(framesize - 1);
 352                 regs->srgr1     |= FWID(0);
 353                 break;
 354         }
 355
 356         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 357         mcbsp_data->configured = 1;
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 364  * cache is initialized here
 365  */
 366 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 367                                       unsigned int fmt)
 368 {
 369         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 370         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 371         unsigned int temp_fmt = fmt;
 372
 373         if (mcbsp_data->configured)
 374                 return 0;
 375
 376         mcbsp_data->fmt = fmt;
 377         memset(regs, 0, sizeof(*regs));
 378         /* Generic McBSP register settings */
 379         regs->spcr2     |= XINTM(3) | FREE;
 380         regs->spcr1     |= RINTM(3);
 381         /* RFIG and XFIG are not defined in 34xx */
 382         if (!cpu_is_omap34xx()) {
 383                 regs->rcr2      |= RFIG;
 384                 regs->xcr2      |= XFIG;
 385         }
 386         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 387                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 388                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 389         }
 390
 391         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 392         case SND_SOC_DAIFMT_I2S:
 393                 /* 1-bit data delay */
 394                 regs->rcr2      |= RDATDLY(1);
 395                 regs->xcr2      |= XDATDLY(1);
 396                 break;
 397         case SND_SOC_DAIFMT_DSP_A:
 398                 /* 1-bit data delay */
 399                 regs->rcr2      |= RDATDLY(1);
 400                 regs->xcr2      |= XDATDLY(1);
 401                 /* Invert FS polarity configuration */
 402                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 403                 break;
 404         case SND_SOC_DAIFMT_DSP_B:
 405                 /* 0-bit data delay */
 406                 regs->rcr2      |= RDATDLY(0);
 407                 regs->xcr2      |= XDATDLY(0);
 408                 /* Invert FS polarity configuration */
 409                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 410                 break;
 411         default:
 412                 /* Unsupported data format */
 413                 return -EINVAL;
 414         }
 415
 416         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 417         case SND_SOC_DAIFMT_CBS_CFS:
 418                 /* McBSP master. Set FS and bit clocks as outputs */
 419                 regs->pcr0      |= FSXM | FSRM |
 420                                    CLKXM | CLKRM;
 421                 /* Sample rate generator drives the FS */
 422                 regs->srgr2     |= FSGM;
 423                 break;
 424         case SND_SOC_DAIFMT_CBM_CFM:
 425                 /* McBSP slave */
 426                 break;
 427         default:
 428                 /* Unsupported master/slave configuration */
 429                 return -EINVAL;
 430         }
 431
 432         /* Set bit clock (CLKX/CLKR) and FS polarities */
 433         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 434         case SND_SOC_DAIFMT_NB_NF:
 435                 /*
 436                  * Normal BCLK + FS.
 437                  * FS active low. TX data driven on falling edge of bit clock
 438                  * and RX data sampled on rising edge of bit clock.
 439                  */
 440                 regs->pcr0      |= FSXP | FSRP |
 441                                    CLKXP | CLKRP;
 442                 break;
 443         case SND_SOC_DAIFMT_NB_IF:
 444                 regs->pcr0      |= CLKXP | CLKRP;
 445                 break;
 446         case SND_SOC_DAIFMT_IB_NF:
 447                 regs->pcr0      |= FSXP | FSRP;
 448                 break;
 449         case SND_SOC_DAIFMT_IB_IF:
 450                 break;
 451         default:
 452                 return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 459                                      int div_id, int div)
 460 {
 461         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 462         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 463
 464         if (div_id != OMAP_MCBSP_CLKGDV)
 465                 return -ENODEV;
 466
 467         mcbsp_data->clk_div = div;
 468         regs->srgr1     |= CLKGDV(div - 1);
 469
 470         return 0;
 471 }
 472
 473 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 474                                        int clk_id)
 475 {
 476         int sel_bit;
 477         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 478
 479         if (cpu_class_is_omap1()) {
 480                 /* OMAP1's can use only external source clock */
 481                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 482                         return -EINVAL;
 483                 else
 484                         return 0;
 485         }
 486
 487         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 488                 return -EINVAL;
 489
 490         if (cpu_is_omap343x())
 491                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 492
 493         switch (mcbsp_data->bus_id) {
 494         case 0:
 495                 reg = OMAP2_CONTROL_DEVCONF0;
 496                 sel_bit = 2;
 497                 break;
 498         case 1:
 499                 reg = OMAP2_CONTROL_DEVCONF0;
 500                 sel_bit = 6;
 501                 break;
 502         case 2:
 503                 reg = reg_devconf1;
 504                 sel_bit = 0;
 505                 break;
 506         case 3:
 507                 reg = reg_devconf1;
 508                 sel_bit = 2;
 509                 break;
 510         case 4:
 511                 reg = reg_devconf1;
 512                 sel_bit = 4;
 513                 break;
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 519                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 520         else
 521                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 522
 523         return 0;
 524 }
 525
 526 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
 527                                        int clk_id)
 528 {
 529         int sel_bit, set = 0;
 530         u16 reg = OMAP2_CONTROL_DEVCONF0;
 531
 532         if (cpu_class_is_omap1())
 533                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
 534         if (mcbsp_data->bus_id != 0)
 535                 return -EINVAL;
 536
 537         switch (clk_id) {
 538         case OMAP_MCBSP_CLKR_SRC_CLKX:
 539                 set = 1;
 540         case OMAP_MCBSP_CLKR_SRC_CLKR:
 541                 sel_bit = 3;
 542                 break;
 543         case OMAP_MCBSP_FSR_SRC_FSX:
 544                 set = 1;
 545         case OMAP_MCBSP_FSR_SRC_FSR:
 546                 sel_bit = 4;
 547                 break;
 548         default:
 549                 return -EINVAL;
 550         }
 551
 552         if (set)
 553                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 554         else
 555                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 556
 557         return 0;
 558 }
 559
 560 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 561                                          int clk_id, unsigned int freq,
 562                                          int dir)
 563 {
 564         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 565         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 566         int err = 0;
 567
 568         mcbsp_data->in_freq = freq;
 569
 570         switch (clk_id) {
 571         case OMAP_MCBSP_SYSCLK_CLK:
 572                 regs->srgr2     |= CLKSM;
 573                 break;
 574         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 575         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 576                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 577                 break;
 578
 579         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 580                 regs->srgr2     |= CLKSM;
 581         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 582                 regs->pcr0      |= SCLKME;
 583                 break;
 584
 585         case OMAP_MCBSP_CLKR_SRC_CLKR:
 586         case OMAP_MCBSP_CLKR_SRC_CLKX:
 587         case OMAP_MCBSP_FSR_SRC_FSR:
 588         case OMAP_MCBSP_FSR_SRC_FSX:
 589                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
 590                 break;
 591         default:
 592                 err = -ENODEV;
 593         }
 594
 595         return err;
 596 }
 597
 598 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 599         .startup        = omap_mcbsp_dai_startup,
 600         .shutdown       = omap_mcbsp_dai_shutdown,
 601         .trigger        = omap_mcbsp_dai_trigger,
 602         .hw_params      = omap_mcbsp_dai_hw_params,
 603         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 604         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 605         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 606 };
 607
 608 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 609 {                                                               \
 610         .name = "omap-mcbsp-dai-"#link_id,                      \
 611         .id = (link_id),                                        \
 612         .playback = {                                           \
 613                 .channels_min = 1,                              \
 614                 .channels_max = 16,                             \
 615                 .rates = OMAP_MCBSP_RATES,                      \
 616                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 617         },                                                      \
 618         .capture = {                                            \
 619                 .channels_min = 1,                              \
 620                 .channels_max = 16,                             \
 621                 .rates = OMAP_MCBSP_RATES,                      \
 622                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 623         },                                                      \
 624         .ops = &omap_mcbsp_dai_ops,                             \
 625         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 626 }
 627
 628 struct snd_soc_dai omap_mcbsp_dai[] = {
 629         OMAP_MCBSP_DAI_BUILDER(0),
 630         OMAP_MCBSP_DAI_BUILDER(1),
 631 #if NUM_LINKS >= 3
 632         OMAP_MCBSP_DAI_BUILDER(2),
 633 #endif
 634 #if NUM_LINKS == 5
 635         OMAP_MCBSP_DAI_BUILDER(3),
 636         OMAP_MCBSP_DAI_BUILDER(4),
 637 #endif
 638 };
 639
 640 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 641
 642 static int __init snd_omap_mcbsp_init(void)
 643 {
 644         return snd_soc_register_dais(omap_mcbsp_dai,
 645                                      ARRAY_SIZE(omap_mcbsp_dai));
 646 }
 647 module_init(snd_omap_mcbsp_init);
 648
 649 static void __exit snd_omap_mcbsp_exit(void)
 650 {
 651         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 652 }
 653 module_exit(snd_omap_mcbsp_exit);
 654
 655 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 656 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 657 MODULE_LICENSE("GPL");