2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jhnikula@gmail.com>
7 * Peter Ujfalusi <peter.ujfalusi@nokia.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
34 #include <plat/control.h>
36 #include <plat/mcbsp.h>
37 #include "omap-mcbsp.h"
40 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
43 xhandler_get, xhandler_put) \
44 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
45 .info = omap_mcbsp_st_info_volsw, \
46 .get = xhandler_get, .put = xhandler_put, \
47 .private_value = (unsigned long) &(struct soc_mixer_control) \
48 {.min = xmin, .max = xmax} }
50 struct omap_mcbsp_data {
52 struct omap_mcbsp_reg_cfg regs;
55 * Flags indicating is the bus already activated and configured by
64 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
66 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
69 * Stream DMA parameters. DMA request line and port address are set runtime
70 * since they are different between OMAP1 and later OMAPs
72 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
74 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
75 static const int omap1_dma_reqs[][2] = {
76 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
77 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
78 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
80 static const unsigned long omap1_mcbsp_port[][2] = {
81 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
82 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
83 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
84 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
85 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
86 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
89 static const int omap1_dma_reqs[][2] = {};
90 static const unsigned long omap1_mcbsp_port[][2] = {};
93 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
94 static const int omap24xx_dma_reqs[][2] = {
95 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
96 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
97 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
98 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
99 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
100 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
104 static const int omap24xx_dma_reqs[][2] = {};
107 #if defined(CONFIG_ARCH_OMAP2420)
108 static const unsigned long omap2420_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
115 static const unsigned long omap2420_mcbsp_port[][2] = {};
118 #if defined(CONFIG_ARCH_OMAP2430)
119 static const unsigned long omap2430_mcbsp_port[][2] = {
120 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
121 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
122 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
123 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
124 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
125 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
126 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
132 static const unsigned long omap2430_mcbsp_port[][2] = {};
135 #if defined(CONFIG_ARCH_OMAP3)
136 static const unsigned long omap34xx_mcbsp_port[][2] = {
137 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
138 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
139 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
140 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
141 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
142 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
143 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
144 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
145 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
146 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
149 static const unsigned long omap34xx_mcbsp_port[][2] = {};
152 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
154 struct snd_soc_pcm_runtime *rtd = substream->private_data;
155 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
156 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
157 int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
160 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
161 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
162 samples = snd_pcm_lib_period_bytes(substream) >> 1;
166 /* Configure McBSP internal buffer usage */
167 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
168 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
170 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
173 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
174 struct snd_soc_dai *dai)
176 struct snd_soc_pcm_runtime *rtd = substream->private_data;
177 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
178 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
179 int bus_id = mcbsp_data->bus_id;
182 if (!cpu_dai->active)
183 err = omap_mcbsp_request(bus_id);
185 if (cpu_is_omap343x()) {
186 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
190 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
191 * Set constraint for minimum buffer size to the same than FIFO
192 * size in order to avoid underruns in playback startup because
193 * HW is keeping the DMA request active until FIFO is filled.
196 snd_pcm_hw_constraint_minmax(substream->runtime,
197 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
200 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
201 max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
203 max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
208 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
209 snd_pcm_hw_constraint_minmax(substream->runtime,
210 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
217 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
218 struct snd_soc_dai *dai)
220 struct snd_soc_pcm_runtime *rtd = substream->private_data;
221 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
222 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
224 if (!cpu_dai->active) {
225 omap_mcbsp_free(mcbsp_data->bus_id);
226 mcbsp_data->configured = 0;
230 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
231 struct snd_soc_dai *dai)
233 struct snd_soc_pcm_runtime *rtd = substream->private_data;
234 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
235 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
236 int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
239 case SNDRV_PCM_TRIGGER_START:
240 case SNDRV_PCM_TRIGGER_RESUME:
241 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
242 mcbsp_data->active++;
243 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
246 case SNDRV_PCM_TRIGGER_STOP:
247 case SNDRV_PCM_TRIGGER_SUSPEND:
248 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
249 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
250 mcbsp_data->active--;
259 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
260 struct snd_pcm_hw_params *params,
261 struct snd_soc_dai *dai)
263 struct snd_soc_pcm_runtime *rtd = substream->private_data;
264 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
265 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
266 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
267 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
268 int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
270 unsigned int format, div, framesize, master;
272 if (cpu_class_is_omap1()) {
273 dma = omap1_dma_reqs[bus_id][substream->stream];
274 port = omap1_mcbsp_port[bus_id][substream->stream];
275 } else if (cpu_is_omap2420()) {
276 dma = omap24xx_dma_reqs[bus_id][substream->stream];
277 port = omap2420_mcbsp_port[bus_id][substream->stream];
278 } else if (cpu_is_omap2430()) {
279 dma = omap24xx_dma_reqs[bus_id][substream->stream];
280 port = omap2430_mcbsp_port[bus_id][substream->stream];
281 } else if (cpu_is_omap343x()) {
282 dma = omap24xx_dma_reqs[bus_id][substream->stream];
283 port = omap34xx_mcbsp_port[bus_id][substream->stream];
284 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
285 omap_mcbsp_set_threshold;
286 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
287 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
288 MCBSP_DMA_MODE_THRESHOLD)
289 sync_mode = OMAP_DMA_SYNC_FRAME;
293 omap_mcbsp_dai_dma_params[id][substream->stream].name =
294 substream->stream ? "Audio Capture" : "Audio Playback";
295 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
296 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
297 omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
298 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
299 OMAP_DMA_DATA_TYPE_S16;
301 snd_soc_dai_set_dma_data(cpu_dai, substream,
302 &omap_mcbsp_dai_dma_params[id][substream->stream]);
304 if (mcbsp_data->configured) {
305 /* McBSP already configured by another stream */
309 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
310 wpf = channels = params_channels(params);
311 if (channels == 2 && format == SND_SOC_DAIFMT_I2S) {
312 /* Use dual-phase frames */
313 regs->rcr2 |= RPHASE;
314 regs->xcr2 |= XPHASE;
315 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
317 regs->rcr2 |= RFRLEN2(wpf - 1);
318 regs->xcr2 |= XFRLEN2(wpf - 1);
321 regs->rcr1 |= RFRLEN1(wpf - 1);
322 regs->xcr1 |= XFRLEN1(wpf - 1);
324 switch (params_format(params)) {
325 case SNDRV_PCM_FORMAT_S16_LE:
326 /* Set word lengths */
328 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
329 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
330 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
331 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
334 /* Unsupported PCM format */
338 /* In McBSP master modes, FRAME (i.e. sample rate) is generated
339 * by _counting_ BCLKs. Calculate frame size in BCLKs */
340 master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
341 if (master == SND_SOC_DAIFMT_CBS_CFS) {
342 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
343 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
345 if (framesize < wlen * channels) {
346 printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
347 "channels\n", __func__);
351 framesize = wlen * channels;
353 /* Set FS period and length in terms of bit clock periods */
355 case SND_SOC_DAIFMT_I2S:
356 regs->srgr2 |= FPER(framesize - 1);
357 regs->srgr1 |= FWID((framesize >> 1) - 1);
359 case SND_SOC_DAIFMT_DSP_A:
360 case SND_SOC_DAIFMT_DSP_B:
361 regs->srgr2 |= FPER(framesize - 1);
362 regs->srgr1 |= FWID(0);
366 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
367 mcbsp_data->configured = 1;
373 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
374 * cache is initialized here
376 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
379 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
380 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
381 unsigned int temp_fmt = fmt;
383 if (mcbsp_data->configured)
386 mcbsp_data->fmt = fmt;
387 memset(regs, 0, sizeof(*regs));
388 /* Generic McBSP register settings */
389 regs->spcr2 |= XINTM(3) | FREE;
390 regs->spcr1 |= RINTM(3);
391 /* RFIG and XFIG are not defined in 34xx */
392 if (!cpu_is_omap34xx()) {
396 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
397 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
398 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
401 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
402 case SND_SOC_DAIFMT_I2S:
403 /* 1-bit data delay */
404 regs->rcr2 |= RDATDLY(1);
405 regs->xcr2 |= XDATDLY(1);
407 case SND_SOC_DAIFMT_DSP_A:
408 /* 1-bit data delay */
409 regs->rcr2 |= RDATDLY(1);
410 regs->xcr2 |= XDATDLY(1);
411 /* Invert FS polarity configuration */
412 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
414 case SND_SOC_DAIFMT_DSP_B:
415 /* 0-bit data delay */
416 regs->rcr2 |= RDATDLY(0);
417 regs->xcr2 |= XDATDLY(0);
418 /* Invert FS polarity configuration */
419 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
422 /* Unsupported data format */
426 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
427 case SND_SOC_DAIFMT_CBS_CFS:
428 /* McBSP master. Set FS and bit clocks as outputs */
429 regs->pcr0 |= FSXM | FSRM |
431 /* Sample rate generator drives the FS */
434 case SND_SOC_DAIFMT_CBM_CFM:
438 /* Unsupported master/slave configuration */
442 /* Set bit clock (CLKX/CLKR) and FS polarities */
443 switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
444 case SND_SOC_DAIFMT_NB_NF:
447 * FS active low. TX data driven on falling edge of bit clock
448 * and RX data sampled on rising edge of bit clock.
450 regs->pcr0 |= FSXP | FSRP |
453 case SND_SOC_DAIFMT_NB_IF:
454 regs->pcr0 |= CLKXP | CLKRP;
456 case SND_SOC_DAIFMT_IB_NF:
457 regs->pcr0 |= FSXP | FSRP;
459 case SND_SOC_DAIFMT_IB_IF:
468 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
471 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
472 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
474 if (div_id != OMAP_MCBSP_CLKGDV)
477 mcbsp_data->clk_div = div;
478 regs->srgr1 |= CLKGDV(div - 1);
483 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
487 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
489 if (cpu_class_is_omap1()) {
490 /* OMAP1's can use only external source clock */
491 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
497 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
500 if (cpu_is_omap343x())
501 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
503 switch (mcbsp_data->bus_id) {
505 reg = OMAP2_CONTROL_DEVCONF0;
509 reg = OMAP2_CONTROL_DEVCONF0;
528 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
529 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
531 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
536 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
539 int sel_bit, set = 0;
540 u16 reg = OMAP2_CONTROL_DEVCONF0;
542 if (cpu_class_is_omap1())
543 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
544 if (mcbsp_data->bus_id != 0)
548 case OMAP_MCBSP_CLKR_SRC_CLKX:
550 case OMAP_MCBSP_CLKR_SRC_CLKR:
553 case OMAP_MCBSP_FSR_SRC_FSX:
555 case OMAP_MCBSP_FSR_SRC_FSR:
563 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
565 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
570 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
571 int clk_id, unsigned int freq,
574 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
575 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
578 mcbsp_data->in_freq = freq;
581 case OMAP_MCBSP_SYSCLK_CLK:
582 regs->srgr2 |= CLKSM;
584 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
585 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
586 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
589 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
590 regs->srgr2 |= CLKSM;
591 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
592 regs->pcr0 |= SCLKME;
595 case OMAP_MCBSP_CLKR_SRC_CLKR:
596 case OMAP_MCBSP_CLKR_SRC_CLKX:
597 case OMAP_MCBSP_FSR_SRC_FSR:
598 case OMAP_MCBSP_FSR_SRC_FSX:
599 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
608 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
609 .startup = omap_mcbsp_dai_startup,
610 .shutdown = omap_mcbsp_dai_shutdown,
611 .trigger = omap_mcbsp_dai_trigger,
612 .hw_params = omap_mcbsp_dai_hw_params,
613 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
614 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
615 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
618 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
620 .name = "omap-mcbsp-dai-"#link_id, \
624 .channels_max = 16, \
625 .rates = OMAP_MCBSP_RATES, \
626 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
630 .channels_max = 16, \
631 .rates = OMAP_MCBSP_RATES, \
632 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
634 .ops = &omap_mcbsp_dai_ops, \
635 .private_data = &mcbsp_data[(link_id)].bus_id, \
638 struct snd_soc_dai omap_mcbsp_dai[] = {
639 OMAP_MCBSP_DAI_BUILDER(0),
640 OMAP_MCBSP_DAI_BUILDER(1),
642 OMAP_MCBSP_DAI_BUILDER(2),
645 OMAP_MCBSP_DAI_BUILDER(3),
646 OMAP_MCBSP_DAI_BUILDER(4),
650 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
652 int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
653 struct snd_ctl_elem_info *uinfo)
655 struct soc_mixer_control *mc =
656 (struct soc_mixer_control *)kcontrol->private_value;
660 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
662 uinfo->value.integer.min = min;
663 uinfo->value.integer.max = max;
667 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel) \
669 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
670 struct snd_ctl_elem_value *uc) \
672 struct soc_mixer_control *mc = \
673 (struct soc_mixer_control *)kc->private_value; \
676 int val = uc->value.integer.value[0]; \
678 if (val < min || val > max) \
681 /* OMAP McBSP implementation uses index values 0..4 */ \
682 return omap_st_set_chgain((id)-1, channel, val); \
685 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel) \
687 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
688 struct snd_ctl_elem_value *uc) \
692 if (omap_st_get_chgain((id)-1, channel, &chgain)) \
695 uc->value.integer.value[0] = chgain; \
699 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
700 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
701 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
702 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
703 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
704 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
705 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
706 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
708 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
709 struct snd_ctl_elem_value *ucontrol)
711 struct soc_mixer_control *mc =
712 (struct soc_mixer_control *)kcontrol->private_value;
713 u8 value = ucontrol->value.integer.value[0];
715 if (value == omap_st_is_enabled(mc->reg))
719 omap_st_enable(mc->reg);
721 omap_st_disable(mc->reg);
726 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
727 struct snd_ctl_elem_value *ucontrol)
729 struct soc_mixer_control *mc =
730 (struct soc_mixer_control *)kcontrol->private_value;
732 ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
736 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
737 SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
738 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
739 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
741 omap_mcbsp2_get_st_ch0_volume,
742 omap_mcbsp2_set_st_ch0_volume),
743 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
745 omap_mcbsp2_get_st_ch1_volume,
746 omap_mcbsp2_set_st_ch1_volume),
749 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
750 SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
751 omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
752 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
754 omap_mcbsp3_get_st_ch0_volume,
755 omap_mcbsp3_set_st_ch0_volume),
756 OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
758 omap_mcbsp3_get_st_ch1_volume,
759 omap_mcbsp3_set_st_ch1_volume),
762 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
764 if (!cpu_is_omap34xx())
768 case 1: /* McBSP 2 */
769 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
770 ARRAY_SIZE(omap_mcbsp2_st_controls));
771 case 2: /* McBSP 3 */
772 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
773 ARRAY_SIZE(omap_mcbsp3_st_controls));
780 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
782 static int __init snd_omap_mcbsp_init(void)
784 return snd_soc_register_dais(omap_mcbsp_dai,
785 ARRAY_SIZE(omap_mcbsp_dai));
787 module_init(snd_omap_mcbsp_init);
789 static void __exit snd_omap_mcbsp_exit(void)
791 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
793 module_exit(snd_omap_mcbsp_exit);
795 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
796 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
797 MODULE_LICENSE("GPL");