sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/control.h>
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  43         xhandler_get, xhandler_put) \
  44 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  45         .info = omap_mcbsp_st_info_volsw, \
  46         .get = xhandler_get, .put = xhandler_put, \
  47         .private_value = (unsigned long) &(struct soc_mixer_control) \
  48         {.min = xmin, .max = xmax} }
  49
  50 struct omap_mcbsp_data {
  51         unsigned int                    bus_id;
  52         struct omap_mcbsp_reg_cfg       regs;
  53         unsigned int                    fmt;
  54         /*
  55          * Flags indicating is the bus already activated and configured by
  56          * another substream
  57          */
  58         int                             active;
  59         int                             configured;
  60         unsigned int                    in_freq;
  61         int                             clk_div;
  62         int                             wlen;
  63 };
  64
  65 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  66
  67 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  68
  69 /*
  70  * Stream DMA parameters. DMA request line and port address are set runtime
  71  * since they are different between OMAP1 and later OMAPs
  72  */
  73 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  74
  75 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  76 static const int omap1_dma_reqs[][2] = {
  77         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  78         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  79         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  80 };
  81 static const unsigned long omap1_mcbsp_port[][2] = {
  82         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  83           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  84         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  85           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  86         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  87           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  88 };
  89 #else
  90 static const int omap1_dma_reqs[][2] = {};
  91 static const unsigned long omap1_mcbsp_port[][2] = {};
  92 #endif
  93
  94 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  95 static const int omap24xx_dma_reqs[][2] = {
  96         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  97         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  98 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  99         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
 100         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
 101         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
 102 #endif
 103 };
 104 #else
 105 static const int omap24xx_dma_reqs[][2] = {};
 106 #endif
 107
 108 #if defined(CONFIG_ARCH_OMAP2420)
 109 static const unsigned long omap2420_mcbsp_port[][2] = {
 110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 114 };
 115 #else
 116 static const unsigned long omap2420_mcbsp_port[][2] = {};
 117 #endif
 118
 119 #if defined(CONFIG_ARCH_OMAP2430)
 120 static const unsigned long omap2430_mcbsp_port[][2] = {
 121         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 122           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 123         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 124           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 125         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 126           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 127         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 129         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 131 };
 132 #else
 133 static const unsigned long omap2430_mcbsp_port[][2] = {};
 134 #endif
 135
 136 #if defined(CONFIG_ARCH_OMAP3)
 137 static const unsigned long omap34xx_mcbsp_port[][2] = {
 138         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 139           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 140         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 141           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 142         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 143           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 144         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 145           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 146         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 147           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 148 };
 149 #else
 150 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 151 #endif
 152
 153 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 154 {
 155         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 156         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 157         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 158         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 159         int words;
 160
 161         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 162         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 163                 /* The FIFO size depends on the McBSP word configuration */
 164                 words = snd_pcm_lib_period_bytes(substream) /
 165                                                         (mcbsp_data->wlen / 8);
 166         else
 167                 words = 1;
 168
 169         /* Configure McBSP internal buffer usage */
 170         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 171                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
 172         else
 173                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
 174 }
 175
 176 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 177                                     struct snd_pcm_hw_rule *rule)
 178 {
 179         struct snd_interval *buffer_size = hw_param_interval(params,
 180                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 181         struct snd_interval *channels = hw_param_interval(params,
 182                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 183         struct omap_mcbsp_data *mcbsp_data = rule->private;
 184         struct snd_interval frames;
 185         int size;
 186
 187         snd_interval_any(&frames);
 188         size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
 189
 190         frames.min = size / channels->min;
 191         frames.integer = 1;
 192         return snd_interval_refine(buffer_size, &frames);
 193 }
 194
 195 static int omap_mcbsp_hwrule_max_periodsize(struct snd_pcm_hw_params *params,
 196                                     struct snd_pcm_hw_rule *rule)
 197 {
 198         struct snd_interval *period_size = hw_param_interval(params,
 199                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
 200         struct snd_interval *channels = hw_param_interval(params,
 201                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 202         struct snd_pcm_substream *substream = rule->private;
 203         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 204         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 205         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 206         struct snd_interval frames;
 207         int size;
 208
 209         snd_interval_any(&frames);
 210         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 211                 size = omap_mcbsp_get_max_tx_threshold(mcbsp_data->bus_id);
 212         else
 213                 size = omap_mcbsp_get_max_rx_threshold(mcbsp_data->bus_id);
 214
 215         frames.max = size / channels->min;
 216         frames.integer = 1;
 217         return snd_interval_refine(period_size, &frames);
 218 }
 219
 220 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 221                                   struct snd_soc_dai *dai)
 222 {
 223         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 224         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 225         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 226         int bus_id = mcbsp_data->bus_id;
 227         int err = 0;
 228
 229         if (!cpu_dai->active)
 230                 err = omap_mcbsp_request(bus_id);
 231
 232         /*
 233          * OMAP3 McBSP FIFO is word structured.
 234          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 235          * McBSP1,3,4,5 has 128 word long buffer
 236          * This means that the size of the FIFO depends on the sample format.
 237          * For example on McBSP3:
 238          * 16bit samples: size is 128 * 2 = 256 bytes
 239          * 32bit samples: size is 128 * 4 = 512 bytes
 240          * It is simpler to place constraint for buffer and period based on
 241          * channels.
 242          * McBSP3 as example again (16 or 32 bit samples):
 243          * 1 channel (mono): size is 128 frames (128 words)
 244          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 245          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 246          */
 247         if (cpu_is_omap343x()) {
 248                 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
 249
 250                 /*
 251                 * The first rule is for the buffer size, we should not allow
 252                 * smaller buffer than the FIFO size to avoid underruns
 253                 */
 254                 snd_pcm_hw_rule_add(substream->runtime, 0,
 255                                     SNDRV_PCM_HW_PARAM_CHANNELS,
 256                                     omap_mcbsp_hwrule_min_buffersize,
 257                                     mcbsp_data,
 258                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 259
 260                 /*
 261                  * In case of threshold mode, the rule will ensure, that the
 262                  * period size is not bigger than the maximum allowed threshold
 263                  * value.
 264                  */
 265                 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 266                         snd_pcm_hw_rule_add(substream->runtime, 0,
 267                                             SNDRV_PCM_HW_PARAM_CHANNELS,
 268                                             omap_mcbsp_hwrule_max_periodsize,
 269                                             substream,
 270                                             SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
 271         }
 272
 273         return err;
 274 }
 275
 276 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 277                                     struct snd_soc_dai *dai)
 278 {
 279         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 280         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 281         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 282
 283         if (!cpu_dai->active) {
 284                 omap_mcbsp_free(mcbsp_data->bus_id);
 285                 mcbsp_data->configured = 0;
 286         }
 287 }
 288
 289 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 290                                   struct snd_soc_dai *dai)
 291 {
 292         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 293         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 294         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 295         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 296
 297         switch (cmd) {
 298         case SNDRV_PCM_TRIGGER_START:
 299         case SNDRV_PCM_TRIGGER_RESUME:
 300         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 301                 mcbsp_data->active++;
 302                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 303                 break;
 304
 305         case SNDRV_PCM_TRIGGER_STOP:
 306         case SNDRV_PCM_TRIGGER_SUSPEND:
 307         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 308                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 309                 mcbsp_data->active--;
 310                 break;
 311         default:
 312                 err = -EINVAL;
 313         }
 314
 315         return err;
 316 }
 317
 318 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 319                         struct snd_pcm_substream *substream,
 320                         struct snd_soc_dai *dai)
 321 {
 322         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 323         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 324         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 325         u16 fifo_use;
 326         snd_pcm_sframes_t delay;
 327
 328         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 329                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
 330         else
 331                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
 332
 333         /*
 334          * Divide the used locations with the channel count to get the
 335          * FIFO usage in samples (don't care about partial samples in the
 336          * buffer).
 337          */
 338         delay = fifo_use / substream->runtime->channels;
 339
 340         return delay;
 341 }
 342
 343 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 344                                     struct snd_pcm_hw_params *params,
 345                                     struct snd_soc_dai *dai)
 346 {
 347         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 348         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 349         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 350         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 351         struct omap_pcm_dma_data *dma_data;
 352         int dma, bus_id = mcbsp_data->bus_id;
 353         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 354         unsigned long port;
 355         unsigned int format, div, framesize, master;
 356
 357         dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream];
 358         if (cpu_class_is_omap1()) {
 359                 dma = omap1_dma_reqs[bus_id][substream->stream];
 360                 port = omap1_mcbsp_port[bus_id][substream->stream];
 361         } else if (cpu_is_omap2420()) {
 362                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 363                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 364         } else if (cpu_is_omap2430()) {
 365                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 366                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 367         } else if (cpu_is_omap343x()) {
 368                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 369                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 370                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 371                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 372                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 373                                                 MCBSP_DMA_MODE_THRESHOLD)
 374                         sync_mode = OMAP_DMA_SYNC_FRAME;
 375         } else {
 376                 return -ENODEV;
 377         }
 378         dma_data->name = substream->stream ? "Audio Capture" : "Audio Playback";
 379         dma_data->dma_req = dma;
 380         dma_data->port_addr = port;
 381         dma_data->sync_mode = sync_mode;
 382         switch (params_format(params)) {
 383         case SNDRV_PCM_FORMAT_S16_LE:
 384                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 385                 break;
 386         case SNDRV_PCM_FORMAT_S32_LE:
 387                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 388                 break;
 389         default:
 390                 return -EINVAL;
 391         }
 392
 393         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 394
 395         if (mcbsp_data->configured) {
 396                 /* McBSP already configured by another stream */
 397                 return 0;
 398         }
 399
 400         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 401         wpf = channels = params_channels(params);
 402         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 403                               format == SND_SOC_DAIFMT_LEFT_J)) {
 404                 /* Use dual-phase frames */
 405                 regs->rcr2      |= RPHASE;
 406                 regs->xcr2      |= XPHASE;
 407                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 408                 wpf--;
 409                 regs->rcr2      |= RFRLEN2(wpf - 1);
 410                 regs->xcr2      |= XFRLEN2(wpf - 1);
 411         }
 412
 413         regs->rcr1      |= RFRLEN1(wpf - 1);
 414         regs->xcr1      |= XFRLEN1(wpf - 1);
 415
 416         switch (params_format(params)) {
 417         case SNDRV_PCM_FORMAT_S16_LE:
 418                 /* Set word lengths */
 419                 wlen = 16;
 420                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 421                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 422                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 423                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 424                 break;
 425         case SNDRV_PCM_FORMAT_S32_LE:
 426                 /* Set word lengths */
 427                 wlen = 32;
 428                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 429                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 430                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 431                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 432                 break;
 433         default:
 434                 /* Unsupported PCM format */
 435                 return -EINVAL;
 436         }
 437
 438         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 439          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 440         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 441         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 442                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 443                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 444
 445                 if (framesize < wlen * channels) {
 446                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 447                                         "channels\n", __func__);
 448                         return -EINVAL;
 449                 }
 450         } else
 451                 framesize = wlen * channels;
 452
 453         /* Set FS period and length in terms of bit clock periods */
 454         switch (format) {
 455         case SND_SOC_DAIFMT_I2S:
 456         case SND_SOC_DAIFMT_LEFT_J:
 457                 regs->srgr2     |= FPER(framesize - 1);
 458                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 459                 break;
 460         case SND_SOC_DAIFMT_DSP_A:
 461         case SND_SOC_DAIFMT_DSP_B:
 462                 regs->srgr2     |= FPER(framesize - 1);
 463                 regs->srgr1     |= FWID(0);
 464                 break;
 465         }
 466
 467         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 468         mcbsp_data->wlen = wlen;
 469         mcbsp_data->configured = 1;
 470
 471         return 0;
 472 }
 473
 474 /*
 475  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 476  * cache is initialized here
 477  */
 478 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 479                                       unsigned int fmt)
 480 {
 481         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 482         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 483         unsigned int temp_fmt = fmt;
 484
 485         if (mcbsp_data->configured)
 486                 return 0;
 487
 488         mcbsp_data->fmt = fmt;
 489         memset(regs, 0, sizeof(*regs));
 490         /* Generic McBSP register settings */
 491         regs->spcr2     |= XINTM(3) | FREE;
 492         regs->spcr1     |= RINTM(3);
 493         /* RFIG and XFIG are not defined in 34xx */
 494         if (!cpu_is_omap34xx()) {
 495                 regs->rcr2      |= RFIG;
 496                 regs->xcr2      |= XFIG;
 497         }
 498         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 499                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 500                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 501         }
 502
 503         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 504         case SND_SOC_DAIFMT_I2S:
 505                 /* 1-bit data delay */
 506                 regs->rcr2      |= RDATDLY(1);
 507                 regs->xcr2      |= XDATDLY(1);
 508                 break;
 509         case SND_SOC_DAIFMT_LEFT_J:
 510                 /* 0-bit data delay */
 511                 regs->rcr2      |= RDATDLY(0);
 512                 regs->xcr2      |= XDATDLY(0);
 513                 regs->spcr1     |= RJUST(2);
 514                 /* Invert FS polarity configuration */
 515                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 516                 break;
 517         case SND_SOC_DAIFMT_DSP_A:
 518                 /* 1-bit data delay */
 519                 regs->rcr2      |= RDATDLY(1);
 520                 regs->xcr2      |= XDATDLY(1);
 521                 /* Invert FS polarity configuration */
 522                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 523                 break;
 524         case SND_SOC_DAIFMT_DSP_B:
 525                 /* 0-bit data delay */
 526                 regs->rcr2      |= RDATDLY(0);
 527                 regs->xcr2      |= XDATDLY(0);
 528                 /* Invert FS polarity configuration */
 529                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 530                 break;
 531         default:
 532                 /* Unsupported data format */
 533                 return -EINVAL;
 534         }
 535
 536         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 537         case SND_SOC_DAIFMT_CBS_CFS:
 538                 /* McBSP master. Set FS and bit clocks as outputs */
 539                 regs->pcr0      |= FSXM | FSRM |
 540                                    CLKXM | CLKRM;
 541                 /* Sample rate generator drives the FS */
 542                 regs->srgr2     |= FSGM;
 543                 break;
 544         case SND_SOC_DAIFMT_CBM_CFM:
 545                 /* McBSP slave */
 546                 break;
 547         default:
 548                 /* Unsupported master/slave configuration */
 549                 return -EINVAL;
 550         }
 551
 552         /* Set bit clock (CLKX/CLKR) and FS polarities */
 553         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 554         case SND_SOC_DAIFMT_NB_NF:
 555                 /*
 556                  * Normal BCLK + FS.
 557                  * FS active low. TX data driven on falling edge of bit clock
 558                  * and RX data sampled on rising edge of bit clock.
 559                  */
 560                 regs->pcr0      |= FSXP | FSRP |
 561                                    CLKXP | CLKRP;
 562                 break;
 563         case SND_SOC_DAIFMT_NB_IF:
 564                 regs->pcr0      |= CLKXP | CLKRP;
 565                 break;
 566         case SND_SOC_DAIFMT_IB_NF:
 567                 regs->pcr0      |= FSXP | FSRP;
 568                 break;
 569         case SND_SOC_DAIFMT_IB_IF:
 570                 break;
 571         default:
 572                 return -EINVAL;
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 579                                      int div_id, int div)
 580 {
 581         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 582         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 583
 584         if (div_id != OMAP_MCBSP_CLKGDV)
 585                 return -ENODEV;
 586
 587         mcbsp_data->clk_div = div;
 588         regs->srgr1     |= CLKGDV(div - 1);
 589
 590         return 0;
 591 }
 592
 593 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 594                                        int clk_id)
 595 {
 596         int sel_bit;
 597         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 598
 599         if (cpu_class_is_omap1()) {
 600                 /* OMAP1's can use only external source clock */
 601                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 602                         return -EINVAL;
 603                 else
 604                         return 0;
 605         }
 606
 607         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 608                 return -EINVAL;
 609
 610         if (cpu_is_omap343x())
 611                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 612
 613         switch (mcbsp_data->bus_id) {
 614         case 0:
 615                 reg = OMAP2_CONTROL_DEVCONF0;
 616                 sel_bit = 2;
 617                 break;
 618         case 1:
 619                 reg = OMAP2_CONTROL_DEVCONF0;
 620                 sel_bit = 6;
 621                 break;
 622         case 2:
 623                 reg = reg_devconf1;
 624                 sel_bit = 0;
 625                 break;
 626         case 3:
 627                 reg = reg_devconf1;
 628                 sel_bit = 2;
 629                 break;
 630         case 4:
 631                 reg = reg_devconf1;
 632                 sel_bit = 4;
 633                 break;
 634         default:
 635                 return -EINVAL;
 636         }
 637
 638         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 639                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 640         else
 641                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 642
 643         return 0;
 644 }
 645
 646 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
 647                                        int clk_id)
 648 {
 649         int sel_bit, set = 0;
 650         u16 reg = OMAP2_CONTROL_DEVCONF0;
 651
 652         if (cpu_class_is_omap1())
 653                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
 654         if (mcbsp_data->bus_id != 0)
 655                 return -EINVAL;
 656
 657         switch (clk_id) {
 658         case OMAP_MCBSP_CLKR_SRC_CLKX:
 659                 set = 1;
 660         case OMAP_MCBSP_CLKR_SRC_CLKR:
 661                 sel_bit = 3;
 662                 break;
 663         case OMAP_MCBSP_FSR_SRC_FSX:
 664                 set = 1;
 665         case OMAP_MCBSP_FSR_SRC_FSR:
 666                 sel_bit = 4;
 667                 break;
 668         default:
 669                 return -EINVAL;
 670         }
 671
 672         if (set)
 673                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 674         else
 675                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 676
 677         return 0;
 678 }
 679
 680 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 681                                          int clk_id, unsigned int freq,
 682                                          int dir)
 683 {
 684         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 685         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 686         int err = 0;
 687
 688         mcbsp_data->in_freq = freq;
 689
 690         switch (clk_id) {
 691         case OMAP_MCBSP_SYSCLK_CLK:
 692                 regs->srgr2     |= CLKSM;
 693                 break;
 694         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 695         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 696                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 697                 break;
 698
 699         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 700                 regs->srgr2     |= CLKSM;
 701         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 702                 regs->pcr0      |= SCLKME;
 703                 break;
 704
 705         case OMAP_MCBSP_CLKR_SRC_CLKR:
 706         case OMAP_MCBSP_CLKR_SRC_CLKX:
 707         case OMAP_MCBSP_FSR_SRC_FSR:
 708         case OMAP_MCBSP_FSR_SRC_FSX:
 709                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
 710                 break;
 711         default:
 712                 err = -ENODEV;
 713         }
 714
 715         return err;
 716 }
 717
 718 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 719         .startup        = omap_mcbsp_dai_startup,
 720         .shutdown       = omap_mcbsp_dai_shutdown,
 721         .trigger        = omap_mcbsp_dai_trigger,
 722         .delay          = omap_mcbsp_dai_delay,
 723         .hw_params      = omap_mcbsp_dai_hw_params,
 724         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 725         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 726         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 727 };
 728
 729 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 730 {                                                               \
 731         .name = "omap-mcbsp-dai-"#link_id,                      \
 732         .id = (link_id),                                        \
 733         .playback = {                                           \
 734                 .channels_min = 1,                              \
 735                 .channels_max = 16,                             \
 736                 .rates = OMAP_MCBSP_RATES,                      \
 737                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 738                            SNDRV_PCM_FMTBIT_S32_LE,             \
 739         },                                                      \
 740         .capture = {                                            \
 741                 .channels_min = 1,                              \
 742                 .channels_max = 16,                             \
 743                 .rates = OMAP_MCBSP_RATES,                      \
 744                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 745                            SNDRV_PCM_FMTBIT_S32_LE,             \
 746         },                                                      \
 747         .ops = &omap_mcbsp_dai_ops,                             \
 748         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 749 }
 750
 751 struct snd_soc_dai omap_mcbsp_dai[] = {
 752         OMAP_MCBSP_DAI_BUILDER(0),
 753         OMAP_MCBSP_DAI_BUILDER(1),
 754 #if NUM_LINKS >= 3
 755         OMAP_MCBSP_DAI_BUILDER(2),
 756 #endif
 757 #if NUM_LINKS == 5
 758         OMAP_MCBSP_DAI_BUILDER(3),
 759         OMAP_MCBSP_DAI_BUILDER(4),
 760 #endif
 761 };
 762
 763 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 764
 765 int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 766                         struct snd_ctl_elem_info *uinfo)
 767 {
 768         struct soc_mixer_control *mc =
 769                 (struct soc_mixer_control *)kcontrol->private_value;
 770         int max = mc->max;
 771         int min = mc->min;
 772
 773         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 774         uinfo->count = 1;
 775         uinfo->value.integer.min = min;
 776         uinfo->value.integer.max = max;
 777         return 0;
 778 }
 779
 780 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
 781 static int                                                              \
 782 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 783                                         struct snd_ctl_elem_value *uc)  \
 784 {                                                                       \
 785         struct soc_mixer_control *mc =                                  \
 786                 (struct soc_mixer_control *)kc->private_value;          \
 787         int max = mc->max;                                              \
 788         int min = mc->min;                                              \
 789         int val = uc->value.integer.value[0];                           \
 790                                                                         \
 791         if (val < min || val > max)                                     \
 792                 return -EINVAL;                                         \
 793                                                                         \
 794         /* OMAP McBSP implementation uses index values 0..4 */          \
 795         return omap_st_set_chgain((id)-1, channel, val);                \
 796 }
 797
 798 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
 799 static int                                                              \
 800 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 801                                         struct snd_ctl_elem_value *uc)  \
 802 {                                                                       \
 803         s16 chgain;                                                     \
 804                                                                         \
 805         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
 806                 return -EAGAIN;                                         \
 807                                                                         \
 808         uc->value.integer.value[0] = chgain;                            \
 809         return 0;                                                       \
 810 }
 811
 812 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
 813 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
 814 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
 815 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
 816 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
 817 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
 818 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
 819 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
 820
 821 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 822                                 struct snd_ctl_elem_value *ucontrol)
 823 {
 824         struct soc_mixer_control *mc =
 825                 (struct soc_mixer_control *)kcontrol->private_value;
 826         u8 value = ucontrol->value.integer.value[0];
 827
 828         if (value == omap_st_is_enabled(mc->reg))
 829                 return 0;
 830
 831         if (value)
 832                 omap_st_enable(mc->reg);
 833         else
 834                 omap_st_disable(mc->reg);
 835
 836         return 1;
 837 }
 838
 839 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 840                                 struct snd_ctl_elem_value *ucontrol)
 841 {
 842         struct soc_mixer_control *mc =
 843                 (struct soc_mixer_control *)kcontrol->private_value;
 844
 845         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
 846         return 0;
 847 }
 848
 849 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 850         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 851                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 852         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 853                                       -32768, 32767,
 854                                       omap_mcbsp2_get_st_ch0_volume,
 855                                       omap_mcbsp2_set_st_ch0_volume),
 856         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 857                                       -32768, 32767,
 858                                       omap_mcbsp2_get_st_ch1_volume,
 859                                       omap_mcbsp2_set_st_ch1_volume),
 860 };
 861
 862 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 863         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 864                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 865         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 866                                       -32768, 32767,
 867                                       omap_mcbsp3_get_st_ch0_volume,
 868                                       omap_mcbsp3_set_st_ch0_volume),
 869         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 870                                       -32768, 32767,
 871                                       omap_mcbsp3_get_st_ch1_volume,
 872                                       omap_mcbsp3_set_st_ch1_volume),
 873 };
 874
 875 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
 876 {
 877         if (!cpu_is_omap34xx())
 878                 return -ENODEV;
 879
 880         switch (mcbsp_id) {
 881         case 1: /* McBSP 2 */
 882                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
 883                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 884         case 2: /* McBSP 3 */
 885                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
 886                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 887         default:
 888                 break;
 889         }
 890
 891         return -EINVAL;
 892 }
 893 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 894
 895 static int __init snd_omap_mcbsp_init(void)
 896 {
 897         return snd_soc_register_dais(omap_mcbsp_dai,
 898                                      ARRAY_SIZE(omap_mcbsp_dai));
 899 }
 900 module_init(snd_omap_mcbsp_init);
 901
 902 static void __exit snd_omap_mcbsp_exit(void)
 903 {
 904         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 905 }
 906 module_exit(snd_omap_mcbsp_exit);
 907
 908 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 909 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 910 MODULE_LICENSE("GPL");