sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <plat/control.h>
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  43         xhandler_get, xhandler_put) \
  44 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  45         .info = omap_mcbsp_st_info_volsw, \
  46         .get = xhandler_get, .put = xhandler_put, \
  47         .private_value = (unsigned long) &(struct soc_mixer_control) \
  48         {.min = xmin, .max = xmax} }
  49
  50 struct omap_mcbsp_data {
  51         unsigned int                    bus_id;
  52         struct omap_mcbsp_reg_cfg       regs;
  53         unsigned int                    fmt;
  54         /*
  55          * Flags indicating is the bus already activated and configured by
  56          * another substream
  57          */
  58         int                             active;
  59         int                             configured;
  60         unsigned int                    in_freq;
  61         int                             clk_div;
  62         int                             wlen;
  63 };
  64
  65 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  66
  67 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  68
  69 /*
  70  * Stream DMA parameters. DMA request line and port address are set runtime
  71  * since they are different between OMAP1 and later OMAPs
  72  */
  73 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  74
  75 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  76 static const int omap1_dma_reqs[][2] = {
  77         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  78         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  79         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  80 };
  81 static const unsigned long omap1_mcbsp_port[][2] = {
  82         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  83           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  84         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  85           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  86         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  87           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  88 };
  89 #else
  90 static const int omap1_dma_reqs[][2] = {};
  91 static const unsigned long omap1_mcbsp_port[][2] = {};
  92 #endif
  93
  94 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  95 static const int omap24xx_dma_reqs[][2] = {
  96         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  97         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  98 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
  99         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
 100         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
 101         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
 102 #endif
 103 };
 104 #else
 105 static const int omap24xx_dma_reqs[][2] = {};
 106 #endif
 107
 108 #if defined(CONFIG_ARCH_OMAP2420)
 109 static const unsigned long omap2420_mcbsp_port[][2] = {
 110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 114 };
 115 #else
 116 static const unsigned long omap2420_mcbsp_port[][2] = {};
 117 #endif
 118
 119 #if defined(CONFIG_ARCH_OMAP2430)
 120 static const unsigned long omap2430_mcbsp_port[][2] = {
 121         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 122           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 123         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 124           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 125         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 126           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 127         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 129         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 131 };
 132 #else
 133 static const unsigned long omap2430_mcbsp_port[][2] = {};
 134 #endif
 135
 136 #if defined(CONFIG_ARCH_OMAP3)
 137 static const unsigned long omap34xx_mcbsp_port[][2] = {
 138         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 139           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 140         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 141           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 142         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 143           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 144         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 145           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 146         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 147           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 148 };
 149 #else
 150 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 151 #endif
 152
 153 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 154 {
 155         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 156         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 157         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 158         int dma_op_mode = omap_mcbsp_get_dma_op_mode(mcbsp_data->bus_id);
 159         int words;
 160
 161         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 162         if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 163                 /* The FIFO size depends on the McBSP word configuration */
 164                 words = snd_pcm_lib_period_bytes(substream) /
 165                                                         (mcbsp_data->wlen / 8);
 166         else
 167                 words = 1;
 168
 169         /* Configure McBSP internal buffer usage */
 170         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 171                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, words);
 172         else
 173                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, words);
 174 }
 175
 176 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
 177                                     struct snd_pcm_hw_rule *rule)
 178 {
 179         struct snd_interval *buffer_size = hw_param_interval(params,
 180                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 181         struct snd_interval *channels = hw_param_interval(params,
 182                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 183         struct omap_mcbsp_data *mcbsp_data = rule->private;
 184         struct snd_interval frames;
 185         int size;
 186
 187         snd_interval_any(&frames);
 188         size = omap_mcbsp_get_fifo_size(mcbsp_data->bus_id);
 189
 190         frames.min = size / channels->min;
 191         frames.integer = 1;
 192         return snd_interval_refine(buffer_size, &frames);
 193 }
 194
 195 static int omap_mcbsp_hwrule_max_periodsize(struct snd_pcm_hw_params *params,
 196                                     struct snd_pcm_hw_rule *rule)
 197 {
 198         struct snd_interval *period_size = hw_param_interval(params,
 199                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
 200         struct snd_interval *channels = hw_param_interval(params,
 201                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 202         struct snd_pcm_substream *substream = rule->private;
 203         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 204         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 205         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 206         struct snd_interval frames;
 207         int size;
 208
 209         snd_interval_any(&frames);
 210         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 211                 size = omap_mcbsp_get_max_tx_threshold(mcbsp_data->bus_id);
 212         else
 213                 size = omap_mcbsp_get_max_rx_threshold(mcbsp_data->bus_id);
 214
 215         frames.max = size / channels->min;
 216         frames.integer = 1;
 217         return snd_interval_refine(period_size, &frames);
 218 }
 219
 220 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 221                                   struct snd_soc_dai *dai)
 222 {
 223         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 224         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 225         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 226         int bus_id = mcbsp_data->bus_id;
 227         int err = 0;
 228
 229         if (!cpu_dai->active)
 230                 err = omap_mcbsp_request(bus_id);
 231
 232         /*
 233          * OMAP3 McBSP FIFO is word structured.
 234          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 235          * McBSP1,3,4,5 has 128 word long buffer
 236          * This means that the size of the FIFO depends on the sample format.
 237          * For example on McBSP3:
 238          * 16bit samples: size is 128 * 2 = 256 bytes
 239          * 32bit samples: size is 128 * 4 = 512 bytes
 240          * It is simpler to place constraint for buffer and period based on
 241          * channels.
 242          * McBSP3 as example again (16 or 32 bit samples):
 243          * 1 channel (mono): size is 128 frames (128 words)
 244          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 245          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 246          */
 247         if (cpu_is_omap343x()) {
 248                 int dma_op_mode = omap_mcbsp_get_dma_op_mode(bus_id);
 249
 250                 /*
 251                 * The first rule is for the buffer size, we should not allow
 252                 * smaller buffer than the FIFO size to avoid underruns
 253                 */
 254                 snd_pcm_hw_rule_add(substream->runtime, 0,
 255                                     SNDRV_PCM_HW_PARAM_CHANNELS,
 256                                     omap_mcbsp_hwrule_min_buffersize,
 257                                     mcbsp_data,
 258                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
 259
 260                 /*
 261                  * In case of threshold mode, the rule will ensure, that the
 262                  * period size is not bigger than the maximum allowed threshold
 263                  * value.
 264                  */
 265                 if (dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 266                         snd_pcm_hw_rule_add(substream->runtime, 0,
 267                                             SNDRV_PCM_HW_PARAM_CHANNELS,
 268                                             omap_mcbsp_hwrule_max_periodsize,
 269                                             substream,
 270                                             SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
 271         }
 272
 273         return err;
 274 }
 275
 276 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 277                                     struct snd_soc_dai *dai)
 278 {
 279         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 280         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 281         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 282
 283         if (!cpu_dai->active) {
 284                 omap_mcbsp_free(mcbsp_data->bus_id);
 285                 mcbsp_data->configured = 0;
 286         }
 287 }
 288
 289 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 290                                   struct snd_soc_dai *dai)
 291 {
 292         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 293         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 294         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 295         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 296
 297         switch (cmd) {
 298         case SNDRV_PCM_TRIGGER_START:
 299         case SNDRV_PCM_TRIGGER_RESUME:
 300         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 301                 mcbsp_data->active++;
 302                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 303                 break;
 304
 305         case SNDRV_PCM_TRIGGER_STOP:
 306         case SNDRV_PCM_TRIGGER_SUSPEND:
 307         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 308                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 309                 mcbsp_data->active--;
 310                 break;
 311         default:
 312                 err = -EINVAL;
 313         }
 314
 315         return err;
 316 }
 317
 318 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 319                         struct snd_pcm_substream *substream,
 320                         struct snd_soc_dai *dai)
 321 {
 322         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 323         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 324         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 325         u16 fifo_use;
 326         snd_pcm_sframes_t delay;
 327
 328         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 329                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp_data->bus_id);
 330         else
 331                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp_data->bus_id);
 332
 333         /*
 334          * Divide the used locations with the channel count to get the
 335          * FIFO usage in samples (don't care about partial samples in the
 336          * buffer).
 337          */
 338         delay = fifo_use / substream->runtime->channels;
 339
 340         return delay;
 341 }
 342
 343 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 344                                     struct snd_pcm_hw_params *params,
 345                                     struct snd_soc_dai *dai)
 346 {
 347         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 348         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 349         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 350         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 351         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 352         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 353         unsigned long port;
 354         unsigned int format, div, framesize, master;
 355
 356         if (cpu_class_is_omap1()) {
 357                 dma = omap1_dma_reqs[bus_id][substream->stream];
 358                 port = omap1_mcbsp_port[bus_id][substream->stream];
 359         } else if (cpu_is_omap2420()) {
 360                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 361                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 362         } else if (cpu_is_omap2430()) {
 363                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 364                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 365         } else if (cpu_is_omap343x()) {
 366                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 367                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 368                 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
 369                                                 omap_mcbsp_set_threshold;
 370                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 371                 if (omap_mcbsp_get_dma_op_mode(bus_id) ==
 372                                                 MCBSP_DMA_MODE_THRESHOLD)
 373                         sync_mode = OMAP_DMA_SYNC_FRAME;
 374         } else {
 375                 return -ENODEV;
 376         }
 377         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 378                 substream->stream ? "Audio Capture" : "Audio Playback";
 379         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 380         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 381         omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
 382         switch (params_format(params)) {
 383         case SNDRV_PCM_FORMAT_S16_LE:
 384                 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
 385                          OMAP_DMA_DATA_TYPE_S16;
 386                 break;
 387         case SNDRV_PCM_FORMAT_S32_LE:
 388                 omap_mcbsp_dai_dma_params[id][substream->stream].data_type =
 389                          OMAP_DMA_DATA_TYPE_S32;
 390                 break;
 391         default:
 392                 return -EINVAL;
 393         }
 394
 395         snd_soc_dai_set_dma_data(cpu_dai, substream,
 396                 &omap_mcbsp_dai_dma_params[id][substream->stream]);
 397
 398         if (mcbsp_data->configured) {
 399                 /* McBSP already configured by another stream */
 400                 return 0;
 401         }
 402
 403         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 404         wpf = channels = params_channels(params);
 405         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 406                               format == SND_SOC_DAIFMT_LEFT_J)) {
 407                 /* Use dual-phase frames */
 408                 regs->rcr2      |= RPHASE;
 409                 regs->xcr2      |= XPHASE;
 410                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 411                 wpf--;
 412                 regs->rcr2      |= RFRLEN2(wpf - 1);
 413                 regs->xcr2      |= XFRLEN2(wpf - 1);
 414         }
 415
 416         regs->rcr1      |= RFRLEN1(wpf - 1);
 417         regs->xcr1      |= XFRLEN1(wpf - 1);
 418
 419         switch (params_format(params)) {
 420         case SNDRV_PCM_FORMAT_S16_LE:
 421                 /* Set word lengths */
 422                 wlen = 16;
 423                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 424                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 425                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 426                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 427                 break;
 428         case SNDRV_PCM_FORMAT_S32_LE:
 429                 /* Set word lengths */
 430                 wlen = 32;
 431                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 432                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 433                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 434                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 435                 break;
 436         default:
 437                 /* Unsupported PCM format */
 438                 return -EINVAL;
 439         }
 440
 441         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 442          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 443         master = mcbsp_data->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 444         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 445                 div = mcbsp_data->clk_div ? mcbsp_data->clk_div : 1;
 446                 framesize = (mcbsp_data->in_freq / div) / params_rate(params);
 447
 448                 if (framesize < wlen * channels) {
 449                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 450                                         "channels\n", __func__);
 451                         return -EINVAL;
 452                 }
 453         } else
 454                 framesize = wlen * channels;
 455
 456         /* Set FS period and length in terms of bit clock periods */
 457         switch (format) {
 458         case SND_SOC_DAIFMT_I2S:
 459         case SND_SOC_DAIFMT_LEFT_J:
 460                 regs->srgr2     |= FPER(framesize - 1);
 461                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 462                 break;
 463         case SND_SOC_DAIFMT_DSP_A:
 464         case SND_SOC_DAIFMT_DSP_B:
 465                 regs->srgr2     |= FPER(framesize - 1);
 466                 regs->srgr1     |= FWID(0);
 467                 break;
 468         }
 469
 470         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 471         mcbsp_data->wlen = wlen;
 472         mcbsp_data->configured = 1;
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 479  * cache is initialized here
 480  */
 481 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 482                                       unsigned int fmt)
 483 {
 484         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 485         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 486         unsigned int temp_fmt = fmt;
 487
 488         if (mcbsp_data->configured)
 489                 return 0;
 490
 491         mcbsp_data->fmt = fmt;
 492         memset(regs, 0, sizeof(*regs));
 493         /* Generic McBSP register settings */
 494         regs->spcr2     |= XINTM(3) | FREE;
 495         regs->spcr1     |= RINTM(3);
 496         /* RFIG and XFIG are not defined in 34xx */
 497         if (!cpu_is_omap34xx()) {
 498                 regs->rcr2      |= RFIG;
 499                 regs->xcr2      |= XFIG;
 500         }
 501         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 502                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 503                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 504         }
 505
 506         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 507         case SND_SOC_DAIFMT_I2S:
 508                 /* 1-bit data delay */
 509                 regs->rcr2      |= RDATDLY(1);
 510                 regs->xcr2      |= XDATDLY(1);
 511                 break;
 512         case SND_SOC_DAIFMT_LEFT_J:
 513                 /* 0-bit data delay */
 514                 regs->rcr2      |= RDATDLY(0);
 515                 regs->xcr2      |= XDATDLY(0);
 516                 regs->spcr1     |= RJUST(2);
 517                 /* Invert FS polarity configuration */
 518                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 519                 break;
 520         case SND_SOC_DAIFMT_DSP_A:
 521                 /* 1-bit data delay */
 522                 regs->rcr2      |= RDATDLY(1);
 523                 regs->xcr2      |= XDATDLY(1);
 524                 /* Invert FS polarity configuration */
 525                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 526                 break;
 527         case SND_SOC_DAIFMT_DSP_B:
 528                 /* 0-bit data delay */
 529                 regs->rcr2      |= RDATDLY(0);
 530                 regs->xcr2      |= XDATDLY(0);
 531                 /* Invert FS polarity configuration */
 532                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 533                 break;
 534         default:
 535                 /* Unsupported data format */
 536                 return -EINVAL;
 537         }
 538
 539         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 540         case SND_SOC_DAIFMT_CBS_CFS:
 541                 /* McBSP master. Set FS and bit clocks as outputs */
 542                 regs->pcr0      |= FSXM | FSRM |
 543                                    CLKXM | CLKRM;
 544                 /* Sample rate generator drives the FS */
 545                 regs->srgr2     |= FSGM;
 546                 break;
 547         case SND_SOC_DAIFMT_CBM_CFM:
 548                 /* McBSP slave */
 549                 break;
 550         default:
 551                 /* Unsupported master/slave configuration */
 552                 return -EINVAL;
 553         }
 554
 555         /* Set bit clock (CLKX/CLKR) and FS polarities */
 556         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 557         case SND_SOC_DAIFMT_NB_NF:
 558                 /*
 559                  * Normal BCLK + FS.
 560                  * FS active low. TX data driven on falling edge of bit clock
 561                  * and RX data sampled on rising edge of bit clock.
 562                  */
 563                 regs->pcr0      |= FSXP | FSRP |
 564                                    CLKXP | CLKRP;
 565                 break;
 566         case SND_SOC_DAIFMT_NB_IF:
 567                 regs->pcr0      |= CLKXP | CLKRP;
 568                 break;
 569         case SND_SOC_DAIFMT_IB_NF:
 570                 regs->pcr0      |= FSXP | FSRP;
 571                 break;
 572         case SND_SOC_DAIFMT_IB_IF:
 573                 break;
 574         default:
 575                 return -EINVAL;
 576         }
 577
 578         return 0;
 579 }
 580
 581 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 582                                      int div_id, int div)
 583 {
 584         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 585         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 586
 587         if (div_id != OMAP_MCBSP_CLKGDV)
 588                 return -ENODEV;
 589
 590         mcbsp_data->clk_div = div;
 591         regs->srgr1     |= CLKGDV(div - 1);
 592
 593         return 0;
 594 }
 595
 596 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 597                                        int clk_id)
 598 {
 599         int sel_bit;
 600         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 601
 602         if (cpu_class_is_omap1()) {
 603                 /* OMAP1's can use only external source clock */
 604                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 605                         return -EINVAL;
 606                 else
 607                         return 0;
 608         }
 609
 610         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 611                 return -EINVAL;
 612
 613         if (cpu_is_omap343x())
 614                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 615
 616         switch (mcbsp_data->bus_id) {
 617         case 0:
 618                 reg = OMAP2_CONTROL_DEVCONF0;
 619                 sel_bit = 2;
 620                 break;
 621         case 1:
 622                 reg = OMAP2_CONTROL_DEVCONF0;
 623                 sel_bit = 6;
 624                 break;
 625         case 2:
 626                 reg = reg_devconf1;
 627                 sel_bit = 0;
 628                 break;
 629         case 3:
 630                 reg = reg_devconf1;
 631                 sel_bit = 2;
 632                 break;
 633         case 4:
 634                 reg = reg_devconf1;
 635                 sel_bit = 4;
 636                 break;
 637         default:
 638                 return -EINVAL;
 639         }
 640
 641         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 642                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 643         else
 644                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 645
 646         return 0;
 647 }
 648
 649 static int omap_mcbsp_dai_set_rcvr_src(struct omap_mcbsp_data *mcbsp_data,
 650                                        int clk_id)
 651 {
 652         int sel_bit, set = 0;
 653         u16 reg = OMAP2_CONTROL_DEVCONF0;
 654
 655         if (cpu_class_is_omap1())
 656                 return -EINVAL; /* TODO: Can this be implemented for OMAP1? */
 657         if (mcbsp_data->bus_id != 0)
 658                 return -EINVAL;
 659
 660         switch (clk_id) {
 661         case OMAP_MCBSP_CLKR_SRC_CLKX:
 662                 set = 1;
 663         case OMAP_MCBSP_CLKR_SRC_CLKR:
 664                 sel_bit = 3;
 665                 break;
 666         case OMAP_MCBSP_FSR_SRC_FSX:
 667                 set = 1;
 668         case OMAP_MCBSP_FSR_SRC_FSR:
 669                 sel_bit = 4;
 670                 break;
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         if (set)
 676                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 677         else
 678                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 679
 680         return 0;
 681 }
 682
 683 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 684                                          int clk_id, unsigned int freq,
 685                                          int dir)
 686 {
 687         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 688         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 689         int err = 0;
 690
 691         mcbsp_data->in_freq = freq;
 692
 693         switch (clk_id) {
 694         case OMAP_MCBSP_SYSCLK_CLK:
 695                 regs->srgr2     |= CLKSM;
 696                 break;
 697         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 698         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 699                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 700                 break;
 701
 702         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 703                 regs->srgr2     |= CLKSM;
 704         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 705                 regs->pcr0      |= SCLKME;
 706                 break;
 707
 708         case OMAP_MCBSP_CLKR_SRC_CLKR:
 709         case OMAP_MCBSP_CLKR_SRC_CLKX:
 710         case OMAP_MCBSP_FSR_SRC_FSR:
 711         case OMAP_MCBSP_FSR_SRC_FSX:
 712                 err = omap_mcbsp_dai_set_rcvr_src(mcbsp_data, clk_id);
 713                 break;
 714         default:
 715                 err = -ENODEV;
 716         }
 717
 718         return err;
 719 }
 720
 721 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 722         .startup        = omap_mcbsp_dai_startup,
 723         .shutdown       = omap_mcbsp_dai_shutdown,
 724         .trigger        = omap_mcbsp_dai_trigger,
 725         .delay          = omap_mcbsp_dai_delay,
 726         .hw_params      = omap_mcbsp_dai_hw_params,
 727         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 728         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 729         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 730 };
 731
 732 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 733 {                                                               \
 734         .name = "omap-mcbsp-dai-"#link_id,                      \
 735         .id = (link_id),                                        \
 736         .playback = {                                           \
 737                 .channels_min = 1,                              \
 738                 .channels_max = 16,                             \
 739                 .rates = OMAP_MCBSP_RATES,                      \
 740                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 741                            SNDRV_PCM_FMTBIT_S32_LE,             \
 742         },                                                      \
 743         .capture = {                                            \
 744                 .channels_min = 1,                              \
 745                 .channels_max = 16,                             \
 746                 .rates = OMAP_MCBSP_RATES,                      \
 747                 .formats = SNDRV_PCM_FMTBIT_S16_LE |            \
 748                            SNDRV_PCM_FMTBIT_S32_LE,             \
 749         },                                                      \
 750         .ops = &omap_mcbsp_dai_ops,                             \
 751         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 752 }
 753
 754 struct snd_soc_dai omap_mcbsp_dai[] = {
 755         OMAP_MCBSP_DAI_BUILDER(0),
 756         OMAP_MCBSP_DAI_BUILDER(1),
 757 #if NUM_LINKS >= 3
 758         OMAP_MCBSP_DAI_BUILDER(2),
 759 #endif
 760 #if NUM_LINKS == 5
 761         OMAP_MCBSP_DAI_BUILDER(3),
 762         OMAP_MCBSP_DAI_BUILDER(4),
 763 #endif
 764 };
 765
 766 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 767
 768 int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 769                         struct snd_ctl_elem_info *uinfo)
 770 {
 771         struct soc_mixer_control *mc =
 772                 (struct soc_mixer_control *)kcontrol->private_value;
 773         int max = mc->max;
 774         int min = mc->min;
 775
 776         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 777         uinfo->count = 1;
 778         uinfo->value.integer.min = min;
 779         uinfo->value.integer.max = max;
 780         return 0;
 781 }
 782
 783 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(id, channel)                   \
 784 static int                                                              \
 785 omap_mcbsp##id##_set_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 786                                         struct snd_ctl_elem_value *uc)  \
 787 {                                                                       \
 788         struct soc_mixer_control *mc =                                  \
 789                 (struct soc_mixer_control *)kc->private_value;          \
 790         int max = mc->max;                                              \
 791         int min = mc->min;                                              \
 792         int val = uc->value.integer.value[0];                           \
 793                                                                         \
 794         if (val < min || val > max)                                     \
 795                 return -EINVAL;                                         \
 796                                                                         \
 797         /* OMAP McBSP implementation uses index values 0..4 */          \
 798         return omap_st_set_chgain((id)-1, channel, val);                \
 799 }
 800
 801 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(id, channel)                   \
 802 static int                                                              \
 803 omap_mcbsp##id##_get_st_ch##channel##_volume(struct snd_kcontrol *kc,   \
 804                                         struct snd_ctl_elem_value *uc)  \
 805 {                                                                       \
 806         s16 chgain;                                                     \
 807                                                                         \
 808         if (omap_st_get_chgain((id)-1, channel, &chgain))               \
 809                 return -EAGAIN;                                         \
 810                                                                         \
 811         uc->value.integer.value[0] = chgain;                            \
 812         return 0;                                                       \
 813 }
 814
 815 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 0)
 816 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(2, 1)
 817 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 0)
 818 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(3, 1)
 819 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 0)
 820 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(2, 1)
 821 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 0)
 822 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(3, 1)
 823
 824 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 825                                 struct snd_ctl_elem_value *ucontrol)
 826 {
 827         struct soc_mixer_control *mc =
 828                 (struct soc_mixer_control *)kcontrol->private_value;
 829         u8 value = ucontrol->value.integer.value[0];
 830
 831         if (value == omap_st_is_enabled(mc->reg))
 832                 return 0;
 833
 834         if (value)
 835                 omap_st_enable(mc->reg);
 836         else
 837                 omap_st_disable(mc->reg);
 838
 839         return 1;
 840 }
 841
 842 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 843                                 struct snd_ctl_elem_value *ucontrol)
 844 {
 845         struct soc_mixer_control *mc =
 846                 (struct soc_mixer_control *)kcontrol->private_value;
 847
 848         ucontrol->value.integer.value[0] = omap_st_is_enabled(mc->reg);
 849         return 0;
 850 }
 851
 852 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 853         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 854                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 855         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 856                                       -32768, 32767,
 857                                       omap_mcbsp2_get_st_ch0_volume,
 858                                       omap_mcbsp2_set_st_ch0_volume),
 859         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 860                                       -32768, 32767,
 861                                       omap_mcbsp2_get_st_ch1_volume,
 862                                       omap_mcbsp2_set_st_ch1_volume),
 863 };
 864
 865 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 866         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 867                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 868         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 869                                       -32768, 32767,
 870                                       omap_mcbsp3_get_st_ch0_volume,
 871                                       omap_mcbsp3_set_st_ch0_volume),
 872         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 873                                       -32768, 32767,
 874                                       omap_mcbsp3_get_st_ch1_volume,
 875                                       omap_mcbsp3_set_st_ch1_volume),
 876 };
 877
 878 int omap_mcbsp_st_add_controls(struct snd_soc_codec *codec, int mcbsp_id)
 879 {
 880         if (!cpu_is_omap34xx())
 881                 return -ENODEV;
 882
 883         switch (mcbsp_id) {
 884         case 1: /* McBSP 2 */
 885                 return snd_soc_add_controls(codec, omap_mcbsp2_st_controls,
 886                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 887         case 2: /* McBSP 3 */
 888                 return snd_soc_add_controls(codec, omap_mcbsp3_st_controls,
 889                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 890         default:
 891                 break;
 892         }
 893
 894         return -EINVAL;
 895 }
 896 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 897
 898 static int __init snd_omap_mcbsp_init(void)
 899 {
 900         return snd_soc_register_dais(omap_mcbsp_dai,
 901                                      ARRAY_SIZE(omap_mcbsp_dai));
 902 }
 903 module_init(snd_omap_mcbsp_init);
 904
 905 static void __exit snd_omap_mcbsp_exit(void)
 906 {
 907         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 908 }
 909 module_exit(snd_omap_mcbsp_exit);
 910
 911 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 912 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 913 MODULE_LICENSE("GPL");