2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/initval.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/pxa2xx-lib.h>
33 #include <mach/hardware.h>
35 #include <mach/audio.h>
38 #include "pxa2xx-pcm.h"
42 * SSP audio private data
45 struct ssp_device *ssp;
56 static void dump_registers(struct ssp_device *ssp)
58 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
59 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
60 pxa_ssp_read_reg(ssp, SSTO));
62 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
63 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
64 pxa_ssp_read_reg(ssp, SSACD));
67 static void pxa_ssp_enable(struct ssp_device *ssp)
71 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
72 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
75 static void pxa_ssp_disable(struct ssp_device *ssp)
79 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
80 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
83 struct pxa2xx_pcm_dma_data {
84 struct pxa2xx_pcm_dma_params params;
88 static struct pxa2xx_pcm_dma_params *
89 pxa_ssp_get_dma_params(struct ssp_device *ssp, int width4, int out)
91 struct pxa2xx_pcm_dma_data *dma;
93 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL);
97 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id,
98 width4 ? "32-bit" : "16-bit", out ? "out" : "in");
100 dma->params.name = dma->name;
101 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx);
102 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) :
103 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) |
104 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16;
105 dma->params.dev_addr = ssp->phys_base + SSDR;
110 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
111 struct snd_soc_dai *dai)
113 struct snd_soc_pcm_runtime *rtd = substream->private_data;
114 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
115 struct ssp_priv *priv = cpu_dai->private_data;
116 struct ssp_device *ssp = priv->ssp;
119 if (!cpu_dai->active) {
120 clk_enable(ssp->clk);
121 pxa_ssp_disable(ssp);
124 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
125 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
130 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
131 struct snd_soc_dai *dai)
133 struct snd_soc_pcm_runtime *rtd = substream->private_data;
134 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
135 struct ssp_priv *priv = cpu_dai->private_data;
136 struct ssp_device *ssp = priv->ssp;
138 if (!cpu_dai->active) {
139 pxa_ssp_disable(ssp);
140 clk_disable(ssp->clk);
143 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
144 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
149 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
151 struct ssp_priv *priv = cpu_dai->private_data;
152 struct ssp_device *ssp = priv->ssp;
154 if (!cpu_dai->active)
155 clk_enable(ssp->clk);
157 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
158 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
159 priv->to = __raw_readl(ssp->mmio_base + SSTO);
160 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
162 pxa_ssp_disable(ssp);
163 clk_disable(ssp->clk);
167 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
169 struct ssp_priv *priv = cpu_dai->private_data;
170 struct ssp_device *ssp = priv->ssp;
171 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
173 clk_enable(ssp->clk);
175 __raw_writel(sssr, ssp->mmio_base + SSSR);
176 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
177 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
178 __raw_writel(priv->to, ssp->mmio_base + SSTO);
179 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
184 clk_disable(ssp->clk);
190 #define pxa_ssp_suspend NULL
191 #define pxa_ssp_resume NULL
195 * ssp_set_clkdiv - set SSP clock divider
196 * @div: serial clock rate divider
198 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
200 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
202 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {
203 sscr0 &= ~0x0000ff00;
204 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
206 sscr0 &= ~0x000fff00;
207 sscr0 |= (div - 1) << 8; /* 1..4096 */
209 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
213 * pxa_ssp_get_clkdiv - get SSP clock divider
215 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
217 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
220 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)
221 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
223 div = ((sscr0 >> 8) & 0xfff) + 1;
228 * Set the SSP ports SYSCLK.
230 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
231 int clk_id, unsigned int freq, int dir)
233 struct ssp_priv *priv = cpu_dai->private_data;
234 struct ssp_device *ssp = priv->ssp;
237 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
238 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
240 dev_dbg(&ssp->pdev->dev,
241 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
242 cpu_dai->id, clk_id, freq);
245 case PXA_SSP_CLK_NET_PLL:
248 case PXA_SSP_CLK_PLL:
249 /* Internal PLL is fixed */
251 priv->sysclk = 1843200;
253 priv->sysclk = 13000000;
255 case PXA_SSP_CLK_EXT:
259 case PXA_SSP_CLK_NET:
261 sscr0 |= SSCR0_NCS | SSCR0_MOD;
263 case PXA_SSP_CLK_AUDIO:
265 pxa_ssp_set_scr(ssp, 1);
272 /* The SSP clock must be disabled when changing SSP clock mode
273 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
274 if (!cpu_is_pxa3xx())
275 clk_disable(ssp->clk);
276 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
277 pxa_ssp_write_reg(ssp, SSCR0, val);
278 if (!cpu_is_pxa3xx())
279 clk_enable(ssp->clk);
285 * Set the SSP clock dividers.
287 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
290 struct ssp_priv *priv = cpu_dai->private_data;
291 struct ssp_device *ssp = priv->ssp;
295 case PXA_SSP_AUDIO_DIV_ACDS:
296 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
297 pxa_ssp_write_reg(ssp, SSACD, val);
299 case PXA_SSP_AUDIO_DIV_SCDB:
300 val = pxa_ssp_read_reg(ssp, SSACD);
302 #if defined(CONFIG_PXA3xx)
307 case PXA_SSP_CLK_SCDB_1:
310 case PXA_SSP_CLK_SCDB_4:
312 #if defined(CONFIG_PXA3xx)
313 case PXA_SSP_CLK_SCDB_8:
323 pxa_ssp_write_reg(ssp, SSACD, val);
325 case PXA_SSP_DIV_SCR:
326 pxa_ssp_set_scr(ssp, div);
336 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
338 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
339 int source, unsigned int freq_in, unsigned int freq_out)
341 struct ssp_priv *priv = cpu_dai->private_data;
342 struct ssp_device *ssp = priv->ssp;
343 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
345 #if defined(CONFIG_PXA3xx)
347 pxa_ssp_write_reg(ssp, SSACDD, 0);
374 /* PXA3xx has a clock ditherer which can be used to generate
375 * a wider range of frequencies - calculate a value for it.
377 if (cpu_is_pxa3xx()) {
381 do_div(tmp, freq_out);
384 val = (val << 16) | 64;
385 pxa_ssp_write_reg(ssp, SSACDD, val);
389 dev_dbg(&ssp->pdev->dev,
390 "Using SSACDD %x to supply %uHz\n",
399 pxa_ssp_write_reg(ssp, SSACD, ssacd);
405 * Set the active slots in TDM/Network mode
407 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
408 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
410 struct ssp_priv *priv = cpu_dai->private_data;
411 struct ssp_device *ssp = priv->ssp;
414 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
415 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
419 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
421 sscr0 |= SSCR0_DataSize(slot_width);
424 /* enable network mode */
427 /* set number of active slots */
428 sscr0 |= SSCR0_SlotsPerFrm(slots);
430 /* set active slot mask */
431 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
432 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
434 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
440 * Tristate the SSP DAI lines
442 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
445 struct ssp_priv *priv = cpu_dai->private_data;
446 struct ssp_device *ssp = priv->ssp;
449 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
454 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
460 * Set up the SSP DAI format.
461 * The SSP Port must be inactive before calling this function as the
462 * physical interface format is changed.
464 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
467 struct ssp_priv *priv = cpu_dai->private_data;
468 struct ssp_device *ssp = priv->ssp;
473 /* check if we need to change anything at all */
474 if (priv->dai_fmt == fmt)
477 /* we can only change the settings if the port is not in use */
478 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
479 dev_err(&ssp->pdev->dev,
480 "can't change hardware dai format: stream is in use");
484 /* reset port settings */
485 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
486 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
487 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
490 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
491 case SND_SOC_DAIFMT_CBM_CFM:
492 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
494 case SND_SOC_DAIFMT_CBM_CFS:
495 sscr1 |= SSCR1_SCLKDIR;
497 case SND_SOC_DAIFMT_CBS_CFS:
503 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
504 case SND_SOC_DAIFMT_NB_NF:
505 sspsp |= SSPSP_SFRMP;
507 case SND_SOC_DAIFMT_NB_IF:
509 case SND_SOC_DAIFMT_IB_IF:
510 sspsp |= SSPSP_SCMODE(2);
512 case SND_SOC_DAIFMT_IB_NF:
513 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
519 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
520 case SND_SOC_DAIFMT_I2S:
522 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
523 /* See hw_params() */
526 case SND_SOC_DAIFMT_DSP_A:
528 case SND_SOC_DAIFMT_DSP_B:
529 sscr0 |= SSCR0_MOD | SSCR0_PSP;
530 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
537 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
538 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
539 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
543 /* Since we are configuring the timings for the format by hand
544 * we have to defer some things until hw_params() where we
545 * know parameters like the sample size.
553 * Set the SSP audio DMA parameters and sample size.
554 * Can be called multiple times by oss emulation.
556 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
557 struct snd_pcm_hw_params *params,
558 struct snd_soc_dai *dai)
560 struct snd_soc_pcm_runtime *rtd = substream->private_data;
561 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
562 struct ssp_priv *priv = cpu_dai->private_data;
563 struct ssp_device *ssp = priv->ssp;
564 int chn = params_channels(params);
567 int width = snd_pcm_format_physical_width(params_format(params));
568 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
569 struct pxa2xx_pcm_dma_params *dma_data;
571 dma_data = snd_soc_dai_get_dma_data(dai, substream);
573 /* generate correct DMA params */
576 /* Network mode with one active slot (ttsa == 1) can be used
577 * to force 16-bit frame width on the wire (for S16_LE), even
578 * with two channels. Use 16-bit DMA transfers for this case.
580 dma_data = pxa_ssp_get_dma_params(ssp,
581 ((chn == 2) && (ttsa != 1)) || (width == 32),
582 substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
584 snd_soc_dai_set_dma_data(dai, substream, dma_data);
586 /* we can only change the settings if the port is not in use */
587 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
590 /* clear selected SSP bits */
591 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
592 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
595 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
596 switch (params_format(params)) {
597 case SNDRV_PCM_FORMAT_S16_LE:
600 sscr0 |= SSCR0_FPCKE;
602 sscr0 |= SSCR0_DataSize(16);
604 case SNDRV_PCM_FORMAT_S24_LE:
605 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
607 case SNDRV_PCM_FORMAT_S32_LE:
608 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
611 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
613 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
614 case SND_SOC_DAIFMT_I2S:
615 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
617 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
618 /* This is a special case where the bitclk is 64fs
619 * and we're not dealing with 2*32 bits of audio
622 * The SSP values used for that are all found out by
623 * trying and failing a lot; some of the registers
624 * needed for that mode are only available on PXA3xx.
628 if (!cpu_is_pxa3xx())
631 sspsp |= SSPSP_SFRMWDTH(width * 2);
632 sspsp |= SSPSP_SFRMDLY(width * 4);
633 sspsp |= SSPSP_EDMYSTOP(3);
634 sspsp |= SSPSP_DMYSTOP(3);
635 sspsp |= SSPSP_DMYSTRT(1);
640 /* The frame width is the width the LRCLK is
641 * asserted for; the delay is expressed in
642 * half cycle units. We need the extra cycle
643 * because the data starts clocking out one BCLK
644 * after LRCLK changes polarity.
646 sspsp |= SSPSP_SFRMWDTH(width + 1);
647 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
648 sspsp |= SSPSP_DMYSTRT(1);
651 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
657 /* When we use a network mode, we always require TDM slots
658 * - complain loudly and fail if they've not been set up yet.
660 if ((sscr0 & SSCR0_MOD) && !ttsa) {
661 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
670 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
671 struct snd_soc_dai *dai)
673 struct snd_soc_pcm_runtime *rtd = substream->private_data;
674 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
676 struct ssp_priv *priv = cpu_dai->private_data;
677 struct ssp_device *ssp = priv->ssp;
681 case SNDRV_PCM_TRIGGER_RESUME:
684 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
685 val = pxa_ssp_read_reg(ssp, SSCR1);
686 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
690 pxa_ssp_write_reg(ssp, SSCR1, val);
691 val = pxa_ssp_read_reg(ssp, SSSR);
692 pxa_ssp_write_reg(ssp, SSSR, val);
694 case SNDRV_PCM_TRIGGER_START:
695 val = pxa_ssp_read_reg(ssp, SSCR1);
696 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
700 pxa_ssp_write_reg(ssp, SSCR1, val);
703 case SNDRV_PCM_TRIGGER_STOP:
704 val = pxa_ssp_read_reg(ssp, SSCR1);
705 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
709 pxa_ssp_write_reg(ssp, SSCR1, val);
711 case SNDRV_PCM_TRIGGER_SUSPEND:
712 pxa_ssp_disable(ssp);
714 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
715 val = pxa_ssp_read_reg(ssp, SSCR1);
716 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
720 pxa_ssp_write_reg(ssp, SSCR1, val);
732 static int pxa_ssp_probe(struct platform_device *pdev,
733 struct snd_soc_dai *dai)
735 struct ssp_priv *priv;
738 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
742 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
743 if (priv->ssp == NULL) {
748 priv->dai_fmt = (unsigned int) -1;
749 dai->private_data = priv;
758 static void pxa_ssp_remove(struct platform_device *pdev,
759 struct snd_soc_dai *dai)
761 struct ssp_priv *priv = dai->private_data;
762 pxa_ssp_free(priv->ssp);
765 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
766 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
767 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
768 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
770 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
771 SNDRV_PCM_FMTBIT_S24_LE | \
772 SNDRV_PCM_FMTBIT_S32_LE)
774 static struct snd_soc_dai_ops pxa_ssp_dai_ops = {
775 .startup = pxa_ssp_startup,
776 .shutdown = pxa_ssp_shutdown,
777 .trigger = pxa_ssp_trigger,
778 .hw_params = pxa_ssp_hw_params,
779 .set_sysclk = pxa_ssp_set_dai_sysclk,
780 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
781 .set_pll = pxa_ssp_set_dai_pll,
782 .set_fmt = pxa_ssp_set_dai_fmt,
783 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
784 .set_tristate = pxa_ssp_set_dai_tristate,
787 struct snd_soc_dai pxa_ssp_dai[] = {
789 .name = "pxa2xx-ssp1",
791 .probe = pxa_ssp_probe,
792 .remove = pxa_ssp_remove,
793 .suspend = pxa_ssp_suspend,
794 .resume = pxa_ssp_resume,
798 .rates = PXA_SSP_RATES,
799 .formats = PXA_SSP_FORMATS,
804 .rates = PXA_SSP_RATES,
805 .formats = PXA_SSP_FORMATS,
807 .ops = &pxa_ssp_dai_ops,
809 { .name = "pxa2xx-ssp2",
811 .probe = pxa_ssp_probe,
812 .remove = pxa_ssp_remove,
813 .suspend = pxa_ssp_suspend,
814 .resume = pxa_ssp_resume,
818 .rates = PXA_SSP_RATES,
819 .formats = PXA_SSP_FORMATS,
824 .rates = PXA_SSP_RATES,
825 .formats = PXA_SSP_FORMATS,
827 .ops = &pxa_ssp_dai_ops,
830 .name = "pxa2xx-ssp3",
832 .probe = pxa_ssp_probe,
833 .remove = pxa_ssp_remove,
834 .suspend = pxa_ssp_suspend,
835 .resume = pxa_ssp_resume,
839 .rates = PXA_SSP_RATES,
840 .formats = PXA_SSP_FORMATS,
845 .rates = PXA_SSP_RATES,
846 .formats = PXA_SSP_FORMATS,
848 .ops = &pxa_ssp_dai_ops,
851 .name = "pxa2xx-ssp4",
853 .probe = pxa_ssp_probe,
854 .remove = pxa_ssp_remove,
855 .suspend = pxa_ssp_suspend,
856 .resume = pxa_ssp_resume,
860 .rates = PXA_SSP_RATES,
861 .formats = PXA_SSP_FORMATS,
866 .rates = PXA_SSP_RATES,
867 .formats = PXA_SSP_FORMATS,
869 .ops = &pxa_ssp_dai_ops,
872 EXPORT_SYMBOL_GPL(pxa_ssp_dai);
874 static int __init pxa_ssp_init(void)
876 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
878 module_init(pxa_ssp_init);
880 static void __exit pxa_ssp_exit(void)
882 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai));
884 module_exit(pxa_ssp_exit);
886 /* Module information */
887 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
888 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
889 MODULE_LICENSE("GPL");