2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
23 #include <linux/pxa2xx_ssp.h>
25 #include <linux/dmaengine.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
37 #include "../../arm/pxa2xx-pcm.h"
41 * SSP audio private data
44 struct ssp_device *ssp;
55 static void dump_registers(struct ssp_device *ssp)
57 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
58 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
59 pxa_ssp_read_reg(ssp, SSTO));
61 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
62 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
63 pxa_ssp_read_reg(ssp, SSACD));
66 static void pxa_ssp_enable(struct ssp_device *ssp)
70 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
71 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
74 static void pxa_ssp_disable(struct ssp_device *ssp)
78 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
79 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
82 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
83 int out, struct snd_dmaengine_dai_dma_data *dma)
85 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
86 DMA_SLAVE_BUSWIDTH_2_BYTES;
88 dma->addr = ssp->phys_base + SSDR;
91 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
92 struct snd_soc_dai *cpu_dai)
94 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
95 struct ssp_device *ssp = priv->ssp;
96 struct snd_dmaengine_dai_dma_data *dma;
99 if (!cpu_dai->active) {
100 clk_enable(ssp->clk);
101 pxa_ssp_disable(ssp);
104 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
108 dma->filter_data = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
109 &ssp->drcmr_tx : &ssp->drcmr_rx;
111 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
116 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
117 struct snd_soc_dai *cpu_dai)
119 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
120 struct ssp_device *ssp = priv->ssp;
122 if (!cpu_dai->active) {
123 pxa_ssp_disable(ssp);
124 clk_disable(ssp->clk);
127 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
128 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
133 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
135 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
136 struct ssp_device *ssp = priv->ssp;
138 if (!cpu_dai->active)
139 clk_enable(ssp->clk);
141 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
142 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
143 priv->to = __raw_readl(ssp->mmio_base + SSTO);
144 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
146 pxa_ssp_disable(ssp);
147 clk_disable(ssp->clk);
151 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
153 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
154 struct ssp_device *ssp = priv->ssp;
155 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
157 clk_enable(ssp->clk);
159 __raw_writel(sssr, ssp->mmio_base + SSSR);
160 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
161 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
162 __raw_writel(priv->to, ssp->mmio_base + SSTO);
163 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
168 clk_disable(ssp->clk);
174 #define pxa_ssp_suspend NULL
175 #define pxa_ssp_resume NULL
179 * ssp_set_clkdiv - set SSP clock divider
180 * @div: serial clock rate divider
182 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
184 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
186 if (ssp->type == PXA25x_SSP) {
187 sscr0 &= ~0x0000ff00;
188 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
190 sscr0 &= ~0x000fff00;
191 sscr0 |= (div - 1) << 8; /* 1..4096 */
193 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
197 * pxa_ssp_get_clkdiv - get SSP clock divider
199 static u32 pxa_ssp_get_scr(struct ssp_device *ssp)
201 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
204 if (ssp->type == PXA25x_SSP)
205 div = ((sscr0 >> 8) & 0xff) * 2 + 2;
207 div = ((sscr0 >> 8) & 0xfff) + 1;
212 * Set the SSP ports SYSCLK.
214 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
215 int clk_id, unsigned int freq, int dir)
217 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
218 struct ssp_device *ssp = priv->ssp;
221 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
222 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
224 dev_dbg(&ssp->pdev->dev,
225 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
226 cpu_dai->id, clk_id, freq);
229 case PXA_SSP_CLK_NET_PLL:
232 case PXA_SSP_CLK_PLL:
233 /* Internal PLL is fixed */
234 if (ssp->type == PXA25x_SSP)
235 priv->sysclk = 1843200;
237 priv->sysclk = 13000000;
239 case PXA_SSP_CLK_EXT:
243 case PXA_SSP_CLK_NET:
245 sscr0 |= SSCR0_NCS | SSCR0_MOD;
247 case PXA_SSP_CLK_AUDIO:
249 pxa_ssp_set_scr(ssp, 1);
256 /* The SSP clock must be disabled when changing SSP clock mode
257 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
258 if (ssp->type != PXA3xx_SSP)
259 clk_disable(ssp->clk);
260 val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;
261 pxa_ssp_write_reg(ssp, SSCR0, val);
262 if (ssp->type != PXA3xx_SSP)
263 clk_enable(ssp->clk);
269 * Set the SSP clock dividers.
271 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
274 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
275 struct ssp_device *ssp = priv->ssp;
279 case PXA_SSP_AUDIO_DIV_ACDS:
280 val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
281 pxa_ssp_write_reg(ssp, SSACD, val);
283 case PXA_SSP_AUDIO_DIV_SCDB:
284 val = pxa_ssp_read_reg(ssp, SSACD);
286 if (ssp->type == PXA3xx_SSP)
289 case PXA_SSP_CLK_SCDB_1:
292 case PXA_SSP_CLK_SCDB_4:
294 case PXA_SSP_CLK_SCDB_8:
295 if (ssp->type == PXA3xx_SSP)
303 pxa_ssp_write_reg(ssp, SSACD, val);
305 case PXA_SSP_DIV_SCR:
306 pxa_ssp_set_scr(ssp, div);
316 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
318 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id,
319 int source, unsigned int freq_in, unsigned int freq_out)
321 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
322 struct ssp_device *ssp = priv->ssp;
323 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
325 if (ssp->type == PXA3xx_SSP)
326 pxa_ssp_write_reg(ssp, SSACDD, 0);
351 /* PXA3xx has a clock ditherer which can be used to generate
352 * a wider range of frequencies - calculate a value for it.
354 if (ssp->type == PXA3xx_SSP) {
358 do_div(tmp, freq_out);
361 val = (val << 16) | 64;
362 pxa_ssp_write_reg(ssp, SSACDD, val);
366 dev_dbg(&ssp->pdev->dev,
367 "Using SSACDD %x to supply %uHz\n",
375 pxa_ssp_write_reg(ssp, SSACD, ssacd);
381 * Set the active slots in TDM/Network mode
383 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
384 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
386 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
387 struct ssp_device *ssp = priv->ssp;
390 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
391 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
395 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
397 sscr0 |= SSCR0_DataSize(slot_width);
400 /* enable network mode */
403 /* set number of active slots */
404 sscr0 |= SSCR0_SlotsPerFrm(slots);
406 /* set active slot mask */
407 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
408 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
410 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
416 * Tristate the SSP DAI lines
418 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
421 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
422 struct ssp_device *ssp = priv->ssp;
425 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
430 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
436 * Set up the SSP DAI format.
437 * The SSP Port must be inactive before calling this function as the
438 * physical interface format is changed.
440 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
443 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
444 struct ssp_device *ssp = priv->ssp;
445 u32 sscr0, sscr1, sspsp, scfr;
447 /* check if we need to change anything at all */
448 if (priv->dai_fmt == fmt)
451 /* we can only change the settings if the port is not in use */
452 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) {
453 dev_err(&ssp->pdev->dev,
454 "can't change hardware dai format: stream is in use");
458 /* reset port settings */
459 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
460 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
461 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
464 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
465 case SND_SOC_DAIFMT_CBM_CFM:
466 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
468 case SND_SOC_DAIFMT_CBM_CFS:
469 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
471 case SND_SOC_DAIFMT_CBS_CFS:
477 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
478 case SND_SOC_DAIFMT_NB_NF:
479 sspsp |= SSPSP_SFRMP;
481 case SND_SOC_DAIFMT_NB_IF:
483 case SND_SOC_DAIFMT_IB_IF:
484 sspsp |= SSPSP_SCMODE(2);
486 case SND_SOC_DAIFMT_IB_NF:
487 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
493 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
494 case SND_SOC_DAIFMT_I2S:
496 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
497 /* See hw_params() */
500 case SND_SOC_DAIFMT_DSP_A:
502 case SND_SOC_DAIFMT_DSP_B:
503 sscr0 |= SSCR0_MOD | SSCR0_PSP;
504 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
511 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
512 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
513 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
515 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
516 case SND_SOC_DAIFMT_CBM_CFM:
517 case SND_SOC_DAIFMT_CBM_CFS:
518 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
519 pxa_ssp_write_reg(ssp, SSCR1, scfr);
521 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
528 /* Since we are configuring the timings for the format by hand
529 * we have to defer some things until hw_params() where we
530 * know parameters like the sample size.
538 * Set the SSP audio DMA parameters and sample size.
539 * Can be called multiple times by oss emulation.
541 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
542 struct snd_pcm_hw_params *params,
543 struct snd_soc_dai *cpu_dai)
545 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
546 struct ssp_device *ssp = priv->ssp;
547 int chn = params_channels(params);
550 int width = snd_pcm_format_physical_width(params_format(params));
551 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
552 struct snd_dmaengine_dai_dma_data *dma_data;
554 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
556 /* Network mode with one active slot (ttsa == 1) can be used
557 * to force 16-bit frame width on the wire (for S16_LE), even
558 * with two channels. Use 16-bit DMA transfers for this case.
560 pxa_ssp_set_dma_params(ssp,
561 ((chn == 2) && (ttsa != 1)) || (width == 32),
562 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
564 /* we can only change the settings if the port is not in use */
565 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
568 /* clear selected SSP bits */
569 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
572 switch (params_format(params)) {
573 case SNDRV_PCM_FORMAT_S16_LE:
574 if (ssp->type == PXA3xx_SSP)
575 sscr0 |= SSCR0_FPCKE;
576 sscr0 |= SSCR0_DataSize(16);
578 case SNDRV_PCM_FORMAT_S24_LE:
579 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
581 case SNDRV_PCM_FORMAT_S32_LE:
582 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
585 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
587 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
588 case SND_SOC_DAIFMT_I2S:
589 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
591 if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) {
592 /* This is a special case where the bitclk is 64fs
593 * and we're not dealing with 2*32 bits of audio
596 * The SSP values used for that are all found out by
597 * trying and failing a lot; some of the registers
598 * needed for that mode are only available on PXA3xx.
600 if (ssp->type != PXA3xx_SSP)
603 sspsp |= SSPSP_SFRMWDTH(width * 2);
604 sspsp |= SSPSP_SFRMDLY(width * 4);
605 sspsp |= SSPSP_EDMYSTOP(3);
606 sspsp |= SSPSP_DMYSTOP(3);
607 sspsp |= SSPSP_DMYSTRT(1);
609 /* The frame width is the width the LRCLK is
610 * asserted for; the delay is expressed in
611 * half cycle units. We need the extra cycle
612 * because the data starts clocking out one BCLK
613 * after LRCLK changes polarity.
615 sspsp |= SSPSP_SFRMWDTH(width + 1);
616 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
617 sspsp |= SSPSP_DMYSTRT(1);
620 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
626 /* When we use a network mode, we always require TDM slots
627 * - complain loudly and fail if they've not been set up yet.
629 if ((sscr0 & SSCR0_MOD) && !ttsa) {
630 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
639 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
640 struct ssp_device *ssp, int value)
642 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
643 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
644 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
645 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
647 if (value && (sscr0 & SSCR0_SSE))
648 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
650 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
654 sscr1 &= ~SSCR1_TSRE;
659 sscr1 &= ~SSCR1_RSRE;
662 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
665 pxa_ssp_write_reg(ssp, SSSR, sssr);
666 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
667 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
671 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
672 struct snd_soc_dai *cpu_dai)
675 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
676 struct ssp_device *ssp = priv->ssp;
680 case SNDRV_PCM_TRIGGER_RESUME:
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 pxa_ssp_set_running_bit(substream, ssp, 1);
685 val = pxa_ssp_read_reg(ssp, SSSR);
686 pxa_ssp_write_reg(ssp, SSSR, val);
688 case SNDRV_PCM_TRIGGER_START:
689 pxa_ssp_set_running_bit(substream, ssp, 1);
691 case SNDRV_PCM_TRIGGER_STOP:
692 pxa_ssp_set_running_bit(substream, ssp, 0);
694 case SNDRV_PCM_TRIGGER_SUSPEND:
695 pxa_ssp_disable(ssp);
697 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
698 pxa_ssp_set_running_bit(substream, ssp, 0);
710 static int pxa_ssp_probe(struct snd_soc_dai *dai)
712 struct device *dev = dai->dev;
713 struct ssp_priv *priv;
716 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
721 struct device_node *ssp_handle;
723 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
725 dev_err(dev, "unable to get 'port' phandle\n");
730 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
731 if (priv->ssp == NULL) {
736 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
737 if (priv->ssp == NULL) {
743 priv->dai_fmt = (unsigned int) -1;
744 snd_soc_dai_set_drvdata(dai, priv);
753 static int pxa_ssp_remove(struct snd_soc_dai *dai)
755 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
757 pxa_ssp_free(priv->ssp);
762 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
763 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
764 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
765 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
766 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
768 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
770 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
771 .startup = pxa_ssp_startup,
772 .shutdown = pxa_ssp_shutdown,
773 .trigger = pxa_ssp_trigger,
774 .hw_params = pxa_ssp_hw_params,
775 .set_sysclk = pxa_ssp_set_dai_sysclk,
776 .set_clkdiv = pxa_ssp_set_dai_clkdiv,
777 .set_pll = pxa_ssp_set_dai_pll,
778 .set_fmt = pxa_ssp_set_dai_fmt,
779 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
780 .set_tristate = pxa_ssp_set_dai_tristate,
783 static struct snd_soc_dai_driver pxa_ssp_dai = {
784 .probe = pxa_ssp_probe,
785 .remove = pxa_ssp_remove,
786 .suspend = pxa_ssp_suspend,
787 .resume = pxa_ssp_resume,
791 .rates = PXA_SSP_RATES,
792 .formats = PXA_SSP_FORMATS,
797 .rates = PXA_SSP_RATES,
798 .formats = PXA_SSP_FORMATS,
800 .ops = &pxa_ssp_dai_ops,
803 static const struct snd_soc_component_driver pxa_ssp_component = {
808 static const struct of_device_id pxa_ssp_of_ids[] = {
809 { .compatible = "mrvl,pxa-ssp-dai" },
814 static int asoc_ssp_probe(struct platform_device *pdev)
816 return snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
820 static int asoc_ssp_remove(struct platform_device *pdev)
822 snd_soc_unregister_component(&pdev->dev);
826 static struct platform_driver asoc_ssp_driver = {
828 .name = "pxa-ssp-dai",
829 .owner = THIS_MODULE,
830 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
833 .probe = asoc_ssp_probe,
834 .remove = asoc_ssp_remove,
837 module_platform_driver(asoc_ssp_driver);
839 /* Module information */
840 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
841 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
842 MODULE_LICENSE("GPL");