1 /* sound/soc/s3c24xx/s3c-ac97.c
3 * ALSA SoC Audio Layer - S3C AC97 Controller driver
4 * Evolved from s3c2443-ac97.c
6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
7 * Author: Jaswinder Singh <jassi.brar@samsung.com>
8 * Credits: Graeme Gregory, Sean Choi
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
21 #include <sound/soc.h>
23 #include <plat/regs-ac97.h>
25 #include <plat/audio.h>
30 #define AC_CMD_ADDR(x) (x << 16)
31 #define AC_CMD_DATA(x) (x & 0xffff)
33 struct s3c_ac97_info {
37 struct completion done;
39 static struct s3c_ac97_info s3c_ac97;
41 static struct s3c2410_dma_client s3c_dma_client_out = {
45 static struct s3c2410_dma_client s3c_dma_client_in = {
49 static struct s3c2410_dma_client s3c_dma_client_micin = {
53 static struct s3c_dma_params s3c_ac97_pcm_out = {
54 .client = &s3c_dma_client_out,
58 static struct s3c_dma_params s3c_ac97_pcm_in = {
59 .client = &s3c_dma_client_in,
63 static struct s3c_dma_params s3c_ac97_mic_in = {
64 .client = &s3c_dma_client_micin,
68 static void s3c_ac97_activate(struct snd_ac97 *ac97)
72 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
73 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
74 return; /* Return if already active */
76 INIT_COMPLETION(s3c_ac97.done);
78 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
79 ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
80 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
83 ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
84 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
87 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
88 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
89 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
91 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
92 printk(KERN_ERR "AC97: Unable to activate!");
95 static unsigned short s3c_ac97_read(struct snd_ac97 *ac97,
98 u32 ac_glbctrl, ac_codec_cmd;
101 mutex_lock(&s3c_ac97.lock);
103 s3c_ac97_activate(ac97);
105 INIT_COMPLETION(s3c_ac97.done);
107 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
108 ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
109 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
113 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
114 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
115 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
117 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
118 printk(KERN_ERR "AC97: Unable to read!");
120 stat = readl(s3c_ac97.regs + S3C_AC97_STAT);
121 addr = (stat >> 16) & 0x7f;
122 data = (stat & 0xffff);
125 printk(KERN_ERR "s3c-ac97: req addr = %02x, rep addr = %02x\n", reg, addr);
127 mutex_unlock(&s3c_ac97.lock);
129 return (unsigned short)data;
132 static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
135 u32 ac_glbctrl, ac_codec_cmd;
137 mutex_lock(&s3c_ac97.lock);
139 s3c_ac97_activate(ac97);
141 INIT_COMPLETION(s3c_ac97.done);
143 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
144 ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
145 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
149 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
150 ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
151 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
153 if (!wait_for_completion_timeout(&s3c_ac97.done, HZ))
154 printk(KERN_ERR "AC97: Unable to write!");
156 ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD);
157 ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
158 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD);
160 mutex_unlock(&s3c_ac97.lock);
163 static void s3c_ac97_cold_reset(struct snd_ac97 *ac97)
165 writel(S3C_AC97_GLBCTRL_COLDRESET,
166 s3c_ac97.regs + S3C_AC97_GLBCTRL);
169 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
173 static void s3c_ac97_warm_reset(struct snd_ac97 *ac97)
177 stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7;
178 if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE)
179 return; /* Return if already active */
181 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL);
184 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL);
187 s3c_ac97_activate(ac97);
190 static irqreturn_t s3c_ac97_irq(int irq, void *dev_id)
192 u32 ac_glbctrl, ac_glbstat;
194 ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT);
196 if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) {
198 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
199 ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
200 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
202 complete(&s3c_ac97.done);
205 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
206 ac_glbctrl |= (1<<30); /* Clear interrupt */
207 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
212 struct snd_ac97_bus_ops soc_ac97_ops = {
213 .read = s3c_ac97_read,
214 .write = s3c_ac97_write,
215 .warm_reset = s3c_ac97_warm_reset,
216 .reset = s3c_ac97_cold_reset,
218 EXPORT_SYMBOL_GPL(soc_ac97_ops);
220 static int s3c_ac97_hw_params(struct snd_pcm_substream *substream,
221 struct snd_pcm_hw_params *params,
222 struct snd_soc_dai *dai)
224 struct snd_soc_pcm_runtime *rtd = substream->private_data;
225 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
226 struct s3c_dma_params *dma_data;
228 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
229 dma_data = &s3c_ac97_pcm_out;
231 dma_data = &s3c_ac97_pcm_in;
233 snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
238 static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
239 struct snd_soc_dai *dai)
242 struct snd_soc_pcm_runtime *rtd = substream->private_data;
243 struct s3c_dma_params *dma_data =
244 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
246 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
247 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
248 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
250 ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
253 case SNDRV_PCM_TRIGGER_START:
254 case SNDRV_PCM_TRIGGER_RESUME:
255 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
256 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
257 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
259 ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
262 case SNDRV_PCM_TRIGGER_STOP:
263 case SNDRV_PCM_TRIGGER_SUSPEND:
264 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
268 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
270 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
275 static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream,
276 struct snd_pcm_hw_params *params,
277 struct snd_soc_dai *dai)
279 struct snd_soc_pcm_runtime *rtd = substream->private_data;
280 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
285 snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in);
290 static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream,
291 int cmd, struct snd_soc_dai *dai)
294 struct snd_soc_pcm_runtime *rtd = substream->private_data;
295 struct s3c_dma_params *dma_data =
296 snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
298 ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL);
299 ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK;
302 case SNDRV_PCM_TRIGGER_START:
303 case SNDRV_PCM_TRIGGER_RESUME:
304 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
305 ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA;
308 case SNDRV_PCM_TRIGGER_STOP:
309 case SNDRV_PCM_TRIGGER_SUSPEND:
310 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
314 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL);
316 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
321 static struct snd_soc_dai_ops s3c_ac97_dai_ops = {
322 .hw_params = s3c_ac97_hw_params,
323 .trigger = s3c_ac97_trigger,
326 static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = {
327 .hw_params = s3c_ac97_hw_mic_params,
328 .trigger = s3c_ac97_mic_trigger,
331 static struct snd_soc_dai_driver s3c_ac97_dai[] = {
332 [S3C_AC97_DAI_PCM] = {
336 .stream_name = "AC97 Playback",
339 .rates = SNDRV_PCM_RATE_8000_48000,
340 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
342 .stream_name = "AC97 Capture",
345 .rates = SNDRV_PCM_RATE_8000_48000,
346 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
347 .ops = &s3c_ac97_dai_ops,
349 [S3C_AC97_DAI_MIC] = {
350 .name = "s3c-ac97-mic",
353 .stream_name = "AC97 Mic Capture",
356 .rates = SNDRV_PCM_RATE_8000_48000,
357 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
358 .ops = &s3c_ac97_mic_dai_ops,
362 static __devinit int s3c_ac97_probe(struct platform_device *pdev)
364 struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res;
365 struct s3c_audio_pdata *ac97_pdata;
368 ac97_pdata = pdev->dev.platform_data;
369 if (!ac97_pdata || !ac97_pdata->cfg_gpio) {
370 dev_err(&pdev->dev, "cfg_gpio callback not provided!\n");
374 /* Check for availability of necessary resource */
375 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
377 dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n");
381 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
383 dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n");
387 dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2);
389 dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n");
393 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
395 dev_err(&pdev->dev, "Unable to get register resource\n");
399 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
401 dev_err(&pdev->dev, "AC97 IRQ not provided!\n");
405 if (!request_mem_region(mem_res->start,
406 resource_size(mem_res), "s3c-ac97")) {
407 dev_err(&pdev->dev, "Unable to request register region\n");
411 s3c_ac97_pcm_out.channel = dmatx_res->start;
412 s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
413 s3c_ac97_pcm_in.channel = dmarx_res->start;
414 s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA;
415 s3c_ac97_mic_in.channel = dmamic_res->start;
416 s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA;
418 init_completion(&s3c_ac97.done);
419 mutex_init(&s3c_ac97.lock);
421 s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res));
422 if (s3c_ac97.regs == NULL) {
423 dev_err(&pdev->dev, "Unable to ioremap register region\n");
428 s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
429 if (IS_ERR(s3c_ac97.ac97_clk)) {
430 dev_err(&pdev->dev, "s3c-ac97 failed to get ac97_clock\n");
434 clk_enable(s3c_ac97.ac97_clk);
436 if (ac97_pdata->cfg_gpio(pdev)) {
437 dev_err(&pdev->dev, "Unable to configure gpio\n");
442 ret = request_irq(irq_res->start, s3c_ac97_irq,
443 IRQF_DISABLED, "AC97", NULL);
445 printk(KERN_ERR "s3c-ac97: interrupt request failed.\n");
449 ret = snd_soc_register_dais(&pdev->dev, s3c_ac97_dai,
450 ARRAY_SIZE(s3c_ac97_dai));
457 free_irq(irq_res->start, NULL);
460 clk_disable(s3c_ac97.ac97_clk);
461 clk_put(s3c_ac97.ac97_clk);
463 iounmap(s3c_ac97.regs);
465 release_mem_region(mem_res->start, resource_size(mem_res));
470 static __devexit int s3c_ac97_remove(struct platform_device *pdev)
472 struct resource *mem_res, *irq_res;
474 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(s3c_ac97_dai));
476 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
478 free_irq(irq_res->start, NULL);
480 clk_disable(s3c_ac97.ac97_clk);
481 clk_put(s3c_ac97.ac97_clk);
483 iounmap(s3c_ac97.regs);
485 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
487 release_mem_region(mem_res->start, resource_size(mem_res));
492 static struct platform_driver s3c_ac97_driver = {
493 .probe = s3c_ac97_probe,
494 .remove = s3c_ac97_remove,
497 .owner = THIS_MODULE,
501 static int __init s3c_ac97_init(void)
503 return platform_driver_register(&s3c_ac97_driver);
505 module_init(s3c_ac97_init);
507 static void __exit s3c_ac97_exit(void)
509 platform_driver_unregister(&s3c_ac97_driver);
511 module_exit(s3c_ac97_exit);
513 MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
514 MODULE_DESCRIPTION("AC97 driver for the Samsung SoC");
515 MODULE_LICENSE("GPL");
516 MODULE_ALIAS("platform:s3c-ac97");