1 /* sound/soc/s3c24xx/s3c-i2c-v2.c
3 * ALSA Soc Audio Layer - I2S core for newer Samsung SoCs.
5 * Copyright (c) 2006 Wolfson Microelectronics PLC.
6 * Graeme Gregory graeme.gregory@wolfsonmicro.com
7 * linux@wolfsonmicro.com
9 * Copyright (c) 2008, 2007, 2004-2005 Simtec Electronics
10 * http://armlinux.simtec.co.uk/
11 * Ben Dooks <ben@simtec.co.uk>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/delay.h>
20 #include <linux/clk.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
27 #include <plat/regs-s3c2412-iis.h>
31 #include "s3c-i2s-v2.h"
34 #undef S3C_IIS_V2_SUPPORTED
36 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
37 #define S3C_IIS_V2_SUPPORTED
40 #ifdef CONFIG_PLAT_S3C64XX
41 #define S3C_IIS_V2_SUPPORTED
44 #ifndef S3C_IIS_V2_SUPPORTED
45 #error Unsupported CPU model
48 #define S3C2412_I2S_DEBUG_CON 0
50 static inline struct s3c_i2sv2_info *to_info(struct snd_soc_dai *cpu_dai)
52 return cpu_dai->private_data;
55 #define bit_set(v, b) (((v) & (b)) ? 1 : 0)
57 #if S3C2412_I2S_DEBUG_CON
58 static void dbg_showcon(const char *fn, u32 con)
60 printk(KERN_DEBUG "%s: LRI=%d, TXFEMPT=%d, RXFEMPT=%d, TXFFULL=%d, RXFFULL=%d\n", fn,
61 bit_set(con, S3C2412_IISCON_LRINDEX),
62 bit_set(con, S3C2412_IISCON_TXFIFO_EMPTY),
63 bit_set(con, S3C2412_IISCON_RXFIFO_EMPTY),
64 bit_set(con, S3C2412_IISCON_TXFIFO_FULL),
65 bit_set(con, S3C2412_IISCON_RXFIFO_FULL));
67 printk(KERN_DEBUG "%s: PAUSE: TXDMA=%d, RXDMA=%d, TXCH=%d, RXCH=%d\n",
69 bit_set(con, S3C2412_IISCON_TXDMA_PAUSE),
70 bit_set(con, S3C2412_IISCON_RXDMA_PAUSE),
71 bit_set(con, S3C2412_IISCON_TXCH_PAUSE),
72 bit_set(con, S3C2412_IISCON_RXCH_PAUSE));
73 printk(KERN_DEBUG "%s: ACTIVE: TXDMA=%d, RXDMA=%d, IIS=%d\n", fn,
74 bit_set(con, S3C2412_IISCON_TXDMA_ACTIVE),
75 bit_set(con, S3C2412_IISCON_RXDMA_ACTIVE),
76 bit_set(con, S3C2412_IISCON_IIS_ACTIVE));
79 static inline void dbg_showcon(const char *fn, u32 con)
85 /* Turn on or off the transmission path. */
86 static void s3c2412_snd_txctrl(struct s3c_i2sv2_info *i2s, int on)
88 void __iomem *regs = i2s->regs;
91 pr_debug("%s(%d)\n", __func__, on);
93 fic = readl(regs + S3C2412_IISFIC);
94 con = readl(regs + S3C2412_IISCON);
95 mod = readl(regs + S3C2412_IISMOD);
97 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
100 con |= S3C2412_IISCON_TXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
101 con &= ~S3C2412_IISCON_TXDMA_PAUSE;
102 con &= ~S3C2412_IISCON_TXCH_PAUSE;
104 switch (mod & S3C2412_IISMOD_MODE_MASK) {
105 case S3C2412_IISMOD_MODE_TXONLY:
106 case S3C2412_IISMOD_MODE_TXRX:
107 /* do nothing, we are in the right mode */
110 case S3C2412_IISMOD_MODE_RXONLY:
111 mod &= ~S3C2412_IISMOD_MODE_MASK;
112 mod |= S3C2412_IISMOD_MODE_TXRX;
116 dev_err(i2s->dev, "TXEN: Invalid MODE %x in IISMOD\n",
117 mod & S3C2412_IISMOD_MODE_MASK);
121 writel(con, regs + S3C2412_IISCON);
122 writel(mod, regs + S3C2412_IISMOD);
124 /* Note, we do not have any indication that the FIFO problems
125 * tha the S3C2410/2440 had apply here, so we should be able
126 * to disable the DMA and TX without resetting the FIFOS.
129 con |= S3C2412_IISCON_TXDMA_PAUSE;
130 con |= S3C2412_IISCON_TXCH_PAUSE;
131 con &= ~S3C2412_IISCON_TXDMA_ACTIVE;
133 switch (mod & S3C2412_IISMOD_MODE_MASK) {
134 case S3C2412_IISMOD_MODE_TXRX:
135 mod &= ~S3C2412_IISMOD_MODE_MASK;
136 mod |= S3C2412_IISMOD_MODE_RXONLY;
139 case S3C2412_IISMOD_MODE_TXONLY:
140 mod &= ~S3C2412_IISMOD_MODE_MASK;
141 con &= ~S3C2412_IISCON_IIS_ACTIVE;
145 dev_err(i2s->dev, "TXDIS: Invalid MODE %x in IISMOD\n",
146 mod & S3C2412_IISMOD_MODE_MASK);
150 writel(mod, regs + S3C2412_IISMOD);
151 writel(con, regs + S3C2412_IISCON);
154 fic = readl(regs + S3C2412_IISFIC);
155 dbg_showcon(__func__, con);
156 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
159 static void s3c2412_snd_rxctrl(struct s3c_i2sv2_info *i2s, int on)
161 void __iomem *regs = i2s->regs;
164 pr_debug("%s(%d)\n", __func__, on);
166 fic = readl(regs + S3C2412_IISFIC);
167 con = readl(regs + S3C2412_IISCON);
168 mod = readl(regs + S3C2412_IISMOD);
170 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
173 con |= S3C2412_IISCON_RXDMA_ACTIVE | S3C2412_IISCON_IIS_ACTIVE;
174 con &= ~S3C2412_IISCON_RXDMA_PAUSE;
175 con &= ~S3C2412_IISCON_RXCH_PAUSE;
177 switch (mod & S3C2412_IISMOD_MODE_MASK) {
178 case S3C2412_IISMOD_MODE_TXRX:
179 case S3C2412_IISMOD_MODE_RXONLY:
180 /* do nothing, we are in the right mode */
183 case S3C2412_IISMOD_MODE_TXONLY:
184 mod &= ~S3C2412_IISMOD_MODE_MASK;
185 mod |= S3C2412_IISMOD_MODE_TXRX;
189 dev_err(i2s->dev, "RXEN: Invalid MODE %x in IISMOD\n",
190 mod & S3C2412_IISMOD_MODE_MASK);
193 writel(mod, regs + S3C2412_IISMOD);
194 writel(con, regs + S3C2412_IISCON);
196 /* See txctrl notes on FIFOs. */
198 con &= ~S3C2412_IISCON_RXDMA_ACTIVE;
199 con |= S3C2412_IISCON_RXDMA_PAUSE;
200 con |= S3C2412_IISCON_RXCH_PAUSE;
202 switch (mod & S3C2412_IISMOD_MODE_MASK) {
203 case S3C2412_IISMOD_MODE_RXONLY:
204 con &= ~S3C2412_IISCON_IIS_ACTIVE;
205 mod &= ~S3C2412_IISMOD_MODE_MASK;
208 case S3C2412_IISMOD_MODE_TXRX:
209 mod &= ~S3C2412_IISMOD_MODE_MASK;
210 mod |= S3C2412_IISMOD_MODE_TXONLY;
214 dev_err(i2s->dev, "RXDIS: Invalid MODE %x in IISMOD\n",
215 mod & S3C2412_IISMOD_MODE_MASK);
218 writel(con, regs + S3C2412_IISCON);
219 writel(mod, regs + S3C2412_IISMOD);
222 fic = readl(regs + S3C2412_IISFIC);
223 pr_debug("%s: IIS: CON=%x MOD=%x FIC=%x\n", __func__, con, mod, fic);
226 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
229 * Wait for the LR signal to allow synchronisation to the L/R clock
230 * from the codec. May only be needed for slave mode.
232 static int s3c2412_snd_lrsync(struct s3c_i2sv2_info *i2s)
235 unsigned long loops = msecs_to_loops(5);
237 pr_debug("Entered %s\n", __func__);
240 iiscon = readl(i2s->regs + S3C2412_IISCON);
241 if (iiscon & S3C2412_IISCON_LRINDEX)
248 printk(KERN_ERR "%s: timeout\n", __func__);
256 * Set S3C2412 I2S DAI format
258 static int s3c2412_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
261 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
264 pr_debug("Entered %s\n", __func__);
266 iismod = readl(i2s->regs + S3C2412_IISMOD);
267 pr_debug("hw_params r: IISMOD: %x \n", iismod);
269 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
270 #define IISMOD_MASTER_MASK S3C2412_IISMOD_MASTER_MASK
271 #define IISMOD_SLAVE S3C2412_IISMOD_SLAVE
272 #define IISMOD_MASTER S3C2412_IISMOD_MASTER_INTERNAL
275 #if defined(CONFIG_PLAT_S3C64XX)
276 /* From Rev1.1 datasheet, we have two master and two slave modes:
278 * 00 = master mode, fed from PCLK
279 * 01 = master mode, fed from CLKAUDIO
280 * 10 = slave mode, using PCLK
281 * 11 = slave mode, using I2SCLK
283 #define IISMOD_MASTER_MASK (1 << 11)
284 #define IISMOD_SLAVE (1 << 11)
285 #define IISMOD_MASTER (0 << 11)
288 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
289 case SND_SOC_DAIFMT_CBM_CFM:
291 iismod &= ~IISMOD_MASTER_MASK;
292 iismod |= IISMOD_SLAVE;
294 case SND_SOC_DAIFMT_CBS_CFS:
296 iismod &= ~IISMOD_MASTER_MASK;
297 iismod |= IISMOD_MASTER;
300 pr_err("unknwon master/slave format\n");
304 iismod &= ~S3C2412_IISMOD_SDF_MASK;
306 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
307 case SND_SOC_DAIFMT_RIGHT_J:
308 iismod |= S3C2412_IISMOD_LR_RLOW;
309 iismod |= S3C2412_IISMOD_SDF_MSB;
311 case SND_SOC_DAIFMT_LEFT_J:
312 iismod |= S3C2412_IISMOD_LR_RLOW;
313 iismod |= S3C2412_IISMOD_SDF_LSB;
315 case SND_SOC_DAIFMT_I2S:
316 iismod &= ~S3C2412_IISMOD_LR_RLOW;
317 iismod |= S3C2412_IISMOD_SDF_IIS;
320 pr_err("Unknown data format\n");
324 writel(iismod, i2s->regs + S3C2412_IISMOD);
325 pr_debug("hw_params w: IISMOD: %x \n", iismod);
329 static int s3c2412_i2s_hw_params(struct snd_pcm_substream *substream,
330 struct snd_pcm_hw_params *params,
331 struct snd_soc_dai *socdai)
333 struct snd_soc_pcm_runtime *rtd = substream->private_data;
334 struct snd_soc_dai_link *dai = rtd->dai;
335 struct s3c_i2sv2_info *i2s = to_info(dai->cpu_dai);
338 pr_debug("Entered %s\n", __func__);
340 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341 dai->cpu_dai->dma_data = i2s->dma_playback;
343 dai->cpu_dai->dma_data = i2s->dma_capture;
345 /* Working copies of register */
346 iismod = readl(i2s->regs + S3C2412_IISMOD);
347 pr_debug("%s: r: IISMOD: %x\n", __func__, iismod);
349 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
350 switch (params_format(params)) {
351 case SNDRV_PCM_FORMAT_S8:
352 iismod |= S3C2412_IISMOD_8BIT;
354 case SNDRV_PCM_FORMAT_S16_LE:
355 iismod &= ~S3C2412_IISMOD_8BIT;
360 #ifdef CONFIG_PLAT_S3C64XX
361 iismod &= ~(S3C64XX_IISMOD_BLC_MASK | S3C2412_IISMOD_BCLK_MASK);
363 switch (params_format(params)) {
364 case SNDRV_PCM_FORMAT_S8:
365 /* 8 bit sample, 16fs BCLK */
366 iismod |= (S3C64XX_IISMOD_BLC_8BIT | S3C2412_IISMOD_BCLK_16FS);
368 case SNDRV_PCM_FORMAT_S16_LE:
369 /* 16 bit sample, 32fs BCLK */
371 case SNDRV_PCM_FORMAT_S24_LE:
372 /* 24 bit sample, 48fs BCLK */
373 iismod |= (S3C64XX_IISMOD_BLC_24BIT | S3C2412_IISMOD_BCLK_48FS);
378 writel(iismod, i2s->regs + S3C2412_IISMOD);
379 pr_debug("%s: w: IISMOD: %x\n", __func__, iismod);
383 static int s3c2412_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
384 struct snd_soc_dai *dai)
386 struct snd_soc_pcm_runtime *rtd = substream->private_data;
387 struct s3c_i2sv2_info *i2s = to_info(rtd->dai->cpu_dai);
388 int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
391 int channel = ((struct s3c_dma_params *)
392 rtd->dai->cpu_dai->dma_data)->channel;
394 pr_debug("Entered %s\n", __func__);
397 case SNDRV_PCM_TRIGGER_START:
398 /* On start, ensure that the FIFOs are cleared and reset. */
400 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH,
401 i2s->regs + S3C2412_IISFIC);
403 /* clear again, just in case */
404 writel(0x0, i2s->regs + S3C2412_IISFIC);
406 case SNDRV_PCM_TRIGGER_RESUME:
407 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
409 ret = s3c2412_snd_lrsync(i2s);
414 local_irq_save(irqs);
417 s3c2412_snd_rxctrl(i2s, 1);
419 s3c2412_snd_txctrl(i2s, 1);
421 local_irq_restore(irqs);
424 * Load the next buffer to DMA to meet the reqirement
425 * of the auto reload mechanism of S3C24XX.
426 * This call won't bother S3C64XX.
428 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STARTED);
432 case SNDRV_PCM_TRIGGER_STOP:
433 case SNDRV_PCM_TRIGGER_SUSPEND:
434 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
435 local_irq_save(irqs);
438 s3c2412_snd_rxctrl(i2s, 0);
440 s3c2412_snd_txctrl(i2s, 0);
442 local_irq_restore(irqs);
454 * Set S3C2412 Clock dividers
456 static int s3c2412_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
459 struct s3c_i2sv2_info *i2s = to_info(cpu_dai);
462 pr_debug("%s(%p, %d, %d)\n", __func__, cpu_dai, div_id, div);
465 case S3C_I2SV2_DIV_BCLK:
468 div = S3C2412_IISMOD_BCLK_16FS;
472 div = S3C2412_IISMOD_BCLK_32FS;
476 div = S3C2412_IISMOD_BCLK_24FS;
480 div = S3C2412_IISMOD_BCLK_48FS;
487 reg = readl(i2s->regs + S3C2412_IISMOD);
488 reg &= ~S3C2412_IISMOD_BCLK_MASK;
489 writel(reg | div, i2s->regs + S3C2412_IISMOD);
491 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
494 case S3C_I2SV2_DIV_RCLK:
497 div = S3C2412_IISMOD_RCLK_256FS;
501 div = S3C2412_IISMOD_RCLK_384FS;
505 div = S3C2412_IISMOD_RCLK_512FS;
509 div = S3C2412_IISMOD_RCLK_768FS;
516 reg = readl(i2s->regs + S3C2412_IISMOD);
517 reg &= ~S3C2412_IISMOD_RCLK_MASK;
518 writel(reg | div, i2s->regs + S3C2412_IISMOD);
519 pr_debug("%s: MOD=%08x\n", __func__, readl(i2s->regs + S3C2412_IISMOD));
522 case S3C_I2SV2_DIV_PRESCALER:
524 writel((div << 8) | S3C2412_IISPSR_PSREN,
525 i2s->regs + S3C2412_IISPSR);
527 writel(0x0, i2s->regs + S3C2412_IISPSR);
529 pr_debug("%s: PSR=%08x\n", __func__, readl(i2s->regs + S3C2412_IISPSR));
539 static snd_pcm_sframes_t s3c2412_i2s_delay(struct snd_pcm_substream *substream,
540 struct snd_soc_dai *dai)
542 struct s3c_i2sv2_info *i2s = to_info(dai);
543 u32 reg = readl(i2s->regs + S3C2412_IISFIC);
544 snd_pcm_sframes_t delay;
546 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
547 delay = S3C2412_IISFIC_TXCOUNT(reg);
549 delay = S3C2412_IISFIC_RXCOUNT(reg);
554 /* default table of all avaialable root fs divisors */
555 static unsigned int iis_fs_tab[] = { 256, 512, 384, 768 };
557 int s3c_i2sv2_iis_calc_rate(struct s3c_i2sv2_rate_calc *info,
559 unsigned int rate, struct clk *clk)
561 unsigned long clkrate = clk_get_rate(clk);
567 signed int deviation = 0;
568 unsigned int best_fs = 0;
569 unsigned int best_div = 0;
570 unsigned int best_rate = 0;
571 unsigned int best_deviation = INT_MAX;
573 pr_debug("Input clock rate %ldHz\n", clkrate);
578 for (fs = 0; fs < ARRAY_SIZE(iis_fs_tab); fs++) {
579 fsdiv = iis_fs_tab[fs];
581 fsclk = clkrate / fsdiv;
584 if ((fsclk % rate) > (rate / 2))
590 actual = clkrate / (fsdiv * div);
591 deviation = actual - rate;
593 printk(KERN_DEBUG "%ufs: div %u => result %u, deviation %d\n",
594 fsdiv, div, actual, deviation);
596 deviation = abs(deviation);
598 if (deviation < best_deviation) {
602 best_deviation = deviation;
609 printk(KERN_DEBUG "best: fs=%u, div=%u, rate=%u\n",
610 best_fs, best_div, best_rate);
612 info->fs_div = best_fs;
613 info->clk_div = best_div;
617 EXPORT_SYMBOL_GPL(s3c_i2sv2_iis_calc_rate);
619 int s3c_i2sv2_probe(struct platform_device *pdev,
620 struct snd_soc_dai *dai,
621 struct s3c_i2sv2_info *i2s,
624 struct device *dev = &pdev->dev;
629 /* record our i2s structure for later use in the callbacks */
630 dai->private_data = i2s;
633 struct resource *res = platform_get_resource(pdev,
637 dev_err(dev, "Unable to get register resource\n");
641 if (!request_mem_region(res->start, resource_size(res),
643 dev_err(dev, "Unable to request register region\n");
650 i2s->regs = ioremap(base, 0x100);
651 if (i2s->regs == NULL) {
652 dev_err(dev, "cannot ioremap registers\n");
656 i2s->iis_pclk = clk_get(dev, "iis");
657 if (IS_ERR(i2s->iis_pclk)) {
658 dev_err(dev, "failed to get iis_clock\n");
663 clk_enable(i2s->iis_pclk);
665 /* Mark ourselves as in TXRX mode so we can run through our cleanup
666 * process without warnings. */
667 iismod = readl(i2s->regs + S3C2412_IISMOD);
668 iismod |= S3C2412_IISMOD_MODE_TXRX;
669 writel(iismod, i2s->regs + S3C2412_IISMOD);
670 s3c2412_snd_txctrl(i2s, 0);
671 s3c2412_snd_rxctrl(i2s, 0);
675 EXPORT_SYMBOL_GPL(s3c_i2sv2_probe);
678 static int s3c2412_i2s_suspend(struct snd_soc_dai *dai)
680 struct s3c_i2sv2_info *i2s = to_info(dai);
684 i2s->suspend_iismod = readl(i2s->regs + S3C2412_IISMOD);
685 i2s->suspend_iiscon = readl(i2s->regs + S3C2412_IISCON);
686 i2s->suspend_iispsr = readl(i2s->regs + S3C2412_IISPSR);
688 /* some basic suspend checks */
690 iismod = readl(i2s->regs + S3C2412_IISMOD);
692 if (iismod & S3C2412_IISCON_RXDMA_ACTIVE)
693 pr_warning("%s: RXDMA active?\n", __func__);
695 if (iismod & S3C2412_IISCON_TXDMA_ACTIVE)
696 pr_warning("%s: TXDMA active?\n", __func__);
698 if (iismod & S3C2412_IISCON_IIS_ACTIVE)
699 pr_warning("%s: IIS active\n", __func__);
705 static int s3c2412_i2s_resume(struct snd_soc_dai *dai)
707 struct s3c_i2sv2_info *i2s = to_info(dai);
709 pr_info("dai_active %d, IISMOD %08x, IISCON %08x\n",
710 dai->active, i2s->suspend_iismod, i2s->suspend_iiscon);
713 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON);
714 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD);
715 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR);
717 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH,
718 i2s->regs + S3C2412_IISFIC);
721 writel(0x0, i2s->regs + S3C2412_IISFIC);
727 #define s3c2412_i2s_suspend NULL
728 #define s3c2412_i2s_resume NULL
731 int s3c_i2sv2_register_dai(struct snd_soc_dai *dai)
733 struct snd_soc_dai_ops *ops = dai->ops;
735 ops->trigger = s3c2412_i2s_trigger;
736 ops->hw_params = s3c2412_i2s_hw_params;
737 ops->set_fmt = s3c2412_i2s_set_fmt;
738 ops->set_clkdiv = s3c2412_i2s_set_clkdiv;
740 /* Allow overriding by (for example) IISv4 */
742 ops->delay = s3c2412_i2s_delay;
744 dai->suspend = s3c2412_i2s_suspend;
745 dai->resume = s3c2412_i2s_resume;
747 return snd_soc_register_dai(dai);
749 EXPORT_SYMBOL_GPL(s3c_i2sv2_register_dai);
751 MODULE_LICENSE("GPL");