2 * s3c24xx-i2s.c -- ALSA Soc Audio Layer
4 * (c) 2006 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
7 * Copyright 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/delay.h>
18 #include <linux/clk.h>
20 #include <linux/gpio.h>
22 #include <sound/soc.h>
23 #include <sound/pcm_params.h>
25 #include <mach/regs-gpio.h>
27 #include <plat/regs-iis.h>
30 #include "s3c24xx-i2s.h"
32 static struct s3c2410_dma_client s3c24xx_dma_client_out = {
33 .name = "I2S PCM Stereo out"
36 static struct s3c2410_dma_client s3c24xx_dma_client_in = {
37 .name = "I2S PCM Stereo in"
40 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_out = {
41 .client = &s3c24xx_dma_client_out,
42 .channel = DMACH_I2S_OUT,
43 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
47 static struct s3c_dma_params s3c24xx_i2s_pcm_stereo_in = {
48 .client = &s3c24xx_dma_client_in,
49 .channel = DMACH_I2S_IN,
50 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
54 struct s3c24xx_i2s_info {
62 static struct s3c24xx_i2s_info s3c24xx_i2s;
64 static void s3c24xx_snd_txctrl(int on)
70 pr_debug("Entered %s\n", __func__);
72 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
73 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
74 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
76 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
79 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
80 iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
81 iiscon &= ~S3C2410_IISCON_TXIDLE;
82 iismod |= S3C2410_IISMOD_TXMODE;
84 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
85 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
86 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
88 /* note, we have to disable the FIFOs otherwise bad things
89 * seem to happen when the DMA stops. According to the
90 * Samsung supplied kernel, this should allow the DMA
91 * engine and FIFOs to reset. If this isn't allowed, the
92 * DMA engine will simply freeze randomly.
95 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
96 iisfcon &= ~S3C2410_IISFCON_TXDMA;
97 iiscon |= S3C2410_IISCON_TXIDLE;
98 iiscon &= ~S3C2410_IISCON_TXDMAEN;
99 iismod &= ~S3C2410_IISMOD_TXMODE;
101 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
102 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
103 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
106 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
109 static void s3c24xx_snd_rxctrl(int on)
115 pr_debug("Entered %s\n", __func__);
117 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
118 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
119 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
121 pr_debug("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
124 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
125 iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
126 iiscon &= ~S3C2410_IISCON_RXIDLE;
127 iismod |= S3C2410_IISMOD_RXMODE;
129 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
130 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
131 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
133 /* note, we have to disable the FIFOs otherwise bad things
134 * seem to happen when the DMA stops. According to the
135 * Samsung supplied kernel, this should allow the DMA
136 * engine and FIFOs to reset. If this isn't allowed, the
137 * DMA engine will simply freeze randomly.
140 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
141 iisfcon &= ~S3C2410_IISFCON_RXDMA;
142 iiscon |= S3C2410_IISCON_RXIDLE;
143 iiscon &= ~S3C2410_IISCON_RXDMAEN;
144 iismod &= ~S3C2410_IISMOD_RXMODE;
146 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
147 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
148 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
151 pr_debug("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
155 * Wait for the LR signal to allow synchronisation to the L/R clock
156 * from the codec. May only be needed for slave mode.
158 static int s3c24xx_snd_lrsync(void)
161 int timeout = 50; /* 5ms */
163 pr_debug("Entered %s\n", __func__);
166 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
167 if (iiscon & S3C2410_IISCON_LRINDEX)
179 * Check whether CPU is the master or slave
181 static inline int s3c24xx_snd_is_clkmaster(void)
183 pr_debug("Entered %s\n", __func__);
185 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
189 * Set S3C24xx I2S DAI format
191 static int s3c24xx_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
196 pr_debug("Entered %s\n", __func__);
198 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
199 pr_debug("hw_params r: IISMOD: %x \n", iismod);
201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
202 case SND_SOC_DAIFMT_CBM_CFM:
203 iismod |= S3C2410_IISMOD_SLAVE;
205 case SND_SOC_DAIFMT_CBS_CFS:
206 iismod &= ~S3C2410_IISMOD_SLAVE;
212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
213 case SND_SOC_DAIFMT_LEFT_J:
214 iismod |= S3C2410_IISMOD_MSB;
216 case SND_SOC_DAIFMT_I2S:
217 iismod &= ~S3C2410_IISMOD_MSB;
223 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
224 pr_debug("hw_params w: IISMOD: %x \n", iismod);
228 static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
229 struct snd_pcm_hw_params *params,
230 struct snd_soc_dai *dai)
232 struct snd_soc_pcm_runtime *rtd = substream->private_data;
233 struct s3c_dma_params *dma_data;
236 pr_debug("Entered %s\n", __func__);
238 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
239 dma_data = &s3c24xx_i2s_pcm_stereo_out;
241 dma_data = &s3c24xx_i2s_pcm_stereo_in;
243 snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
245 /* Working copies of register */
246 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
247 pr_debug("hw_params r: IISMOD: %x\n", iismod);
249 switch (params_format(params)) {
250 case SNDRV_PCM_FORMAT_S8:
251 iismod &= ~S3C2410_IISMOD_16BIT;
252 dma_data->dma_size = 1;
254 case SNDRV_PCM_FORMAT_S16_LE:
255 iismod |= S3C2410_IISMOD_16BIT;
256 dma_data->dma_size = 2;
262 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
263 pr_debug("hw_params w: IISMOD: %x\n", iismod);
267 static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
268 struct snd_soc_dai *dai)
271 struct s3c_dma_params *dma_data =
272 snd_soc_dai_get_dma_data(dai, substream);
274 pr_debug("Entered %s\n", __func__);
277 case SNDRV_PCM_TRIGGER_START:
278 case SNDRV_PCM_TRIGGER_RESUME:
279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
280 if (!s3c24xx_snd_is_clkmaster()) {
281 ret = s3c24xx_snd_lrsync();
286 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
287 s3c24xx_snd_rxctrl(1);
289 s3c24xx_snd_txctrl(1);
291 s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED);
293 case SNDRV_PCM_TRIGGER_STOP:
294 case SNDRV_PCM_TRIGGER_SUSPEND:
295 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
296 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
297 s3c24xx_snd_rxctrl(0);
299 s3c24xx_snd_txctrl(0);
311 * Set S3C24xx Clock source
313 static int s3c24xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
314 int clk_id, unsigned int freq, int dir)
316 u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
318 pr_debug("Entered %s\n", __func__);
320 iismod &= ~S3C2440_IISMOD_MPLL;
323 case S3C24XX_CLKSRC_PCLK:
325 case S3C24XX_CLKSRC_MPLL:
326 iismod |= S3C2440_IISMOD_MPLL;
332 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
337 * Set S3C24xx Clock dividers
339 static int s3c24xx_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
344 pr_debug("Entered %s\n", __func__);
347 case S3C24XX_DIV_BCLK:
348 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
349 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
351 case S3C24XX_DIV_MCLK:
352 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
353 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
355 case S3C24XX_DIV_PRESCALER:
356 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
357 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
358 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
368 * To avoid duplicating clock code, allow machine driver to
369 * get the clockrate from here.
371 u32 s3c24xx_i2s_get_clockrate(void)
373 return clk_get_rate(s3c24xx_i2s.iis_clk);
375 EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
377 static int s3c24xx_i2s_probe(struct snd_soc_dai *dai)
379 pr_debug("Entered %s\n", __func__);
381 s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
382 if (s3c24xx_i2s.regs == NULL)
385 s3c24xx_i2s.iis_clk = clk_get(dai->dev, "iis");
386 if (IS_ERR(s3c24xx_i2s.iis_clk)) {
387 pr_err("failed to get iis_clock\n");
388 iounmap(s3c24xx_i2s.regs);
389 return PTR_ERR(s3c24xx_i2s.iis_clk);
391 clk_enable(s3c24xx_i2s.iis_clk);
393 /* Configure the I2S pins in correct mode */
394 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
395 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
396 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
397 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
398 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
400 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
402 s3c24xx_snd_txctrl(0);
403 s3c24xx_snd_rxctrl(0);
409 static int s3c24xx_i2s_suspend(struct snd_soc_dai *cpu_dai)
411 pr_debug("Entered %s\n", __func__);
413 s3c24xx_i2s.iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
414 s3c24xx_i2s.iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
415 s3c24xx_i2s.iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
416 s3c24xx_i2s.iispsr = readl(s3c24xx_i2s.regs + S3C2410_IISPSR);
418 clk_disable(s3c24xx_i2s.iis_clk);
423 static int s3c24xx_i2s_resume(struct snd_soc_dai *cpu_dai)
425 pr_debug("Entered %s\n", __func__);
426 clk_enable(s3c24xx_i2s.iis_clk);
428 writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
429 writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
430 writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
431 writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR);
436 #define s3c24xx_i2s_suspend NULL
437 #define s3c24xx_i2s_resume NULL
441 #define S3C24XX_I2S_RATES \
442 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
443 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
444 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
446 static struct snd_soc_dai_ops s3c24xx_i2s_dai_ops = {
447 .trigger = s3c24xx_i2s_trigger,
448 .hw_params = s3c24xx_i2s_hw_params,
449 .set_fmt = s3c24xx_i2s_set_fmt,
450 .set_clkdiv = s3c24xx_i2s_set_clkdiv,
451 .set_sysclk = s3c24xx_i2s_set_sysclk,
454 static struct snd_soc_dai_driver s3c24xx_i2s_dai = {
455 .probe = s3c24xx_i2s_probe,
456 .suspend = s3c24xx_i2s_suspend,
457 .resume = s3c24xx_i2s_resume,
461 .rates = S3C24XX_I2S_RATES,
462 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
466 .rates = S3C24XX_I2S_RATES,
467 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
468 .ops = &s3c24xx_i2s_dai_ops,
471 static __devinit int s3c24xx_iis_dev_probe(struct platform_device *pdev)
473 return snd_soc_register_dai(&pdev->dev, &s3c24xx_i2s_dai);
476 static __devexit int s3c24xx_iis_dev_remove(struct platform_device *pdev)
478 snd_soc_unregister_dai(&pdev->dev);
482 static struct platform_driver s3c24xx_iis_driver = {
483 .probe = s3c24xx_iis_dev_probe,
484 .remove = __devexit_p(s3c24xx_iis_dev_remove),
486 .name = "s3c24xx-iis",
487 .owner = THIS_MODULE,
491 static int __init s3c24xx_i2s_init(void)
493 return platform_driver_register(&s3c24xx_iis_driver);
495 module_init(s3c24xx_i2s_init);
497 static void __exit s3c24xx_i2s_exit(void)
499 platform_driver_unregister(&s3c24xx_iis_driver);
501 module_exit(s3c24xx_i2s_exit);
503 /* Module information */
504 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
505 MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
506 MODULE_LICENSE("GPL");
507 MODULE_ALIAS("platform:s3c24xx-iis");