2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
85 #define BP (1 << 4) /* Fix the signal of Biphase output */
86 #define SE (1 << 0) /* Fix the master clock */
89 #define B_CLK 0x00000010
90 #define A_CLK 0x00000001
92 /* IO SHIFT / MACRO */
97 #define AB_IO(param, shift) (param << shift)
100 #define PBSR (1 << 12) /* Port B Software Reset */
101 #define PASR (1 << 8) /* Port A Software Reset */
102 #define IR (1 << 4) /* Interrupt Reset */
103 #define FSISR (1 << 0) /* Software Reset */
106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */
110 #define FIFO_SZ_MASK 0x7
112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
117 * FSI driver use below type name for variable
119 * xxx_len : data length
120 * xxx_width : data width
121 * xxx_offset : data offset
122 * xxx_num : number of data
130 struct snd_pcm_substream *substream;
145 struct fsi_master *master;
148 struct fsi_stream playback;
149 struct fsi_stream capture;
167 struct fsi_priv fsia;
168 struct fsi_priv fsib;
169 struct fsi_core *core;
170 struct sh_fsi_platform_info *info;
175 * basic read write function
178 static void __fsi_reg_write(u32 reg, u32 data)
180 /* valid data area is 24bit */
183 __raw_writel(data, reg);
186 static u32 __fsi_reg_read(u32 reg)
188 return __raw_readl(reg);
191 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
193 u32 val = __fsi_reg_read(reg);
198 __fsi_reg_write(reg, val);
201 #define fsi_reg_write(p, r, d)\
202 __fsi_reg_write((u32)(p->base + REG_##r), d)
204 #define fsi_reg_read(p, r)\
205 __fsi_reg_read((u32)(p->base + REG_##r))
207 #define fsi_reg_mask_set(p, r, m, d)\
208 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
210 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
211 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
212 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
217 spin_lock_irqsave(&master->lock, flags);
218 ret = __fsi_reg_read((u32)(master->base + reg));
219 spin_unlock_irqrestore(&master->lock, flags);
224 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
225 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
226 static void _fsi_master_mask_set(struct fsi_master *master,
227 u32 reg, u32 mask, u32 data)
231 spin_lock_irqsave(&master->lock, flags);
232 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
233 spin_unlock_irqrestore(&master->lock, flags);
240 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
245 static int fsi_is_port_a(struct fsi_priv *fsi)
247 return fsi->master->base == fsi->base;
250 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
252 struct snd_soc_pcm_runtime *rtd = substream->private_data;
257 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
259 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
262 return &master->fsia;
264 return &master->fsib;
267 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
269 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
272 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
274 int is_porta = fsi_is_port_a(fsi);
275 struct fsi_master *master = fsi_get_master(fsi);
277 return is_porta ? master->info->porta_flags :
278 master->info->portb_flags;
281 static inline int fsi_stream_is_play(int stream)
283 return stream == SNDRV_PCM_STREAM_PLAYBACK;
286 static inline int fsi_is_play(struct snd_pcm_substream *substream)
288 return fsi_stream_is_play(substream->stream);
291 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
294 return is_play ? &fsi->playback : &fsi->capture;
297 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
299 int is_porta = fsi_is_port_a(fsi);
303 shift = is_play ? AO_SHIFT : AI_SHIFT;
305 shift = is_play ? BO_SHIFT : BI_SHIFT;
310 static void fsi_stream_push(struct fsi_priv *fsi,
312 struct snd_pcm_substream *substream,
316 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
318 io->substream = substream;
319 io->buff_len = buffer_len;
321 io->period_len = period_len;
323 io->oerr_num = -1; /* ignore 1st err */
324 io->uerr_num = -1; /* ignore 1st err */
327 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
329 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
330 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
333 if (io->oerr_num > 0)
334 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
336 if (io->uerr_num > 0)
337 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
339 io->substream = NULL;
348 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
354 fsi_reg_read(fsi, DOFF_ST) :
355 fsi_reg_read(fsi, DIFF_ST);
357 data_num = 0x1ff & (status >> 8);
358 data_num *= fsi->chan_num;
363 static int fsi_len2num(int len, int width)
368 #define fsi_num2offset(a, b) fsi_num2len(a, b)
369 static int fsi_num2len(int num, int width)
374 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
376 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
377 struct snd_pcm_substream *substream = io->substream;
378 struct snd_pcm_runtime *runtime = substream->runtime;
380 return frames_to_bytes(runtime, 1) / fsi->chan_num;
383 static void fsi_count_fifo_err(struct fsi_priv *fsi)
385 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
386 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
388 if (ostatus & ERR_OVER)
389 fsi->playback.oerr_num++;
391 if (ostatus & ERR_UNDER)
392 fsi->playback.uerr_num++;
394 if (istatus & ERR_OVER)
395 fsi->capture.oerr_num++;
397 if (istatus & ERR_UNDER)
398 fsi->capture.uerr_num++;
400 fsi_reg_write(fsi, DOFF_ST, 0);
401 fsi_reg_write(fsi, DIFF_ST, 0);
408 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
410 int is_play = fsi_stream_is_play(stream);
411 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
413 return io->substream->runtime->dma_area + io->buff_offset;
416 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
421 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
423 for (i = 0; i < num; i++)
424 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
427 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
432 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
435 for (i = 0; i < num; i++)
436 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
439 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
444 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
447 for (i = 0; i < num; i++)
448 fsi_reg_write(fsi, DODT, *(start + i));
451 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
456 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
458 for (i = 0; i < num; i++)
459 *(start + i) = fsi_reg_read(fsi, DIDT);
466 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
468 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
469 struct fsi_master *master = fsi_get_master(fsi);
471 fsi_core_mask_set(master, imsk, data, data);
472 fsi_core_mask_set(master, iemsk, data, data);
475 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
477 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
478 struct fsi_master *master = fsi_get_master(fsi);
480 fsi_core_mask_set(master, imsk, data, 0);
481 fsi_core_mask_set(master, iemsk, data, 0);
484 static u32 fsi_irq_get_status(struct fsi_master *master)
486 return fsi_core_read(master, int_st);
489 static void fsi_irq_clear_status(struct fsi_priv *fsi)
492 struct fsi_master *master = fsi_get_master(fsi);
494 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
495 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
497 /* clear interrupt factor */
498 fsi_core_mask_set(master, int_st, data, 0);
502 * SPDIF master clock function
504 * These functions are used later FSI2
506 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
508 struct fsi_master *master = fsi_get_master(fsi);
511 if (master->core->ver < 2) {
512 pr_err("fsi: register access err (%s)\n", __func__);
517 val = enable ? mask : 0;
520 fsi_core_mask_set(master, a_mclk, mask, val) :
521 fsi_core_mask_set(master, b_mclk, mask, val);
528 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
530 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
531 struct fsi_master *master = fsi_get_master(fsi);
534 fsi_master_mask_set(master, CLK_RST, val, val);
536 fsi_master_mask_set(master, CLK_RST, val, 0);
539 static void fsi_fifo_init(struct fsi_priv *fsi,
541 struct snd_soc_dai *dai)
543 struct fsi_master *master = fsi_get_master(fsi);
544 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
547 /* get on-chip RAM capacity */
548 shift = fsi_master_read(master, FIFO_SZ);
549 shift >>= fsi_get_port_shift(fsi, is_play);
550 shift &= FIFO_SZ_MASK;
551 io->fifo_max_num = 256 << shift;
552 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
555 * The maximum number of sample data varies depending
556 * on the number of channels selected for the format.
558 * FIFOs are used in 4-channel units in 3-channel mode
559 * and in 8-channel units in 5- to 7-channel mode
560 * meaning that more FIFOs than the required size of DPRAM
563 * ex) if 256 words of DP-RAM is connected
564 * 1 channel: 256 (256 x 1 = 256)
565 * 2 channels: 128 (128 x 2 = 256)
566 * 3 channels: 64 ( 64 x 3 = 192)
567 * 4 channels: 64 ( 64 x 4 = 256)
568 * 5 channels: 32 ( 32 x 5 = 160)
569 * 6 channels: 32 ( 32 x 6 = 192)
570 * 7 channels: 32 ( 32 x 7 = 224)
571 * 8 channels: 32 ( 32 x 8 = 256)
573 for (i = 1; i < fsi->chan_num; i <<= 1)
574 io->fifo_max_num >>= 1;
575 dev_dbg(dai->dev, "%d channel %d store\n",
576 fsi->chan_num, io->fifo_max_num);
579 * set interrupt generation factor
583 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
584 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
586 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
587 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
591 static void fsi_soft_all_reset(struct fsi_master *master)
594 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
598 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
599 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
603 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
605 struct snd_pcm_runtime *runtime;
606 struct snd_pcm_substream *substream = NULL;
607 int is_play = fsi_stream_is_play(stream);
608 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
609 int data_residue_num;
614 void (*fn)(struct fsi_priv *fsi, int size);
618 !io->substream->runtime)
622 substream = io->substream;
623 runtime = substream->runtime;
625 /* FSI FIFO has limit.
626 * So, this driver can not send periods data at a time
628 if (io->buff_offset >=
629 fsi_num2offset(io->period_num + 1, io->period_len)) {
632 io->period_num = (io->period_num + 1) % runtime->periods;
634 if (0 == io->period_num)
638 /* get 1 channel data width */
639 ch_width = fsi_get_frame_width(fsi, is_play);
641 /* get residue data number of alsa */
642 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
649 * data_num_max : number of FSI fifo free space
650 * data_num : number of ALSA residue data
652 data_num_max = io->fifo_max_num * fsi->chan_num;
653 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
655 data_num = data_residue_num;
659 fn = fsi_dma_soft_push16;
662 fn = fsi_dma_soft_push32;
671 * data_num_max : number of ALSA free space
672 * data_num : number of data in FSI fifo
674 data_num_max = data_residue_num;
675 data_num = fsi_get_fifo_data_num(fsi, is_play);
679 fn = fsi_dma_soft_pop16;
682 fn = fsi_dma_soft_pop32;
689 data_num = min(data_num, data_num_max);
693 /* update buff_offset */
694 io->buff_offset += fsi_num2offset(data_num, ch_width);
697 snd_pcm_period_elapsed(substream);
702 static int fsi_data_pop(struct fsi_priv *fsi)
704 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
707 static int fsi_data_push(struct fsi_priv *fsi)
709 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
712 static irqreturn_t fsi_interrupt(int irq, void *data)
714 struct fsi_master *master = data;
715 u32 int_st = fsi_irq_get_status(master);
717 /* clear irq status */
718 fsi_master_mask_set(master, SOFT_RST, IR, 0);
719 fsi_master_mask_set(master, SOFT_RST, IR, IR);
721 if (int_st & AB_IO(1, AO_SHIFT))
722 fsi_data_push(&master->fsia);
723 if (int_st & AB_IO(1, BO_SHIFT))
724 fsi_data_push(&master->fsib);
725 if (int_st & AB_IO(1, AI_SHIFT))
726 fsi_data_pop(&master->fsia);
727 if (int_st & AB_IO(1, BI_SHIFT))
728 fsi_data_pop(&master->fsib);
730 fsi_count_fifo_err(&master->fsia);
731 fsi_count_fifo_err(&master->fsib);
733 fsi_irq_clear_status(&master->fsia);
734 fsi_irq_clear_status(&master->fsib);
743 static int fsi_dai_startup(struct snd_pcm_substream *substream,
744 struct snd_soc_dai *dai)
746 struct fsi_priv *fsi = fsi_get_priv(substream);
747 struct fsi_master *master = fsi_get_master(fsi);
748 u32 flags = fsi_get_info_flags(fsi);
751 int is_play = fsi_is_play(substream);
753 pm_runtime_get_sync(dai->dev);
756 /* clock inversion (CKG2) */
758 if (SH_FSI_LRM_INV & flags)
760 if (SH_FSI_BRM_INV & flags)
762 if (SH_FSI_LRS_INV & flags)
764 if (SH_FSI_BRS_INV & flags)
767 fsi_reg_write(fsi, CKG2, data);
771 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
773 case SH_FSI_FMT_MONO:
777 case SH_FSI_FMT_MONO_DELAY:
790 fsi->chan_num = is_play ?
791 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
792 data = CR_TDM | (fsi->chan_num - 1);
794 case SH_FSI_FMT_TDM_DELAY:
795 fsi->chan_num = is_play ?
796 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
797 data = CR_TDM_D | (fsi->chan_num - 1);
799 case SH_FSI_FMT_SPDIF:
800 if (master->core->ver < 2) {
801 dev_err(dai->dev, "This FSI can not use SPDIF\n");
804 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
806 fsi_spdif_clk_ctrl(fsi, 1);
807 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
810 dev_err(dai->dev, "unknown format.\n");
814 fsi_reg_write(fsi, DO_FMT, data) :
815 fsi_reg_write(fsi, DI_FMT, data);
818 fsi_irq_disable(fsi, is_play);
819 fsi_irq_clear_status(fsi);
822 fsi_fifo_init(fsi, is_play, dai);
827 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
828 struct snd_soc_dai *dai)
830 struct fsi_priv *fsi = fsi_get_priv(substream);
831 int is_play = fsi_is_play(substream);
832 struct fsi_master *master = fsi_get_master(fsi);
833 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
835 fsi_irq_disable(fsi, is_play);
836 fsi_clk_ctrl(fsi, 0);
838 set_rate = master->info->set_rate;
839 if (set_rate && fsi->rate)
840 set_rate(dai->dev, fsi_is_port_a(fsi), fsi->rate, 0);
843 pm_runtime_put_sync(dai->dev);
846 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
847 struct snd_soc_dai *dai)
849 struct fsi_priv *fsi = fsi_get_priv(substream);
850 struct snd_pcm_runtime *runtime = substream->runtime;
851 int is_play = fsi_is_play(substream);
855 case SNDRV_PCM_TRIGGER_START:
856 fsi_stream_push(fsi, is_play, substream,
857 frames_to_bytes(runtime, runtime->buffer_size),
858 frames_to_bytes(runtime, runtime->period_size));
859 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
860 fsi_irq_enable(fsi, is_play);
862 case SNDRV_PCM_TRIGGER_STOP:
863 fsi_irq_disable(fsi, is_play);
864 fsi_stream_pop(fsi, is_play);
871 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
873 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
877 pm_runtime_get_sync(dai->dev);
879 /* set master/slave audio interface */
880 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
881 case SND_SOC_DAIFMT_CBM_CFM:
884 case SND_SOC_DAIFMT_CBS_CFS:
890 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
894 pm_runtime_put_sync(dai->dev);
899 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
900 struct snd_pcm_hw_params *params,
901 struct snd_soc_dai *dai)
903 struct fsi_priv *fsi = fsi_get_priv(substream);
904 struct fsi_master *master = fsi_get_master(fsi);
905 int (*set_rate)(struct device *dev, int is_porta, int rate, int enable);
906 int fsi_ver = master->core->ver;
907 long rate = params_rate(params);
910 set_rate = master->info->set_rate;
914 ret = set_rate(dai->dev, fsi_is_port_a(fsi), rate, 1);
915 if (ret < 0) /* error */
922 switch (ret & SH_FSI_ACKMD_MASK) {
925 case SH_FSI_ACKMD_512:
928 case SH_FSI_ACKMD_256:
931 case SH_FSI_ACKMD_128:
934 case SH_FSI_ACKMD_64:
937 case SH_FSI_ACKMD_32:
939 dev_err(dai->dev, "unsupported ACKMD\n");
945 switch (ret & SH_FSI_BPFMD_MASK) {
948 case SH_FSI_BPFMD_32:
951 case SH_FSI_BPFMD_64:
954 case SH_FSI_BPFMD_128:
957 case SH_FSI_BPFMD_256:
960 case SH_FSI_BPFMD_512:
963 case SH_FSI_BPFMD_16:
965 dev_err(dai->dev, "unsupported ACKMD\n");
971 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
973 fsi_clk_ctrl(fsi, 1);
981 static struct snd_soc_dai_ops fsi_dai_ops = {
982 .startup = fsi_dai_startup,
983 .shutdown = fsi_dai_shutdown,
984 .trigger = fsi_dai_trigger,
985 .set_fmt = fsi_dai_set_fmt,
986 .hw_params = fsi_dai_hw_params,
993 static struct snd_pcm_hardware fsi_pcm_hardware = {
994 .info = SNDRV_PCM_INFO_INTERLEAVED |
995 SNDRV_PCM_INFO_MMAP |
996 SNDRV_PCM_INFO_MMAP_VALID |
997 SNDRV_PCM_INFO_PAUSE,
1004 .buffer_bytes_max = 64 * 1024,
1005 .period_bytes_min = 32,
1006 .period_bytes_max = 8192,
1012 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1014 struct snd_pcm_runtime *runtime = substream->runtime;
1017 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1019 ret = snd_pcm_hw_constraint_integer(runtime,
1020 SNDRV_PCM_HW_PARAM_PERIODS);
1025 static int fsi_hw_params(struct snd_pcm_substream *substream,
1026 struct snd_pcm_hw_params *hw_params)
1028 return snd_pcm_lib_malloc_pages(substream,
1029 params_buffer_bytes(hw_params));
1032 static int fsi_hw_free(struct snd_pcm_substream *substream)
1034 return snd_pcm_lib_free_pages(substream);
1037 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 struct fsi_priv *fsi = fsi_get_priv(substream);
1041 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1044 location = (io->buff_offset - 1);
1048 return bytes_to_frames(runtime, location);
1051 static struct snd_pcm_ops fsi_pcm_ops = {
1052 .open = fsi_pcm_open,
1053 .ioctl = snd_pcm_lib_ioctl,
1054 .hw_params = fsi_hw_params,
1055 .hw_free = fsi_hw_free,
1056 .pointer = fsi_pointer,
1063 #define PREALLOC_BUFFER (32 * 1024)
1064 #define PREALLOC_BUFFER_MAX (32 * 1024)
1066 static void fsi_pcm_free(struct snd_pcm *pcm)
1068 snd_pcm_lib_preallocate_free_for_all(pcm);
1071 static int fsi_pcm_new(struct snd_card *card,
1072 struct snd_soc_dai *dai,
1073 struct snd_pcm *pcm)
1076 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1077 * in MMAP mode (i.e. aplay -M)
1079 return snd_pcm_lib_preallocate_pages_for_all(
1081 SNDRV_DMA_TYPE_CONTINUOUS,
1082 snd_dma_continuous_data(GFP_KERNEL),
1083 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1090 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1095 .formats = FSI_FMTS,
1101 .formats = FSI_FMTS,
1105 .ops = &fsi_dai_ops,
1111 .formats = FSI_FMTS,
1117 .formats = FSI_FMTS,
1121 .ops = &fsi_dai_ops,
1125 static struct snd_soc_platform_driver fsi_soc_platform = {
1126 .ops = &fsi_pcm_ops,
1127 .pcm_new = fsi_pcm_new,
1128 .pcm_free = fsi_pcm_free,
1135 static int fsi_probe(struct platform_device *pdev)
1137 struct fsi_master *master;
1138 const struct platform_device_id *id_entry;
1139 struct resource *res;
1143 id_entry = pdev->id_entry;
1145 dev_err(&pdev->dev, "unknown fsi device\n");
1149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 irq = platform_get_irq(pdev, 0);
1151 if (!res || (int)irq <= 0) {
1152 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1157 master = kzalloc(sizeof(*master), GFP_KERNEL);
1159 dev_err(&pdev->dev, "Could not allocate master\n");
1164 master->base = ioremap_nocache(res->start, resource_size(res));
1165 if (!master->base) {
1167 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1171 /* master setting */
1173 master->info = pdev->dev.platform_data;
1174 master->core = (struct fsi_core *)id_entry->driver_data;
1175 spin_lock_init(&master->lock);
1178 master->fsia.base = master->base;
1179 master->fsia.master = master;
1182 master->fsib.base = master->base + 0x40;
1183 master->fsib.master = master;
1185 pm_runtime_enable(&pdev->dev);
1186 pm_runtime_resume(&pdev->dev);
1187 dev_set_drvdata(&pdev->dev, master);
1189 fsi_soft_all_reset(master);
1191 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1192 id_entry->name, master);
1194 dev_err(&pdev->dev, "irq request err\n");
1198 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1200 dev_err(&pdev->dev, "cannot snd soc register\n");
1204 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1207 free_irq(irq, master);
1209 iounmap(master->base);
1210 pm_runtime_disable(&pdev->dev);
1218 static int fsi_remove(struct platform_device *pdev)
1220 struct fsi_master *master;
1222 master = dev_get_drvdata(&pdev->dev);
1224 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1225 snd_soc_unregister_platform(&pdev->dev);
1227 pm_runtime_disable(&pdev->dev);
1229 free_irq(master->irq, master);
1231 iounmap(master->base);
1237 static int fsi_runtime_nop(struct device *dev)
1239 /* Runtime PM callback shared between ->runtime_suspend()
1240 * and ->runtime_resume(). Simply returns success.
1242 * This driver re-initializes all registers after
1243 * pm_runtime_get_sync() anyway so there is no need
1244 * to save and restore registers here.
1249 static struct dev_pm_ops fsi_pm_ops = {
1250 .runtime_suspend = fsi_runtime_nop,
1251 .runtime_resume = fsi_runtime_nop,
1254 static struct fsi_core fsi1_core = {
1263 static struct fsi_core fsi2_core = {
1267 .int_st = CPU_INT_ST,
1270 .a_mclk = A_MST_CTLR,
1271 .b_mclk = B_MST_CTLR,
1274 static struct platform_device_id fsi_id_table[] = {
1275 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1276 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1279 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1281 static struct platform_driver fsi_driver = {
1283 .name = "fsi-pcm-audio",
1287 .remove = fsi_remove,
1288 .id_table = fsi_id_table,
1291 static int __init fsi_mobile_init(void)
1293 return platform_driver_register(&fsi_driver);
1296 static void __exit fsi_mobile_exit(void)
1298 platform_driver_unregister(&fsi_driver);
1301 module_init(fsi_mobile_init);
1302 module_exit(fsi_mobile_exit);
1304 MODULE_LICENSE("GPL");
1305 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1306 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");