2 * Fifo-attached Serial Interface (FSI) support for SH7724
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
36 #define A_MST_CTLR 0x0180
37 #define B_MST_CTLR 0x01A0
38 #define CPU_INT_ST 0x01F4
39 #define CPU_IEMSK 0x01F8
40 #define CPU_IMSK 0x01FC
45 #define CLK_RST 0x0210
46 #define SOFT_RST 0x0214
47 #define FIFO_SZ 0x0218
48 #define MREG_START A_MST_CTLR
49 #define MREG_END FIFO_SZ
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
83 #define BP (1 << 4) /* Fix the signal of Biphase output */
84 #define SE (1 << 0) /* Fix the master clock */
87 #define B_CLK 0x00000010
88 #define A_CLK 0x00000001
90 /* IO SHIFT / MACRO */
95 #define AB_IO(param, shift) (param << shift)
98 #define PBSR (1 << 12) /* Port B Software Reset */
99 #define PASR (1 << 8) /* Port A Software Reset */
100 #define IR (1 << 4) /* Interrupt Reset */
101 #define FSISR (1 << 0) /* Software Reset */
104 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
105 /* 1: Biphase and serial */
108 #define FIFO_SZ_MASK 0x7
110 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
112 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115 * FSI driver use below type name for variable
117 * xxx_len : data length
118 * xxx_width : data width
119 * xxx_offset : data offset
120 * xxx_num : number of data
128 struct snd_pcm_substream *substream;
141 struct fsi_master *master;
143 struct fsi_stream playback;
144 struct fsi_stream capture;
160 struct fsi_priv fsia;
161 struct fsi_priv fsib;
162 struct fsi_core *core;
163 struct sh_fsi_platform_info *info;
168 * basic read write function
171 static void __fsi_reg_write(u32 reg, u32 data)
173 /* valid data area is 24bit */
176 __raw_writel(data, reg);
179 static u32 __fsi_reg_read(u32 reg)
181 return __raw_readl(reg);
184 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
186 u32 val = __fsi_reg_read(reg);
191 __fsi_reg_write(reg, val);
194 #define fsi_reg_write(p, r, d)\
195 __fsi_reg_write((u32)(p->base + REG_##r), d)
197 #define fsi_reg_read(p, r)\
198 __fsi_reg_read((u32)(p->base + REG_##r))
200 #define fsi_reg_mask_set(p, r, m, d)\
201 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
203 static u32 fsi_master_read(struct fsi_master *master, u32 reg)
208 if ((reg < MREG_START) ||
210 pr_err("fsi: register access err (%s)\n", __func__);
214 spin_lock_irqsave(&master->lock, flags);
215 ret = __fsi_reg_read((u32)(master->base + reg));
216 spin_unlock_irqrestore(&master->lock, flags);
221 static void fsi_master_mask_set(struct fsi_master *master,
222 u32 reg, u32 mask, u32 data)
226 if ((reg < MREG_START) ||
228 pr_err("fsi: register access err (%s)\n", __func__);
232 spin_lock_irqsave(&master->lock, flags);
233 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
234 spin_unlock_irqrestore(&master->lock, flags);
241 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
246 static int fsi_is_port_a(struct fsi_priv *fsi)
248 return fsi->master->base == fsi->base;
251 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
253 struct snd_soc_pcm_runtime *rtd = substream->private_data;
258 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
260 struct snd_soc_dai *dai = fsi_get_dai(substream);
261 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
264 return &master->fsia;
266 return &master->fsib;
269 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
271 int is_porta = fsi_is_port_a(fsi);
272 struct fsi_master *master = fsi_get_master(fsi);
274 return is_porta ? master->info->porta_flags :
275 master->info->portb_flags;
278 static inline int fsi_stream_is_play(int stream)
280 return stream == SNDRV_PCM_STREAM_PLAYBACK;
283 static inline int fsi_is_play(struct snd_pcm_substream *substream)
285 return fsi_stream_is_play(substream->stream);
288 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
291 return is_play ? &fsi->playback : &fsi->capture;
294 static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
297 u32 flags = fsi_get_info_flags(fsi);
299 mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
306 return (mode & flags) != mode;
309 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
311 int is_porta = fsi_is_port_a(fsi);
315 shift = is_play ? AO_SHIFT : AI_SHIFT;
317 shift = is_play ? BO_SHIFT : BI_SHIFT;
322 static void fsi_stream_push(struct fsi_priv *fsi,
324 struct snd_pcm_substream *substream,
328 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
330 io->substream = substream;
331 io->buff_len = buffer_len;
333 io->period_len = period_len;
337 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
339 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
341 io->substream = NULL;
348 static int fsi_get_fifo_data_num(struct fsi_priv *fsi, int is_play)
351 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
355 fsi_reg_read(fsi, DOFF_ST) :
356 fsi_reg_read(fsi, DIFF_ST);
358 data_num = 0x1ff & (status >> 8);
359 data_num *= io->chan_num;
364 static int fsi_len2num(int len, int width)
369 #define fsi_num2offset(a, b) fsi_num2len(a, b)
370 static int fsi_num2len(int num, int width)
375 static int fsi_get_frame_width(struct fsi_priv *fsi, int is_play)
377 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
378 struct snd_pcm_substream *substream = io->substream;
379 struct snd_pcm_runtime *runtime = substream->runtime;
381 return frames_to_bytes(runtime, 1) / io->chan_num;
388 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
390 int is_play = fsi_stream_is_play(stream);
391 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
393 return io->substream->runtime->dma_area + io->buff_offset;
396 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
401 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
403 for (i = 0; i < num; i++)
404 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
407 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
412 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
415 for (i = 0; i < num; i++)
416 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
419 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
424 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
427 for (i = 0; i < num; i++)
428 fsi_reg_write(fsi, DODT, *(start + i));
431 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
436 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
438 for (i = 0; i < num; i++)
439 *(start + i) = fsi_reg_read(fsi, DIDT);
446 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
448 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
449 struct fsi_master *master = fsi_get_master(fsi);
451 fsi_master_mask_set(master, master->core->imsk, data, data);
452 fsi_master_mask_set(master, master->core->iemsk, data, data);
455 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
457 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
458 struct fsi_master *master = fsi_get_master(fsi);
460 fsi_master_mask_set(master, master->core->imsk, data, 0);
461 fsi_master_mask_set(master, master->core->iemsk, data, 0);
464 static u32 fsi_irq_get_status(struct fsi_master *master)
466 return fsi_master_read(master, master->core->int_st);
469 static void fsi_irq_clear_status(struct fsi_priv *fsi)
472 struct fsi_master *master = fsi_get_master(fsi);
474 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
475 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
477 /* clear interrupt factor */
478 fsi_master_mask_set(master, master->core->int_st, data, 0);
482 * SPDIF master clock function
484 * These functions are used later FSI2
486 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
488 struct fsi_master *master = fsi_get_master(fsi);
491 if (master->core->ver < 2) {
492 pr_err("fsi: register access err (%s)\n", __func__);
497 val = enable ? mask : 0;
500 fsi_master_mask_set(master, master->core->a_mclk, mask, val) :
501 fsi_master_mask_set(master, master->core->b_mclk, mask, val);
508 static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
510 u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
511 struct fsi_master *master = fsi_get_master(fsi);
514 fsi_master_mask_set(master, CLK_RST, val, val);
516 fsi_master_mask_set(master, CLK_RST, val, 0);
519 static void fsi_fifo_init(struct fsi_priv *fsi,
521 struct snd_soc_dai *dai)
523 struct fsi_master *master = fsi_get_master(fsi);
524 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
527 /* get on-chip RAM capacity */
528 shift = fsi_master_read(master, FIFO_SZ);
529 shift >>= fsi_get_port_shift(fsi, is_play);
530 shift &= FIFO_SZ_MASK;
531 io->fifo_max_num = 256 << shift;
532 dev_dbg(dai->dev, "fifo = %d words\n", io->fifo_max_num);
535 * The maximum number of sample data varies depending
536 * on the number of channels selected for the format.
538 * FIFOs are used in 4-channel units in 3-channel mode
539 * and in 8-channel units in 5- to 7-channel mode
540 * meaning that more FIFOs than the required size of DPRAM
543 * ex) if 256 words of DP-RAM is connected
544 * 1 channel: 256 (256 x 1 = 256)
545 * 2 channels: 128 (128 x 2 = 256)
546 * 3 channels: 64 ( 64 x 3 = 192)
547 * 4 channels: 64 ( 64 x 4 = 256)
548 * 5 channels: 32 ( 32 x 5 = 160)
549 * 6 channels: 32 ( 32 x 6 = 192)
550 * 7 channels: 32 ( 32 x 7 = 224)
551 * 8 channels: 32 ( 32 x 8 = 256)
553 for (i = 1; i < io->chan_num; i <<= 1)
554 io->fifo_max_num >>= 1;
555 dev_dbg(dai->dev, "%d channel %d store\n",
556 io->chan_num, io->fifo_max_num);
559 * set interrupt generation factor
563 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
564 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
566 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
567 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
571 static void fsi_soft_all_reset(struct fsi_master *master)
574 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
578 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
579 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
583 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int startup, int stream)
585 struct snd_pcm_runtime *runtime;
586 struct snd_pcm_substream *substream = NULL;
587 int is_play = fsi_stream_is_play(stream);
588 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
589 int data_residue_num;
594 void (*fn)(struct fsi_priv *fsi, int size);
598 !io->substream->runtime)
602 substream = io->substream;
603 runtime = substream->runtime;
605 /* FSI FIFO has limit.
606 * So, this driver can not send periods data at a time
608 if (io->buff_offset >=
609 fsi_num2offset(io->period_num + 1, io->period_len)) {
612 io->period_num = (io->period_num + 1) % runtime->periods;
614 if (0 == io->period_num)
618 /* get 1 channel data width */
619 ch_width = fsi_get_frame_width(fsi, is_play);
621 /* get residue data number of alsa */
622 data_residue_num = fsi_len2num(io->buff_len - io->buff_offset,
629 * data_num_max : number of FSI fifo free space
630 * data_num : number of ALSA residue data
632 data_num_max = io->fifo_max_num * io->chan_num;
633 data_num_max -= fsi_get_fifo_data_num(fsi, is_play);
635 data_num = data_residue_num;
639 fn = fsi_dma_soft_push16;
642 fn = fsi_dma_soft_push32;
651 * data_num_max : number of ALSA free space
652 * data_num : number of data in FSI fifo
654 data_num_max = data_residue_num;
655 data_num = fsi_get_fifo_data_num(fsi, is_play);
659 fn = fsi_dma_soft_pop16;
662 fn = fsi_dma_soft_pop32;
669 data_num = min(data_num, data_num_max);
673 /* update buff_offset */
674 io->buff_offset += fsi_num2offset(data_num, ch_width);
676 /* check fifo status */
678 struct snd_soc_dai *dai = fsi_get_dai(substream);
679 u32 status = is_play ?
680 fsi_reg_read(fsi, DOFF_ST) :
681 fsi_reg_read(fsi, DIFF_ST);
683 if (status & ERR_OVER)
684 dev_err(dai->dev, "over run\n");
685 if (status & ERR_UNDER)
686 dev_err(dai->dev, "under run\n");
690 fsi_reg_write(fsi, DOFF_ST, 0) :
691 fsi_reg_write(fsi, DIFF_ST, 0);
694 fsi_irq_enable(fsi, is_play);
697 snd_pcm_period_elapsed(substream);
702 static int fsi_data_pop(struct fsi_priv *fsi, int startup)
704 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_CAPTURE);
707 static int fsi_data_push(struct fsi_priv *fsi, int startup)
709 return fsi_fifo_data_ctrl(fsi, startup, SNDRV_PCM_STREAM_PLAYBACK);
712 static irqreturn_t fsi_interrupt(int irq, void *data)
714 struct fsi_master *master = data;
715 u32 int_st = fsi_irq_get_status(master);
717 /* clear irq status */
718 fsi_master_mask_set(master, SOFT_RST, IR, 0);
719 fsi_master_mask_set(master, SOFT_RST, IR, IR);
721 if (int_st & AB_IO(1, AO_SHIFT))
722 fsi_data_push(&master->fsia, 0);
723 if (int_st & AB_IO(1, BO_SHIFT))
724 fsi_data_push(&master->fsib, 0);
725 if (int_st & AB_IO(1, AI_SHIFT))
726 fsi_data_pop(&master->fsia, 0);
727 if (int_st & AB_IO(1, BI_SHIFT))
728 fsi_data_pop(&master->fsib, 0);
730 fsi_irq_clear_status(&master->fsia);
731 fsi_irq_clear_status(&master->fsib);
740 static int fsi_dai_startup(struct snd_pcm_substream *substream,
741 struct snd_soc_dai *dai)
743 struct fsi_priv *fsi = fsi_get_priv(substream);
744 struct fsi_master *master = fsi_get_master(fsi);
745 struct fsi_stream *io;
746 u32 flags = fsi_get_info_flags(fsi);
749 int is_play = fsi_is_play(substream);
752 io = fsi_get_stream(fsi, is_play);
754 pm_runtime_get_sync(dai->dev);
757 data = is_play ? (1 << 0) : (1 << 4);
758 is_master = fsi_is_master_mode(fsi, is_play);
760 fsi_reg_mask_set(fsi, CKG1, data, data);
762 fsi_reg_mask_set(fsi, CKG1, data, 0);
764 /* clock inversion (CKG2) */
766 if (SH_FSI_LRM_INV & flags)
768 if (SH_FSI_BRM_INV & flags)
770 if (SH_FSI_LRS_INV & flags)
772 if (SH_FSI_BRS_INV & flags)
775 fsi_reg_write(fsi, CKG2, data);
779 fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
781 case SH_FSI_FMT_MONO:
785 case SH_FSI_FMT_MONO_DELAY:
798 io->chan_num = is_play ?
799 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
800 data = CR_TDM | (io->chan_num - 1);
802 case SH_FSI_FMT_TDM_DELAY:
803 io->chan_num = is_play ?
804 SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
805 data = CR_TDM_D | (io->chan_num - 1);
807 case SH_FSI_FMT_SPDIF:
808 if (master->core->ver < 2) {
809 dev_err(dai->dev, "This FSI can not use SPDIF\n");
812 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
814 fsi_spdif_clk_ctrl(fsi, 1);
815 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
818 dev_err(dai->dev, "unknown format.\n");
822 fsi_reg_write(fsi, DO_FMT, data) :
823 fsi_reg_write(fsi, DI_FMT, data);
826 fsi_irq_disable(fsi, is_play);
827 fsi_irq_clear_status(fsi);
830 fsi_fifo_init(fsi, is_play, dai);
835 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
836 struct snd_soc_dai *dai)
838 struct fsi_priv *fsi = fsi_get_priv(substream);
839 int is_play = fsi_is_play(substream);
841 fsi_irq_disable(fsi, is_play);
842 fsi_clk_ctrl(fsi, 0);
844 pm_runtime_put_sync(dai->dev);
847 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
848 struct snd_soc_dai *dai)
850 struct fsi_priv *fsi = fsi_get_priv(substream);
851 struct snd_pcm_runtime *runtime = substream->runtime;
852 int is_play = fsi_is_play(substream);
856 case SNDRV_PCM_TRIGGER_START:
857 fsi_stream_push(fsi, is_play, substream,
858 frames_to_bytes(runtime, runtime->buffer_size),
859 frames_to_bytes(runtime, runtime->period_size));
860 ret = is_play ? fsi_data_push(fsi, 1) : fsi_data_pop(fsi, 1);
862 case SNDRV_PCM_TRIGGER_STOP:
863 fsi_irq_disable(fsi, is_play);
864 fsi_stream_pop(fsi, is_play);
871 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
872 struct snd_pcm_hw_params *params,
873 struct snd_soc_dai *dai)
875 struct fsi_priv *fsi = fsi_get_priv(substream);
876 struct fsi_master *master = fsi_get_master(fsi);
877 int (*set_rate)(int is_porta, int rate) = master->info->set_rate;
878 int fsi_ver = master->core->ver;
879 int is_play = fsi_is_play(substream);
882 /* if slave mode, set_rate is not needed */
883 if (!fsi_is_master_mode(fsi, is_play))
886 /* it is error if no set_rate */
890 ret = set_rate(fsi_is_port_a(fsi), params_rate(params));
894 switch (ret & SH_FSI_ACKMD_MASK) {
897 case SH_FSI_ACKMD_512:
900 case SH_FSI_ACKMD_256:
903 case SH_FSI_ACKMD_128:
906 case SH_FSI_ACKMD_64:
909 case SH_FSI_ACKMD_32:
911 dev_err(dai->dev, "unsupported ACKMD\n");
917 switch (ret & SH_FSI_BPFMD_MASK) {
920 case SH_FSI_BPFMD_32:
923 case SH_FSI_BPFMD_64:
926 case SH_FSI_BPFMD_128:
929 case SH_FSI_BPFMD_256:
932 case SH_FSI_BPFMD_512:
935 case SH_FSI_BPFMD_16:
937 dev_err(dai->dev, "unsupported ACKMD\n");
943 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
945 fsi_clk_ctrl(fsi, 1);
953 static struct snd_soc_dai_ops fsi_dai_ops = {
954 .startup = fsi_dai_startup,
955 .shutdown = fsi_dai_shutdown,
956 .trigger = fsi_dai_trigger,
957 .hw_params = fsi_dai_hw_params,
964 static struct snd_pcm_hardware fsi_pcm_hardware = {
965 .info = SNDRV_PCM_INFO_INTERLEAVED |
966 SNDRV_PCM_INFO_MMAP |
967 SNDRV_PCM_INFO_MMAP_VALID |
968 SNDRV_PCM_INFO_PAUSE,
975 .buffer_bytes_max = 64 * 1024,
976 .period_bytes_min = 32,
977 .period_bytes_max = 8192,
983 static int fsi_pcm_open(struct snd_pcm_substream *substream)
985 struct snd_pcm_runtime *runtime = substream->runtime;
988 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
990 ret = snd_pcm_hw_constraint_integer(runtime,
991 SNDRV_PCM_HW_PARAM_PERIODS);
996 static int fsi_hw_params(struct snd_pcm_substream *substream,
997 struct snd_pcm_hw_params *hw_params)
999 return snd_pcm_lib_malloc_pages(substream,
1000 params_buffer_bytes(hw_params));
1003 static int fsi_hw_free(struct snd_pcm_substream *substream)
1005 return snd_pcm_lib_free_pages(substream);
1008 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1010 struct snd_pcm_runtime *runtime = substream->runtime;
1011 struct fsi_priv *fsi = fsi_get_priv(substream);
1012 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1015 location = (io->buff_offset - 1);
1019 return bytes_to_frames(runtime, location);
1022 static struct snd_pcm_ops fsi_pcm_ops = {
1023 .open = fsi_pcm_open,
1024 .ioctl = snd_pcm_lib_ioctl,
1025 .hw_params = fsi_hw_params,
1026 .hw_free = fsi_hw_free,
1027 .pointer = fsi_pointer,
1034 #define PREALLOC_BUFFER (32 * 1024)
1035 #define PREALLOC_BUFFER_MAX (32 * 1024)
1037 static void fsi_pcm_free(struct snd_pcm *pcm)
1039 snd_pcm_lib_preallocate_free_for_all(pcm);
1042 static int fsi_pcm_new(struct snd_card *card,
1043 struct snd_soc_dai *dai,
1044 struct snd_pcm *pcm)
1047 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1048 * in MMAP mode (i.e. aplay -M)
1050 return snd_pcm_lib_preallocate_pages_for_all(
1052 SNDRV_DMA_TYPE_CONTINUOUS,
1053 snd_dma_continuous_data(GFP_KERNEL),
1054 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1061 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1066 .formats = FSI_FMTS,
1072 .formats = FSI_FMTS,
1076 .ops = &fsi_dai_ops,
1082 .formats = FSI_FMTS,
1088 .formats = FSI_FMTS,
1092 .ops = &fsi_dai_ops,
1096 static struct snd_soc_platform_driver fsi_soc_platform = {
1097 .ops = &fsi_pcm_ops,
1098 .pcm_new = fsi_pcm_new,
1099 .pcm_free = fsi_pcm_free,
1106 static int fsi_probe(struct platform_device *pdev)
1108 struct fsi_master *master;
1109 const struct platform_device_id *id_entry;
1110 struct resource *res;
1114 id_entry = pdev->id_entry;
1116 dev_err(&pdev->dev, "unknown fsi device\n");
1120 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1121 irq = platform_get_irq(pdev, 0);
1122 if (!res || (int)irq <= 0) {
1123 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1128 master = kzalloc(sizeof(*master), GFP_KERNEL);
1130 dev_err(&pdev->dev, "Could not allocate master\n");
1135 master->base = ioremap_nocache(res->start, resource_size(res));
1136 if (!master->base) {
1138 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1142 /* master setting */
1144 master->info = pdev->dev.platform_data;
1145 master->core = (struct fsi_core *)id_entry->driver_data;
1146 spin_lock_init(&master->lock);
1149 master->fsia.base = master->base;
1150 master->fsia.master = master;
1153 master->fsib.base = master->base + 0x40;
1154 master->fsib.master = master;
1156 pm_runtime_enable(&pdev->dev);
1157 pm_runtime_resume(&pdev->dev);
1158 dev_set_drvdata(&pdev->dev, master);
1160 fsi_soft_all_reset(master);
1162 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1163 id_entry->name, master);
1165 dev_err(&pdev->dev, "irq request err\n");
1169 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1171 dev_err(&pdev->dev, "cannot snd soc register\n");
1175 return snd_soc_register_dais(&pdev->dev, fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
1178 free_irq(irq, master);
1180 iounmap(master->base);
1181 pm_runtime_disable(&pdev->dev);
1189 static int fsi_remove(struct platform_device *pdev)
1191 struct fsi_master *master;
1193 master = dev_get_drvdata(&pdev->dev);
1195 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1196 snd_soc_unregister_platform(&pdev->dev);
1198 pm_runtime_disable(&pdev->dev);
1200 free_irq(master->irq, master);
1202 iounmap(master->base);
1208 static int fsi_runtime_nop(struct device *dev)
1210 /* Runtime PM callback shared between ->runtime_suspend()
1211 * and ->runtime_resume(). Simply returns success.
1213 * This driver re-initializes all registers after
1214 * pm_runtime_get_sync() anyway so there is no need
1215 * to save and restore registers here.
1220 static struct dev_pm_ops fsi_pm_ops = {
1221 .runtime_suspend = fsi_runtime_nop,
1222 .runtime_resume = fsi_runtime_nop,
1225 static struct fsi_core fsi1_core = {
1234 static struct fsi_core fsi2_core = {
1238 .int_st = CPU_INT_ST,
1241 .a_mclk = A_MST_CTLR,
1242 .b_mclk = B_MST_CTLR,
1245 static struct platform_device_id fsi_id_table[] = {
1246 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1247 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1250 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1252 static struct platform_driver fsi_driver = {
1254 .name = "fsi-pcm-audio",
1258 .remove = fsi_remove,
1259 .id_table = fsi_id_table,
1262 static int __init fsi_mobile_init(void)
1264 return platform_driver_register(&fsi_driver);
1267 static void __exit fsi_mobile_exit(void)
1269 platform_driver_unregister(&fsi_driver);
1272 module_init(fsi_mobile_init);
1273 module_exit(fsi_mobile_exit);
1275 MODULE_LICENSE("GPL");
1276 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1277 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");